xref: /linux/arch/mips/loongson2ef/lemote-2f/ec_kb3310b.h (revision c95baf12f5077419db01313ab61c2aac007d40cd)
1*71e2f4ddSJiaxun Yang /* SPDX-License-Identifier: GPL-2.0-or-later */
2*71e2f4ddSJiaxun Yang /*
3*71e2f4ddSJiaxun Yang  * KB3310B Embedded Controller
4*71e2f4ddSJiaxun Yang  *
5*71e2f4ddSJiaxun Yang  *  Copyright (C) 2008 Lemote Inc.
6*71e2f4ddSJiaxun Yang  *  Author: liujl <liujl@lemote.com>, 2008-03-14
7*71e2f4ddSJiaxun Yang  */
8*71e2f4ddSJiaxun Yang 
9*71e2f4ddSJiaxun Yang #ifndef _EC_KB3310B_H
10*71e2f4ddSJiaxun Yang #define _EC_KB3310B_H
11*71e2f4ddSJiaxun Yang 
12*71e2f4ddSJiaxun Yang extern unsigned char ec_read(unsigned short addr);
13*71e2f4ddSJiaxun Yang extern void ec_write(unsigned short addr, unsigned char val);
14*71e2f4ddSJiaxun Yang extern int ec_query_seq(unsigned char cmd);
15*71e2f4ddSJiaxun Yang extern int ec_query_event_num(void);
16*71e2f4ddSJiaxun Yang extern int ec_get_event_num(void);
17*71e2f4ddSJiaxun Yang 
18*71e2f4ddSJiaxun Yang typedef int (*sci_handler) (int status);
19*71e2f4ddSJiaxun Yang extern sci_handler yeeloong_report_lid_status;
20*71e2f4ddSJiaxun Yang 
21*71e2f4ddSJiaxun Yang #define SCI_IRQ_NUM 0x0A
22*71e2f4ddSJiaxun Yang 
23*71e2f4ddSJiaxun Yang /*
24*71e2f4ddSJiaxun Yang  * The following registers are determined by the EC index configuration.
25*71e2f4ddSJiaxun Yang  * 1, fill the PORT_HIGH as EC register high part.
26*71e2f4ddSJiaxun Yang  * 2, fill the PORT_LOW as EC register low part.
27*71e2f4ddSJiaxun Yang  * 3, fill the PORT_DATA as EC register write data or get the data from it.
28*71e2f4ddSJiaxun Yang  */
29*71e2f4ddSJiaxun Yang #define EC_IO_PORT_HIGH 0x0381
30*71e2f4ddSJiaxun Yang #define EC_IO_PORT_LOW	0x0382
31*71e2f4ddSJiaxun Yang #define EC_IO_PORT_DATA 0x0383
32*71e2f4ddSJiaxun Yang 
33*71e2f4ddSJiaxun Yang /*
34*71e2f4ddSJiaxun Yang  * EC delay time is 500us for register and status access
35*71e2f4ddSJiaxun Yang  */
36*71e2f4ddSJiaxun Yang #define EC_REG_DELAY	500	/* unit : us */
37*71e2f4ddSJiaxun Yang #define EC_CMD_TIMEOUT	0x1000
38*71e2f4ddSJiaxun Yang 
39*71e2f4ddSJiaxun Yang /*
40*71e2f4ddSJiaxun Yang  * EC access port for SCI communication
41*71e2f4ddSJiaxun Yang  */
42*71e2f4ddSJiaxun Yang #define EC_CMD_PORT		0x66
43*71e2f4ddSJiaxun Yang #define EC_STS_PORT		0x66
44*71e2f4ddSJiaxun Yang #define EC_DAT_PORT		0x62
45*71e2f4ddSJiaxun Yang #define CMD_INIT_IDLE_MODE	0xdd
46*71e2f4ddSJiaxun Yang #define CMD_EXIT_IDLE_MODE	0xdf
47*71e2f4ddSJiaxun Yang #define CMD_INIT_RESET_MODE	0xd8
48*71e2f4ddSJiaxun Yang #define CMD_REBOOT_SYSTEM	0x8c
49*71e2f4ddSJiaxun Yang #define CMD_GET_EVENT_NUM	0x84
50*71e2f4ddSJiaxun Yang #define CMD_PROGRAM_PIECE	0xda
51*71e2f4ddSJiaxun Yang 
52*71e2f4ddSJiaxun Yang /* temperature & fan registers */
53*71e2f4ddSJiaxun Yang #define REG_TEMPERATURE_VALUE	0xF458
54*71e2f4ddSJiaxun Yang #define REG_FAN_AUTO_MAN_SWITCH 0xF459
55*71e2f4ddSJiaxun Yang #define BIT_FAN_AUTO		0
56*71e2f4ddSJiaxun Yang #define BIT_FAN_MANUAL		1
57*71e2f4ddSJiaxun Yang #define REG_FAN_CONTROL		0xF4D2
58*71e2f4ddSJiaxun Yang #define BIT_FAN_CONTROL_ON	(1 << 0)
59*71e2f4ddSJiaxun Yang #define BIT_FAN_CONTROL_OFF	(0 << 0)
60*71e2f4ddSJiaxun Yang #define REG_FAN_STATUS		0xF4DA
61*71e2f4ddSJiaxun Yang #define BIT_FAN_STATUS_ON	(1 << 0)
62*71e2f4ddSJiaxun Yang #define BIT_FAN_STATUS_OFF	(0 << 0)
63*71e2f4ddSJiaxun Yang #define REG_FAN_SPEED_HIGH	0xFE22
64*71e2f4ddSJiaxun Yang #define REG_FAN_SPEED_LOW	0xFE23
65*71e2f4ddSJiaxun Yang #define REG_FAN_SPEED_LEVEL	0xF4CC
66*71e2f4ddSJiaxun Yang /* fan speed divider */
67*71e2f4ddSJiaxun Yang #define FAN_SPEED_DIVIDER	480000	/* (60*1000*1000/62.5/2)*/
68*71e2f4ddSJiaxun Yang 
69*71e2f4ddSJiaxun Yang /* battery registers */
70*71e2f4ddSJiaxun Yang #define REG_BAT_DESIGN_CAP_HIGH		0xF77D
71*71e2f4ddSJiaxun Yang #define REG_BAT_DESIGN_CAP_LOW		0xF77E
72*71e2f4ddSJiaxun Yang #define REG_BAT_FULLCHG_CAP_HIGH	0xF780
73*71e2f4ddSJiaxun Yang #define REG_BAT_FULLCHG_CAP_LOW		0xF781
74*71e2f4ddSJiaxun Yang #define REG_BAT_DESIGN_VOL_HIGH		0xF782
75*71e2f4ddSJiaxun Yang #define REG_BAT_DESIGN_VOL_LOW		0xF783
76*71e2f4ddSJiaxun Yang #define REG_BAT_CURRENT_HIGH		0xF784
77*71e2f4ddSJiaxun Yang #define REG_BAT_CURRENT_LOW		0xF785
78*71e2f4ddSJiaxun Yang #define REG_BAT_VOLTAGE_HIGH		0xF786
79*71e2f4ddSJiaxun Yang #define REG_BAT_VOLTAGE_LOW		0xF787
80*71e2f4ddSJiaxun Yang #define REG_BAT_TEMPERATURE_HIGH	0xF788
81*71e2f4ddSJiaxun Yang #define REG_BAT_TEMPERATURE_LOW		0xF789
82*71e2f4ddSJiaxun Yang #define REG_BAT_RELATIVE_CAP_HIGH	0xF492
83*71e2f4ddSJiaxun Yang #define REG_BAT_RELATIVE_CAP_LOW	0xF493
84*71e2f4ddSJiaxun Yang #define REG_BAT_VENDOR			0xF4C4
85*71e2f4ddSJiaxun Yang #define FLAG_BAT_VENDOR_SANYO		0x01
86*71e2f4ddSJiaxun Yang #define FLAG_BAT_VENDOR_SIMPLO		0x02
87*71e2f4ddSJiaxun Yang #define REG_BAT_CELL_COUNT		0xF4C6
88*71e2f4ddSJiaxun Yang #define FLAG_BAT_CELL_3S1P		0x03
89*71e2f4ddSJiaxun Yang #define FLAG_BAT_CELL_3S2P		0x06
90*71e2f4ddSJiaxun Yang #define REG_BAT_CHARGE			0xF4A2
91*71e2f4ddSJiaxun Yang #define FLAG_BAT_CHARGE_DISCHARGE	0x01
92*71e2f4ddSJiaxun Yang #define FLAG_BAT_CHARGE_CHARGE		0x02
93*71e2f4ddSJiaxun Yang #define FLAG_BAT_CHARGE_ACPOWER		0x00
94*71e2f4ddSJiaxun Yang #define REG_BAT_STATUS			0xF4B0
95*71e2f4ddSJiaxun Yang #define BIT_BAT_STATUS_LOW		(1 << 5)
96*71e2f4ddSJiaxun Yang #define BIT_BAT_STATUS_DESTROY		(1 << 2)
97*71e2f4ddSJiaxun Yang #define BIT_BAT_STATUS_FULL		(1 << 1)
98*71e2f4ddSJiaxun Yang #define BIT_BAT_STATUS_IN		(1 << 0)
99*71e2f4ddSJiaxun Yang #define REG_BAT_CHARGE_STATUS		0xF4B1
100*71e2f4ddSJiaxun Yang #define BIT_BAT_CHARGE_STATUS_OVERTEMP	(1 << 2)
101*71e2f4ddSJiaxun Yang #define BIT_BAT_CHARGE_STATUS_PRECHG	(1 << 1)
102*71e2f4ddSJiaxun Yang #define REG_BAT_STATE			0xF482
103*71e2f4ddSJiaxun Yang #define BIT_BAT_STATE_CHARGING		(1 << 1)
104*71e2f4ddSJiaxun Yang #define BIT_BAT_STATE_DISCHARGING	(1 << 0)
105*71e2f4ddSJiaxun Yang #define REG_BAT_POWER			0xF440
106*71e2f4ddSJiaxun Yang #define BIT_BAT_POWER_S3		(1 << 2)
107*71e2f4ddSJiaxun Yang #define BIT_BAT_POWER_ON		(1 << 1)
108*71e2f4ddSJiaxun Yang #define BIT_BAT_POWER_ACIN		(1 << 0)
109*71e2f4ddSJiaxun Yang 
110*71e2f4ddSJiaxun Yang /* other registers */
111*71e2f4ddSJiaxun Yang /* Audio: rd/wr */
112*71e2f4ddSJiaxun Yang #define REG_AUDIO_VOLUME	0xF46C
113*71e2f4ddSJiaxun Yang #define REG_AUDIO_MUTE		0xF4E7
114*71e2f4ddSJiaxun Yang #define REG_AUDIO_BEEP		0xF4D0
115*71e2f4ddSJiaxun Yang /* USB port power or not: rd/wr */
116*71e2f4ddSJiaxun Yang #define REG_USB0_FLAG		0xF461
117*71e2f4ddSJiaxun Yang #define REG_USB1_FLAG		0xF462
118*71e2f4ddSJiaxun Yang #define REG_USB2_FLAG		0xF463
119*71e2f4ddSJiaxun Yang #define BIT_USB_FLAG_ON		1
120*71e2f4ddSJiaxun Yang #define BIT_USB_FLAG_OFF	0
121*71e2f4ddSJiaxun Yang /* LID */
122*71e2f4ddSJiaxun Yang #define REG_LID_DETECT		0xF4BD
123*71e2f4ddSJiaxun Yang #define BIT_LID_DETECT_ON	1
124*71e2f4ddSJiaxun Yang #define BIT_LID_DETECT_OFF	0
125*71e2f4ddSJiaxun Yang /* CRT */
126*71e2f4ddSJiaxun Yang #define REG_CRT_DETECT		0xF4AD
127*71e2f4ddSJiaxun Yang #define BIT_CRT_DETECT_PLUG	1
128*71e2f4ddSJiaxun Yang #define BIT_CRT_DETECT_UNPLUG	0
129*71e2f4ddSJiaxun Yang /* LCD backlight brightness adjust: 9 levels */
130*71e2f4ddSJiaxun Yang #define REG_DISPLAY_BRIGHTNESS	0xF4F5
131*71e2f4ddSJiaxun Yang /* Black screen Status */
132*71e2f4ddSJiaxun Yang #define BIT_DISPLAY_LCD_ON	1
133*71e2f4ddSJiaxun Yang #define BIT_DISPLAY_LCD_OFF	0
134*71e2f4ddSJiaxun Yang /* LCD backlight control: off/restore */
135*71e2f4ddSJiaxun Yang #define REG_BACKLIGHT_CTRL	0xF7BD
136*71e2f4ddSJiaxun Yang #define BIT_BACKLIGHT_ON	1
137*71e2f4ddSJiaxun Yang #define BIT_BACKLIGHT_OFF	0
138*71e2f4ddSJiaxun Yang /* Reset the machine auto-clear: rd/wr */
139*71e2f4ddSJiaxun Yang #define REG_RESET		0xF4EC
140*71e2f4ddSJiaxun Yang #define BIT_RESET_ON		1
141*71e2f4ddSJiaxun Yang /* Light the led: rd/wr */
142*71e2f4ddSJiaxun Yang #define REG_LED			0xF4C8
143*71e2f4ddSJiaxun Yang #define BIT_LED_RED_POWER	(1 << 0)
144*71e2f4ddSJiaxun Yang #define BIT_LED_ORANGE_POWER	(1 << 1)
145*71e2f4ddSJiaxun Yang #define BIT_LED_GREEN_CHARGE	(1 << 2)
146*71e2f4ddSJiaxun Yang #define BIT_LED_RED_CHARGE	(1 << 3)
147*71e2f4ddSJiaxun Yang #define BIT_LED_NUMLOCK		(1 << 4)
148*71e2f4ddSJiaxun Yang /* Test led mode, all led on/off */
149*71e2f4ddSJiaxun Yang #define REG_LED_TEST		0xF4C2
150*71e2f4ddSJiaxun Yang #define BIT_LED_TEST_IN		1
151*71e2f4ddSJiaxun Yang #define BIT_LED_TEST_OUT	0
152*71e2f4ddSJiaxun Yang /* Camera on/off */
153*71e2f4ddSJiaxun Yang #define REG_CAMERA_STATUS	0xF46A
154*71e2f4ddSJiaxun Yang #define BIT_CAMERA_STATUS_ON	1
155*71e2f4ddSJiaxun Yang #define BIT_CAMERA_STATUS_OFF	0
156*71e2f4ddSJiaxun Yang #define REG_CAMERA_CONTROL	0xF7B7
157*71e2f4ddSJiaxun Yang #define BIT_CAMERA_CONTROL_OFF	0
158*71e2f4ddSJiaxun Yang #define BIT_CAMERA_CONTROL_ON	1
159*71e2f4ddSJiaxun Yang /* Wlan Status */
160*71e2f4ddSJiaxun Yang #define REG_WLAN		0xF4FA
161*71e2f4ddSJiaxun Yang #define BIT_WLAN_ON		1
162*71e2f4ddSJiaxun Yang #define BIT_WLAN_OFF		0
163*71e2f4ddSJiaxun Yang #define REG_DISPLAY_LCD		0xF79F
164*71e2f4ddSJiaxun Yang 
165*71e2f4ddSJiaxun Yang /* SCI Event Number from EC */
166*71e2f4ddSJiaxun Yang enum {
167*71e2f4ddSJiaxun Yang 	EVENT_LID = 0x23,	/*  LID open/close */
168*71e2f4ddSJiaxun Yang 	EVENT_DISPLAY_TOGGLE,	/*  Fn+F3 for display switch */
169*71e2f4ddSJiaxun Yang 	EVENT_SLEEP,		/*  Fn+F1 for entering sleep mode */
170*71e2f4ddSJiaxun Yang 	EVENT_OVERTEMP,		/*  Over-temperature happened */
171*71e2f4ddSJiaxun Yang 	EVENT_CRT_DETECT,	/*  CRT is connected */
172*71e2f4ddSJiaxun Yang 	EVENT_CAMERA,		/*  Camera on/off */
173*71e2f4ddSJiaxun Yang 	EVENT_USB_OC2,		/*  USB2 Over Current occurred */
174*71e2f4ddSJiaxun Yang 	EVENT_USB_OC0,		/*  USB0 Over Current occurred */
175*71e2f4ddSJiaxun Yang 	EVENT_BLACK_SCREEN,	/*  Turn on/off backlight */
176*71e2f4ddSJiaxun Yang 	EVENT_AUDIO_MUTE,	/*  Mute on/off */
177*71e2f4ddSJiaxun Yang 	EVENT_DISPLAY_BRIGHTNESS,/* LCD backlight brightness adjust */
178*71e2f4ddSJiaxun Yang 	EVENT_AC_BAT,		/*  AC & Battery relative issue */
179*71e2f4ddSJiaxun Yang 	EVENT_AUDIO_VOLUME,	/*  Volume adjust */
180*71e2f4ddSJiaxun Yang 	EVENT_WLAN,		/*  Wlan on/off */
181*71e2f4ddSJiaxun Yang 	EVENT_END
182*71e2f4ddSJiaxun Yang };
183*71e2f4ddSJiaxun Yang 
184*71e2f4ddSJiaxun Yang #endif /* !_EC_KB3310B_H */
185