1/* 2 * This file is subject to the terms and conditions of the GNU General Public 3 * License. See the file "COPYING" in the main directory of this archive 4 * for more details. 5 * 6 * Copyright (C) 1998, 1999, 2000 by Ralf Baechle 7 * Copyright (C) 1999, 2000 Silicon Graphics, Inc. 8 * Copyright (C) 2007 by Maciej W. Rozycki 9 * Copyright (C) 2011, 2012 MIPS Technologies, Inc. 10 */ 11#include <linux/export.h> 12#include <asm/asm.h> 13#include <asm/asm-offsets.h> 14#include <asm/regdef.h> 15 16#if LONGSIZE == 4 17#define LONG_S_L swl 18#define LONG_S_R swr 19#else 20#define LONG_S_L sdl 21#define LONG_S_R sdr 22#endif 23 24#ifdef CONFIG_CPU_MICROMIPS 25#define STORSIZE (LONGSIZE * 2) 26#define STORMASK (STORSIZE - 1) 27#define FILL64RG t8 28#define FILLPTRG t7 29#undef LONG_S 30#define LONG_S LONG_SP 31#else 32#define STORSIZE LONGSIZE 33#define STORMASK LONGMASK 34#define FILL64RG a1 35#define FILLPTRG t0 36#endif 37 38#define LEGACY_MODE 1 39#define EVA_MODE 2 40 41/* 42 * No need to protect it with EVA #ifdefery. The generated block of code 43 * will never be assembled if EVA is not enabled. 44 */ 45#define __EVAFY(insn, reg, addr) __BUILD_EVA_INSN(insn##e, reg, addr) 46#define ___BUILD_EVA_INSN(insn, reg, addr) __EVAFY(insn, reg, addr) 47 48#define EX(insn,reg,addr,handler) \ 49 .if \mode == LEGACY_MODE; \ 509: insn reg, addr; \ 51 .else; \ 529: ___BUILD_EVA_INSN(insn, reg, addr); \ 53 .endif; \ 54 .section __ex_table,"a"; \ 55 PTR_WD 9b, handler; \ 56 .previous 57 58 .macro f_fill64 dst, offset, val, fixup, mode 59 EX(LONG_S, \val, (\offset + 0 * STORSIZE)(\dst), \fixup) 60 EX(LONG_S, \val, (\offset + 1 * STORSIZE)(\dst), \fixup) 61 EX(LONG_S, \val, (\offset + 2 * STORSIZE)(\dst), \fixup) 62 EX(LONG_S, \val, (\offset + 3 * STORSIZE)(\dst), \fixup) 63#if ((defined(CONFIG_CPU_MICROMIPS) && (LONGSIZE == 4)) || !defined(CONFIG_CPU_MICROMIPS)) 64 EX(LONG_S, \val, (\offset + 4 * STORSIZE)(\dst), \fixup) 65 EX(LONG_S, \val, (\offset + 5 * STORSIZE)(\dst), \fixup) 66 EX(LONG_S, \val, (\offset + 6 * STORSIZE)(\dst), \fixup) 67 EX(LONG_S, \val, (\offset + 7 * STORSIZE)(\dst), \fixup) 68#endif 69#if (!defined(CONFIG_CPU_MICROMIPS) && (LONGSIZE == 4)) 70 EX(LONG_S, \val, (\offset + 8 * STORSIZE)(\dst), \fixup) 71 EX(LONG_S, \val, (\offset + 9 * STORSIZE)(\dst), \fixup) 72 EX(LONG_S, \val, (\offset + 10 * STORSIZE)(\dst), \fixup) 73 EX(LONG_S, \val, (\offset + 11 * STORSIZE)(\dst), \fixup) 74 EX(LONG_S, \val, (\offset + 12 * STORSIZE)(\dst), \fixup) 75 EX(LONG_S, \val, (\offset + 13 * STORSIZE)(\dst), \fixup) 76 EX(LONG_S, \val, (\offset + 14 * STORSIZE)(\dst), \fixup) 77 EX(LONG_S, \val, (\offset + 15 * STORSIZE)(\dst), \fixup) 78#endif 79 .endm 80 81 .align 5 82 83 /* 84 * Macro to generate the __bzero{,_user} symbol 85 * Arguments: 86 * mode: LEGACY_MODE or EVA_MODE 87 */ 88 .macro __BUILD_BZERO mode 89 /* Initialize __memset if this is the first time we call this macro */ 90 .ifnotdef __memset 91 .set __memset, 1 92 .endif 93 94 sltiu t0, a2, STORSIZE /* very small region? */ 95 .set noreorder 96 bnez t0, .Lsmall_memset\@ 97 andi t0, a0, STORMASK /* aligned? */ 98 .set reorder 99 100#ifdef CONFIG_CPU_MICROMIPS 101 move t8, a1 /* used by 'swp' instruction */ 102 move t9, a1 103#endif 104 .set noreorder 105#ifndef CONFIG_CPU_DADDI_WORKAROUNDS 106 beqz t0, 1f 107 PTR_SUBU t0, STORSIZE /* alignment in bytes */ 108#else 109 .set noat 110 li AT, STORSIZE 111 beqz t0, 1f 112 PTR_SUBU t0, AT /* alignment in bytes */ 113 .set at 114#endif 115 .set reorder 116 117#ifndef CONFIG_CPU_NO_LOAD_STORE_LR 118 R10KCBARRIER(0(ra)) 119#ifdef __MIPSEB__ 120 EX(LONG_S_L, a1, (a0), .Lfirst_fixup\@) /* make word/dword aligned */ 121#else 122 EX(LONG_S_R, a1, (a0), .Lfirst_fixup\@) /* make word/dword aligned */ 123#endif 124 PTR_SUBU a0, t0 /* long align ptr */ 125 PTR_ADDU a2, t0 /* correct size */ 126 127#else /* CONFIG_CPU_NO_LOAD_STORE_LR */ 128#define STORE_BYTE(N) \ 129 EX(sb, a1, N(a0), .Lbyte_fixup\@); \ 130 .set noreorder; \ 131 beqz t0, 0f; \ 132 PTR_ADDU t0, 1; \ 133 .set reorder; 134 135 PTR_ADDU a2, t0 /* correct size */ 136 PTR_ADDU t0, 1 137 STORE_BYTE(0) 138 STORE_BYTE(1) 139#if LONGSIZE == 4 140 EX(sb, a1, 2(a0), .Lbyte_fixup\@) 141#else 142 STORE_BYTE(2) 143 STORE_BYTE(3) 144 STORE_BYTE(4) 145 STORE_BYTE(5) 146 EX(sb, a1, 6(a0), .Lbyte_fixup\@) 147#endif 1480: 149 ori a0, STORMASK 150 xori a0, STORMASK 151 PTR_ADDIU a0, STORSIZE 152#endif /* CONFIG_CPU_NO_LOAD_STORE_LR */ 1531: ori t1, a2, 0x3f /* # of full blocks */ 154 xori t1, 0x3f 155 andi t0, a2, 0x40-STORSIZE 156 beqz t1, .Lmemset_partial\@ /* no block to fill */ 157 158 PTR_ADDU t1, a0 /* end address */ 1591: PTR_ADDIU a0, 64 160 R10KCBARRIER(0(ra)) 161 f_fill64 a0, -64, FILL64RG, .Lfwd_fixup\@, \mode 162 bne t1, a0, 1b 163 164.Lmemset_partial\@: 165 R10KCBARRIER(0(ra)) 166 PTR_LA t1, 2f /* where to start */ 167#ifdef CONFIG_CPU_MICROMIPS 168 LONG_SRL t7, t0, 1 169#endif 170#if LONGSIZE == 4 171 PTR_SUBU t1, FILLPTRG 172#else 173 .set noat 174 LONG_SRL AT, FILLPTRG, 1 175 PTR_SUBU t1, AT 176 .set at 177#endif 178 PTR_ADDU a0, t0 /* dest ptr */ 179 jr t1 180 181 /* ... but first do longs ... */ 182 f_fill64 a0, -64, FILL64RG, .Lpartial_fixup\@, \mode 1832: andi a2, STORMASK /* At most one long to go */ 184 185 .set noreorder 186 beqz a2, 1f 187#ifndef CONFIG_CPU_NO_LOAD_STORE_LR 188 PTR_ADDU a0, a2 /* What's left */ 189 .set reorder 190 R10KCBARRIER(0(ra)) 191#ifdef __MIPSEB__ 192 EX(LONG_S_R, a1, -1(a0), .Llast_fixup\@) 193#else 194 EX(LONG_S_L, a1, -1(a0), .Llast_fixup\@) 195#endif 196#else /* CONFIG_CPU_NO_LOAD_STORE_LR */ 197 PTR_SUBU t0, $0, a2 198 .set reorder 199 move a2, zero /* No remaining longs */ 200 PTR_ADDIU t0, 1 201 STORE_BYTE(0) 202 STORE_BYTE(1) 203#if LONGSIZE == 4 204 EX(sb, a1, 2(a0), .Lbyte_fixup\@) 205#else 206 STORE_BYTE(2) 207 STORE_BYTE(3) 208 STORE_BYTE(4) 209 STORE_BYTE(5) 210 EX(sb, a1, 6(a0), .Lbyte_fixup\@) 211#endif 2120: 213#endif /* CONFIG_CPU_NO_LOAD_STORE_LR */ 2141: move a2, zero 215 jr ra 216 217.Lsmall_memset\@: 218 PTR_ADDU t1, a0, a2 219 beqz a2, 2f 220 2211: PTR_ADDIU a0, 1 /* fill bytewise */ 222 R10KCBARRIER(0(ra)) 223 .set noreorder 224 bne t1, a0, 1b 225 EX(sb, a1, -1(a0), .Lsmall_fixup\@) 226 .set reorder 227 2282: move a2, zero 229 jr ra /* done */ 230 .if __memset == 1 231 END(memset) 232 .set __memset, 0 233 .endif 234 235#ifdef CONFIG_CPU_NO_LOAD_STORE_LR 236.Lbyte_fixup\@: 237 /* 238 * unset_bytes = (#bytes - (#unaligned bytes)) - (-#unaligned bytes remaining + 1) + 1 239 * a2 = a2 - t0 + 1 240 */ 241 PTR_SUBU a2, t0 242 PTR_ADDIU a2, 1 243 jr ra 244#endif /* CONFIG_CPU_NO_LOAD_STORE_LR */ 245 246.Lfirst_fixup\@: 247 /* unset_bytes already in a2 */ 248 jr ra 249 250.Lfwd_fixup\@: 251 /* 252 * unset_bytes = partial_start_addr + #bytes - fault_addr 253 * a2 = t1 + (a2 & 3f) - $28->task->BUADDR 254 */ 255 PTR_L t0, TI_TASK($28) 256 andi a2, 0x3f 257 LONG_L t0, THREAD_BUADDR(t0) 258 LONG_ADDU a2, t1 259 LONG_SUBU a2, t0 260 jr ra 261 262.Lpartial_fixup\@: 263 /* 264 * unset_bytes = partial_end_addr + #bytes - fault_addr 265 * a2 = a0 + (a2 & STORMASK) - $28->task->BUADDR 266 */ 267 PTR_L t0, TI_TASK($28) 268 andi a2, STORMASK 269 LONG_L t0, THREAD_BUADDR(t0) 270 LONG_ADDU a2, a0 271 LONG_SUBU a2, t0 272 jr ra 273 274.Llast_fixup\@: 275 /* unset_bytes already in a2 */ 276 jr ra 277 278.Lsmall_fixup\@: 279 /* 280 * unset_bytes = end_addr - current_addr + 1 281 * a2 = t1 - a0 + 1 282 */ 283 PTR_SUBU a2, t1, a0 284 PTR_ADDIU a2, 1 285 jr ra 286 287 .endm 288 289/* 290 * memset(void *s, int c, size_t n) 291 * 292 * a0: start of area to clear 293 * a1: char to fill with 294 * a2: size of area to clear 295 */ 296 297LEAF(memset) 298EXPORT_SYMBOL(memset) 299 move v0, a0 /* result */ 300 beqz a1, 1f 301 302 andi a1, 0xff /* spread fillword */ 303 LONG_SLL t1, a1, 8 304 or a1, t1 305 LONG_SLL t1, a1, 16 306#if LONGSIZE == 8 307 or a1, t1 308 LONG_SLL t1, a1, 32 309#endif 310 or a1, t1 3111: 312#ifndef CONFIG_EVA 313FEXPORT(__bzero) 314EXPORT_SYMBOL(__bzero) 315#endif 316 __BUILD_BZERO LEGACY_MODE 317 318#ifdef CONFIG_EVA 319LEAF(__bzero) 320EXPORT_SYMBOL(__bzero) 321 __BUILD_BZERO EVA_MODE 322END(__bzero) 323#endif 324