1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * 4 * Copyright (C) 2011 Thomas Langer <thomas.langer@lantiq.com> 5 * Copyright (C) 2011 John Crispin <john@phrozen.org> 6 */ 7 8 #include <linux/ioport.h> 9 #include <linux/export.h> 10 #include <linux/clkdev.h> 11 #include <linux/of_address.h> 12 #include <asm/delay.h> 13 14 #include <lantiq_soc.h> 15 16 #include "../clk.h" 17 #include "../prom.h" 18 19 /* infrastructure control register */ 20 #define SYS1_INFRAC 0x00bc 21 /* Configuration fuses for drivers and pll */ 22 #define STATUS_CONFIG 0x0040 23 24 /* GPE frequency selection */ 25 #define GPPC_OFFSET 24 26 #define GPEFREQ_MASK 0x0000C00 27 #define GPEFREQ_OFFSET 10 28 /* Clock status register */ 29 #define SYSCTL_CLKS 0x0000 30 /* Clock enable register */ 31 #define SYSCTL_CLKEN 0x0004 32 /* Clock clear register */ 33 #define SYSCTL_CLKCLR 0x0008 34 /* Activation Status Register */ 35 #define SYSCTL_ACTS 0x0020 36 /* Activation Register */ 37 #define SYSCTL_ACT 0x0024 38 /* Deactivation Register */ 39 #define SYSCTL_DEACT 0x0028 40 /* reboot Register */ 41 #define SYSCTL_RBT 0x002c 42 /* CPU0 Clock Control Register */ 43 #define SYS1_CPU0CC 0x0040 44 /* HRST_OUT_N Control Register */ 45 #define SYS1_HRSTOUTC 0x00c0 46 /* clock divider bit */ 47 #define CPU0CC_CPUDIV 0x0001 48 49 /* Activation Status Register */ 50 #define ACTS_ASC0_ACT 0x00001000 51 #define ACTS_SSC0 0x00002000 52 #define ACTS_ASC1_ACT 0x00000800 53 #define ACTS_I2C_ACT 0x00004000 54 #define ACTS_P0 0x00010000 55 #define ACTS_P1 0x00010000 56 #define ACTS_P2 0x00020000 57 #define ACTS_P3 0x00020000 58 #define ACTS_P4 0x00040000 59 #define ACTS_PADCTRL0 0x00100000 60 #define ACTS_PADCTRL1 0x00100000 61 #define ACTS_PADCTRL2 0x00200000 62 #define ACTS_PADCTRL3 0x00200000 63 #define ACTS_PADCTRL4 0x00400000 64 65 #define sysctl_w32(m, x, y) ltq_w32((x), sysctl_membase[m] + (y)) 66 #define sysctl_r32(m, x) ltq_r32(sysctl_membase[m] + (x)) 67 #define sysctl_w32_mask(m, clear, set, reg) \ 68 sysctl_w32(m, (sysctl_r32(m, reg) & ~(clear)) | (set), reg) 69 70 #define status_w32(x, y) ltq_w32((x), status_membase + (y)) 71 #define status_r32(x) ltq_r32(status_membase + (x)) 72 73 static void __iomem *sysctl_membase[3], *status_membase; 74 void __iomem *ltq_sys1_membase, *ltq_ebu_membase; 75 76 static inline void sysctl_wait(struct clk *clk, 77 unsigned int test, unsigned int reg) 78 { 79 int err = 1000000; 80 81 do {} while (--err && ((sysctl_r32(clk->module, reg) 82 & clk->bits) != test)); 83 if (!err) 84 pr_err("module de/activation failed %d %08X %08X %08X\n", 85 clk->module, clk->bits, test, 86 sysctl_r32(clk->module, reg) & clk->bits); 87 } 88 89 static int sysctl_activate(struct clk *clk) 90 { 91 sysctl_w32(clk->module, clk->bits, SYSCTL_CLKEN); 92 sysctl_w32(clk->module, clk->bits, SYSCTL_ACT); 93 sysctl_wait(clk, clk->bits, SYSCTL_ACTS); 94 return 0; 95 } 96 97 static void sysctl_deactivate(struct clk *clk) 98 { 99 sysctl_w32(clk->module, clk->bits, SYSCTL_CLKCLR); 100 sysctl_w32(clk->module, clk->bits, SYSCTL_DEACT); 101 sysctl_wait(clk, 0, SYSCTL_ACTS); 102 } 103 104 static int sysctl_clken(struct clk *clk) 105 { 106 sysctl_w32(clk->module, clk->bits, SYSCTL_CLKEN); 107 sysctl_w32(clk->module, clk->bits, SYSCTL_ACT); 108 sysctl_wait(clk, clk->bits, SYSCTL_CLKS); 109 return 0; 110 } 111 112 static void sysctl_clkdis(struct clk *clk) 113 { 114 sysctl_w32(clk->module, clk->bits, SYSCTL_CLKCLR); 115 sysctl_wait(clk, 0, SYSCTL_CLKS); 116 } 117 118 static void sysctl_reboot(struct clk *clk) 119 { 120 unsigned int act; 121 unsigned int bits; 122 123 act = sysctl_r32(clk->module, SYSCTL_ACT); 124 bits = ~act & clk->bits; 125 if (bits != 0) { 126 sysctl_w32(clk->module, bits, SYSCTL_CLKEN); 127 sysctl_w32(clk->module, bits, SYSCTL_ACT); 128 sysctl_wait(clk, bits, SYSCTL_ACTS); 129 } 130 sysctl_w32(clk->module, act & clk->bits, SYSCTL_RBT); 131 sysctl_wait(clk, clk->bits, SYSCTL_ACTS); 132 } 133 134 /* enable the ONU core */ 135 static void falcon_gpe_enable(void) 136 { 137 unsigned int freq; 138 unsigned int status; 139 140 /* if the clock is already enabled */ 141 status = sysctl_r32(SYSCTL_SYS1, SYS1_INFRAC); 142 if (status & (1 << (GPPC_OFFSET + 1))) 143 return; 144 145 freq = (status_r32(STATUS_CONFIG) & 146 GPEFREQ_MASK) >> 147 GPEFREQ_OFFSET; 148 if (freq == 0) 149 freq = 1; /* use 625MHz on unfused chip */ 150 151 /* apply new frequency */ 152 sysctl_w32_mask(SYSCTL_SYS1, 7 << (GPPC_OFFSET + 1), 153 freq << (GPPC_OFFSET + 2) , SYS1_INFRAC); 154 udelay(1); 155 156 /* enable new frequency */ 157 sysctl_w32_mask(SYSCTL_SYS1, 0, 1 << (GPPC_OFFSET + 1), SYS1_INFRAC); 158 udelay(1); 159 } 160 161 static inline void clkdev_add_sys(const char *dev, unsigned int module, 162 unsigned int bits) 163 { 164 struct clk *clk = kzalloc(sizeof(struct clk), GFP_KERNEL); 165 166 if (!clk) 167 return; 168 clk->cl.dev_id = dev; 169 clk->cl.con_id = NULL; 170 clk->cl.clk = clk; 171 clk->module = module; 172 clk->bits = bits; 173 clk->activate = sysctl_activate; 174 clk->deactivate = sysctl_deactivate; 175 clk->enable = sysctl_clken; 176 clk->disable = sysctl_clkdis; 177 clk->reboot = sysctl_reboot; 178 clkdev_add(&clk->cl); 179 } 180 181 void __init ltq_soc_init(void) 182 { 183 struct device_node *np_status = 184 of_find_compatible_node(NULL, NULL, "lantiq,status-falcon"); 185 struct device_node *np_ebu = 186 of_find_compatible_node(NULL, NULL, "lantiq,ebu-falcon"); 187 struct device_node *np_sys1 = 188 of_find_compatible_node(NULL, NULL, "lantiq,sys1-falcon"); 189 struct device_node *np_syseth = 190 of_find_compatible_node(NULL, NULL, "lantiq,syseth-falcon"); 191 struct device_node *np_sysgpe = 192 of_find_compatible_node(NULL, NULL, "lantiq,sysgpe-falcon"); 193 struct resource res_status, res_ebu, res_sys[3]; 194 int i; 195 196 /* check if all the core register ranges are available */ 197 if (!np_status || !np_ebu || !np_sys1 || !np_syseth || !np_sysgpe) 198 panic("Failed to load core nodes from devicetree"); 199 200 if (of_address_to_resource(np_status, 0, &res_status) || 201 of_address_to_resource(np_ebu, 0, &res_ebu) || 202 of_address_to_resource(np_sys1, 0, &res_sys[0]) || 203 of_address_to_resource(np_syseth, 0, &res_sys[1]) || 204 of_address_to_resource(np_sysgpe, 0, &res_sys[2])) 205 panic("Failed to get core resources"); 206 207 of_node_put(np_status); 208 of_node_put(np_ebu); 209 of_node_put(np_sys1); 210 of_node_put(np_syseth); 211 of_node_put(np_sysgpe); 212 213 if ((!request_mem_region(res_status.start, resource_size(&res_status), 214 res_status.name)) || 215 (!request_mem_region(res_ebu.start, resource_size(&res_ebu), 216 res_ebu.name)) || 217 (!request_mem_region(res_sys[0].start, resource_size(&res_sys[0]), 218 res_sys[0].name)) || 219 (!request_mem_region(res_sys[1].start, resource_size(&res_sys[1]), 220 res_sys[1].name)) || 221 (!request_mem_region(res_sys[2].start, resource_size(&res_sys[2]), 222 res_sys[2].name))) 223 pr_err("Failed to request core resources"); 224 225 status_membase = ioremap(res_status.start, 226 resource_size(&res_status)); 227 ltq_ebu_membase = ioremap(res_ebu.start, 228 resource_size(&res_ebu)); 229 230 if (!status_membase || !ltq_ebu_membase) 231 panic("Failed to remap core resources"); 232 233 for (i = 0; i < 3; i++) { 234 sysctl_membase[i] = ioremap(res_sys[i].start, 235 resource_size(&res_sys[i])); 236 if (!sysctl_membase[i]) 237 panic("Failed to remap sysctrl resources"); 238 } 239 ltq_sys1_membase = sysctl_membase[0]; 240 241 falcon_gpe_enable(); 242 243 /* get our 3 static rates for cpu, fpi and io clocks */ 244 if (ltq_sys1_r32(SYS1_CPU0CC) & CPU0CC_CPUDIV) 245 clkdev_add_static(CLOCK_200M, CLOCK_100M, CLOCK_200M, 0); 246 else 247 clkdev_add_static(CLOCK_400M, CLOCK_100M, CLOCK_200M, 0); 248 249 /* add our clock domains */ 250 clkdev_add_sys("1d810000.gpio", SYSCTL_SYSETH, ACTS_P0); 251 clkdev_add_sys("1d810100.gpio", SYSCTL_SYSETH, ACTS_P2); 252 clkdev_add_sys("1e800100.gpio", SYSCTL_SYS1, ACTS_P1); 253 clkdev_add_sys("1e800200.gpio", SYSCTL_SYS1, ACTS_P3); 254 clkdev_add_sys("1e800300.gpio", SYSCTL_SYS1, ACTS_P4); 255 clkdev_add_sys("1db01000.pad", SYSCTL_SYSETH, ACTS_PADCTRL0); 256 clkdev_add_sys("1db02000.pad", SYSCTL_SYSETH, ACTS_PADCTRL2); 257 clkdev_add_sys("1e800400.pad", SYSCTL_SYS1, ACTS_PADCTRL1); 258 clkdev_add_sys("1e800500.pad", SYSCTL_SYS1, ACTS_PADCTRL3); 259 clkdev_add_sys("1e800600.pad", SYSCTL_SYS1, ACTS_PADCTRL4); 260 clkdev_add_sys("1e100b00.serial", SYSCTL_SYS1, ACTS_ASC1_ACT); 261 clkdev_add_sys("1e100c00.serial", SYSCTL_SYS1, ACTS_ASC0_ACT); 262 clkdev_add_sys("1e100d00.spi", SYSCTL_SYS1, ACTS_SSC0); 263 clkdev_add_sys("1e200000.i2c", SYSCTL_SYS1, ACTS_I2C_ACT); 264 } 265