1 /* 2 * This file is subject to the terms and conditions of the GNU General Public 3 * License. See the file "COPYING" in the main directory of this archive 4 * for more details. 5 * 6 * Generation of main entry point for the guest, exception handling. 7 * 8 * Copyright (C) 2012 MIPS Technologies, Inc. 9 * Authors: Sanjay Lal <sanjayl@kymasys.com> 10 * 11 * Copyright (C) 2016 Imagination Technologies Ltd. 12 */ 13 14 #include <linux/kvm_host.h> 15 #include <linux/log2.h> 16 #include <asm/mmu_context.h> 17 #include <asm/msa.h> 18 #include <asm/setup.h> 19 #include <asm/tlbex.h> 20 #include <asm/uasm.h> 21 22 /* Register names */ 23 #define ZERO 0 24 #define AT 1 25 #define V0 2 26 #define V1 3 27 #define A0 4 28 #define A1 5 29 30 #if _MIPS_SIM == _MIPS_SIM_ABI32 31 #define T0 8 32 #define T1 9 33 #define T2 10 34 #define T3 11 35 #endif /* _MIPS_SIM == _MIPS_SIM_ABI32 */ 36 37 #if _MIPS_SIM == _MIPS_SIM_ABI64 || _MIPS_SIM == _MIPS_SIM_NABI32 38 #define T0 12 39 #define T1 13 40 #define T2 14 41 #define T3 15 42 #endif /* _MIPS_SIM == _MIPS_SIM_ABI64 || _MIPS_SIM == _MIPS_SIM_NABI32 */ 43 44 #define S0 16 45 #define S1 17 46 #define T9 25 47 #define K0 26 48 #define K1 27 49 #define GP 28 50 #define SP 29 51 #define RA 31 52 53 /* Some CP0 registers */ 54 #define C0_PWBASE 5, 5 55 #define C0_HWRENA 7, 0 56 #define C0_BADVADDR 8, 0 57 #define C0_BADINSTR 8, 1 58 #define C0_BADINSTRP 8, 2 59 #define C0_PGD 9, 7 60 #define C0_ENTRYHI 10, 0 61 #define C0_GUESTCTL1 10, 4 62 #define C0_STATUS 12, 0 63 #define C0_GUESTCTL0 12, 6 64 #define C0_CAUSE 13, 0 65 #define C0_EPC 14, 0 66 #define C0_EBASE 15, 1 67 #define C0_CONFIG5 16, 5 68 #define C0_DDATA_LO 28, 3 69 #define C0_ERROREPC 30, 0 70 71 #define CALLFRAME_SIZ 32 72 73 #ifdef CONFIG_64BIT 74 #define ST0_KX_IF_64 ST0_KX 75 #else 76 #define ST0_KX_IF_64 0 77 #endif 78 79 static unsigned int scratch_vcpu[2] = { C0_DDATA_LO }; 80 static unsigned int scratch_tmp[2] = { C0_ERROREPC }; 81 82 enum label_id { 83 label_fpu_1 = 1, 84 label_msa_1, 85 label_return_to_host, 86 label_kernel_asid, 87 label_exit_common, 88 }; 89 90 UASM_L_LA(_fpu_1) 91 UASM_L_LA(_msa_1) 92 UASM_L_LA(_return_to_host) 93 UASM_L_LA(_kernel_asid) 94 UASM_L_LA(_exit_common) 95 96 static void *kvm_mips_build_enter_guest(void *addr); 97 static void *kvm_mips_build_ret_from_exit(void *addr); 98 static void *kvm_mips_build_ret_to_guest(void *addr); 99 static void *kvm_mips_build_ret_to_host(void *addr); 100 101 /* 102 * The version of this function in tlbex.c uses current_cpu_type(), but for KVM 103 * we assume symmetry. 104 */ 105 static int c0_kscratch(void) 106 { 107 switch (boot_cpu_type()) { 108 case CPU_XLP: 109 case CPU_XLR: 110 return 22; 111 default: 112 return 31; 113 } 114 } 115 116 /** 117 * kvm_mips_entry_setup() - Perform global setup for entry code. 118 * 119 * Perform global setup for entry code, such as choosing a scratch register. 120 * 121 * Returns: 0 on success. 122 * -errno on failure. 123 */ 124 int kvm_mips_entry_setup(void) 125 { 126 /* 127 * We prefer to use KScratchN registers if they are available over the 128 * defaults above, which may not work on all cores. 129 */ 130 unsigned int kscratch_mask = cpu_data[0].kscratch_mask; 131 132 if (pgd_reg != -1) 133 kscratch_mask &= ~BIT(pgd_reg); 134 135 /* Pick a scratch register for storing VCPU */ 136 if (kscratch_mask) { 137 scratch_vcpu[0] = c0_kscratch(); 138 scratch_vcpu[1] = ffs(kscratch_mask) - 1; 139 kscratch_mask &= ~BIT(scratch_vcpu[1]); 140 } 141 142 /* Pick a scratch register to use as a temp for saving state */ 143 if (kscratch_mask) { 144 scratch_tmp[0] = c0_kscratch(); 145 scratch_tmp[1] = ffs(kscratch_mask) - 1; 146 kscratch_mask &= ~BIT(scratch_tmp[1]); 147 } 148 149 return 0; 150 } 151 152 static void kvm_mips_build_save_scratch(u32 **p, unsigned int tmp, 153 unsigned int frame) 154 { 155 /* Save the VCPU scratch register value in cp0_epc of the stack frame */ 156 UASM_i_MFC0(p, tmp, scratch_vcpu[0], scratch_vcpu[1]); 157 UASM_i_SW(p, tmp, offsetof(struct pt_regs, cp0_epc), frame); 158 159 /* Save the temp scratch register value in cp0_cause of stack frame */ 160 if (scratch_tmp[0] == c0_kscratch()) { 161 UASM_i_MFC0(p, tmp, scratch_tmp[0], scratch_tmp[1]); 162 UASM_i_SW(p, tmp, offsetof(struct pt_regs, cp0_cause), frame); 163 } 164 } 165 166 static void kvm_mips_build_restore_scratch(u32 **p, unsigned int tmp, 167 unsigned int frame) 168 { 169 /* 170 * Restore host scratch register values saved by 171 * kvm_mips_build_save_scratch(). 172 */ 173 UASM_i_LW(p, tmp, offsetof(struct pt_regs, cp0_epc), frame); 174 UASM_i_MTC0(p, tmp, scratch_vcpu[0], scratch_vcpu[1]); 175 176 if (scratch_tmp[0] == c0_kscratch()) { 177 UASM_i_LW(p, tmp, offsetof(struct pt_regs, cp0_cause), frame); 178 UASM_i_MTC0(p, tmp, scratch_tmp[0], scratch_tmp[1]); 179 } 180 } 181 182 /** 183 * build_set_exc_base() - Assemble code to write exception base address. 184 * @p: Code buffer pointer. 185 * @reg: Source register (generated code may set WG bit in @reg). 186 * 187 * Assemble code to modify the exception base address in the EBase register, 188 * using the appropriately sized access and setting the WG bit if necessary. 189 */ 190 static inline void build_set_exc_base(u32 **p, unsigned int reg) 191 { 192 if (cpu_has_ebase_wg) { 193 /* Set WG so that all the bits get written */ 194 uasm_i_ori(p, reg, reg, MIPS_EBASE_WG); 195 UASM_i_MTC0(p, reg, C0_EBASE); 196 } else { 197 uasm_i_mtc0(p, reg, C0_EBASE); 198 } 199 } 200 201 /** 202 * kvm_mips_build_vcpu_run() - Assemble function to start running a guest VCPU. 203 * @addr: Address to start writing code. 204 * 205 * Assemble the start of the vcpu_run function to run a guest VCPU. The function 206 * conforms to the following prototype: 207 * 208 * int vcpu_run(struct kvm_run *run, struct kvm_vcpu *vcpu); 209 * 210 * The exit from the guest and return to the caller is handled by the code 211 * generated by kvm_mips_build_ret_to_host(). 212 * 213 * Returns: Next address after end of written function. 214 */ 215 void *kvm_mips_build_vcpu_run(void *addr) 216 { 217 u32 *p = addr; 218 unsigned int i; 219 220 /* 221 * A0: run 222 * A1: vcpu 223 */ 224 225 /* k0/k1 not being used in host kernel context */ 226 UASM_i_ADDIU(&p, K1, SP, -(int)sizeof(struct pt_regs)); 227 for (i = 16; i < 32; ++i) { 228 if (i == 24) 229 i = 28; 230 UASM_i_SW(&p, i, offsetof(struct pt_regs, regs[i]), K1); 231 } 232 233 /* Save host status */ 234 uasm_i_mfc0(&p, V0, C0_STATUS); 235 UASM_i_SW(&p, V0, offsetof(struct pt_regs, cp0_status), K1); 236 237 /* Save scratch registers, will be used to store pointer to vcpu etc */ 238 kvm_mips_build_save_scratch(&p, V1, K1); 239 240 /* VCPU scratch register has pointer to vcpu */ 241 UASM_i_MTC0(&p, A1, scratch_vcpu[0], scratch_vcpu[1]); 242 243 /* Offset into vcpu->arch */ 244 UASM_i_ADDIU(&p, K1, A1, offsetof(struct kvm_vcpu, arch)); 245 246 /* 247 * Save the host stack to VCPU, used for exception processing 248 * when we exit from the Guest 249 */ 250 UASM_i_SW(&p, SP, offsetof(struct kvm_vcpu_arch, host_stack), K1); 251 252 /* Save the kernel gp as well */ 253 UASM_i_SW(&p, GP, offsetof(struct kvm_vcpu_arch, host_gp), K1); 254 255 /* 256 * Setup status register for running the guest in UM, interrupts 257 * are disabled 258 */ 259 UASM_i_LA(&p, K0, ST0_EXL | KSU_USER | ST0_BEV | ST0_KX_IF_64); 260 uasm_i_mtc0(&p, K0, C0_STATUS); 261 uasm_i_ehb(&p); 262 263 /* load up the new EBASE */ 264 UASM_i_LW(&p, K0, offsetof(struct kvm_vcpu_arch, guest_ebase), K1); 265 build_set_exc_base(&p, K0); 266 267 /* 268 * Now that the new EBASE has been loaded, unset BEV, set 269 * interrupt mask as it was but make sure that timer interrupts 270 * are enabled 271 */ 272 uasm_i_addiu(&p, K0, ZERO, ST0_EXL | KSU_USER | ST0_IE | ST0_KX_IF_64); 273 uasm_i_andi(&p, V0, V0, ST0_IM); 274 uasm_i_or(&p, K0, K0, V0); 275 uasm_i_mtc0(&p, K0, C0_STATUS); 276 uasm_i_ehb(&p); 277 278 p = kvm_mips_build_enter_guest(p); 279 280 return p; 281 } 282 283 /** 284 * kvm_mips_build_enter_guest() - Assemble code to resume guest execution. 285 * @addr: Address to start writing code. 286 * 287 * Assemble the code to resume guest execution. This code is common between the 288 * initial entry into the guest from the host, and returning from the exit 289 * handler back to the guest. 290 * 291 * Returns: Next address after end of written function. 292 */ 293 static void *kvm_mips_build_enter_guest(void *addr) 294 { 295 u32 *p = addr; 296 unsigned int i; 297 struct uasm_label labels[2]; 298 struct uasm_reloc relocs[2]; 299 struct uasm_label __maybe_unused *l = labels; 300 struct uasm_reloc __maybe_unused *r = relocs; 301 302 memset(labels, 0, sizeof(labels)); 303 memset(relocs, 0, sizeof(relocs)); 304 305 /* Set Guest EPC */ 306 UASM_i_LW(&p, T0, offsetof(struct kvm_vcpu_arch, pc), K1); 307 UASM_i_MTC0(&p, T0, C0_EPC); 308 309 #ifdef CONFIG_KVM_MIPS_VZ 310 /* Save normal linux process pgd (VZ guarantees pgd_reg is set) */ 311 if (cpu_has_ldpte) 312 UASM_i_MFC0(&p, K0, C0_PWBASE); 313 else 314 UASM_i_MFC0(&p, K0, c0_kscratch(), pgd_reg); 315 UASM_i_SW(&p, K0, offsetof(struct kvm_vcpu_arch, host_pgd), K1); 316 317 /* 318 * Set up KVM GPA pgd. 319 * This does roughly the same as TLBMISS_HANDLER_SETUP_PGD(): 320 * - call tlbmiss_handler_setup_pgd(mm->pgd) 321 * - write mm->pgd into CP0_PWBase 322 * 323 * We keep S0 pointing at struct kvm so we can load the ASID below. 324 */ 325 UASM_i_LW(&p, S0, (int)offsetof(struct kvm_vcpu, kvm) - 326 (int)offsetof(struct kvm_vcpu, arch), K1); 327 UASM_i_LW(&p, A0, offsetof(struct kvm, arch.gpa_mm.pgd), S0); 328 UASM_i_LA(&p, T9, (unsigned long)tlbmiss_handler_setup_pgd); 329 uasm_i_jalr(&p, RA, T9); 330 /* delay slot */ 331 if (cpu_has_htw) 332 UASM_i_MTC0(&p, A0, C0_PWBASE); 333 else 334 uasm_i_nop(&p); 335 336 /* Set GM bit to setup eret to VZ guest context */ 337 uasm_i_addiu(&p, V1, ZERO, 1); 338 uasm_i_mfc0(&p, K0, C0_GUESTCTL0); 339 uasm_i_ins(&p, K0, V1, MIPS_GCTL0_GM_SHIFT, 1); 340 uasm_i_mtc0(&p, K0, C0_GUESTCTL0); 341 342 if (cpu_has_guestid) { 343 /* 344 * Set root mode GuestID, so that root TLB refill handler can 345 * use the correct GuestID in the root TLB. 346 */ 347 348 /* Get current GuestID */ 349 uasm_i_mfc0(&p, T0, C0_GUESTCTL1); 350 /* Set GuestCtl1.RID = GuestCtl1.ID */ 351 uasm_i_ext(&p, T1, T0, MIPS_GCTL1_ID_SHIFT, 352 MIPS_GCTL1_ID_WIDTH); 353 uasm_i_ins(&p, T0, T1, MIPS_GCTL1_RID_SHIFT, 354 MIPS_GCTL1_RID_WIDTH); 355 uasm_i_mtc0(&p, T0, C0_GUESTCTL1); 356 357 /* GuestID handles dealiasing so we don't need to touch ASID */ 358 goto skip_asid_restore; 359 } 360 361 /* Root ASID Dealias (RAD) */ 362 363 /* Save host ASID */ 364 UASM_i_MFC0(&p, K0, C0_ENTRYHI); 365 UASM_i_SW(&p, K0, offsetof(struct kvm_vcpu_arch, host_entryhi), 366 K1); 367 368 /* Set the root ASID for the Guest */ 369 UASM_i_ADDIU(&p, T1, S0, 370 offsetof(struct kvm, arch.gpa_mm.context.asid)); 371 #else 372 /* Set the ASID for the Guest Kernel or User */ 373 UASM_i_LW(&p, T0, offsetof(struct kvm_vcpu_arch, cop0), K1); 374 UASM_i_LW(&p, T0, offsetof(struct mips_coproc, reg[MIPS_CP0_STATUS][0]), 375 T0); 376 uasm_i_andi(&p, T0, T0, KSU_USER | ST0_ERL | ST0_EXL); 377 uasm_i_xori(&p, T0, T0, KSU_USER); 378 uasm_il_bnez(&p, &r, T0, label_kernel_asid); 379 UASM_i_ADDIU(&p, T1, K1, offsetof(struct kvm_vcpu_arch, 380 guest_kernel_mm.context.asid)); 381 /* else user */ 382 UASM_i_ADDIU(&p, T1, K1, offsetof(struct kvm_vcpu_arch, 383 guest_user_mm.context.asid)); 384 uasm_l_kernel_asid(&l, p); 385 #endif 386 387 /* t1: contains the base of the ASID array, need to get the cpu id */ 388 /* smp_processor_id */ 389 uasm_i_lw(&p, T2, offsetof(struct thread_info, cpu), GP); 390 /* index the ASID array */ 391 uasm_i_sll(&p, T2, T2, ilog2(sizeof(long))); 392 UASM_i_ADDU(&p, T3, T1, T2); 393 UASM_i_LW(&p, K0, 0, T3); 394 #ifdef CONFIG_MIPS_ASID_BITS_VARIABLE 395 /* 396 * reuse ASID array offset 397 * cpuinfo_mips is a multiple of sizeof(long) 398 */ 399 uasm_i_addiu(&p, T3, ZERO, sizeof(struct cpuinfo_mips)/sizeof(long)); 400 uasm_i_mul(&p, T2, T2, T3); 401 402 UASM_i_LA_mostly(&p, AT, (long)&cpu_data[0].asid_mask); 403 UASM_i_ADDU(&p, AT, AT, T2); 404 UASM_i_LW(&p, T2, uasm_rel_lo((long)&cpu_data[0].asid_mask), AT); 405 uasm_i_and(&p, K0, K0, T2); 406 #else 407 uasm_i_andi(&p, K0, K0, MIPS_ENTRYHI_ASID); 408 #endif 409 410 #ifndef CONFIG_KVM_MIPS_VZ 411 /* 412 * Set up KVM T&E GVA pgd. 413 * This does roughly the same as TLBMISS_HANDLER_SETUP_PGD(): 414 * - call tlbmiss_handler_setup_pgd(mm->pgd) 415 * - but skips write into CP0_PWBase for now 416 */ 417 UASM_i_LW(&p, A0, (int)offsetof(struct mm_struct, pgd) - 418 (int)offsetof(struct mm_struct, context.asid), T1); 419 420 UASM_i_LA(&p, T9, (unsigned long)tlbmiss_handler_setup_pgd); 421 uasm_i_jalr(&p, RA, T9); 422 uasm_i_mtc0(&p, K0, C0_ENTRYHI); 423 #else 424 /* Set up KVM VZ root ASID (!guestid) */ 425 uasm_i_mtc0(&p, K0, C0_ENTRYHI); 426 skip_asid_restore: 427 #endif 428 uasm_i_ehb(&p); 429 430 /* Disable RDHWR access */ 431 uasm_i_mtc0(&p, ZERO, C0_HWRENA); 432 433 /* load the guest context from VCPU and return */ 434 for (i = 1; i < 32; ++i) { 435 /* Guest k0/k1 loaded later */ 436 if (i == K0 || i == K1) 437 continue; 438 UASM_i_LW(&p, i, offsetof(struct kvm_vcpu_arch, gprs[i]), K1); 439 } 440 441 #ifndef CONFIG_CPU_MIPSR6 442 /* Restore hi/lo */ 443 UASM_i_LW(&p, K0, offsetof(struct kvm_vcpu_arch, hi), K1); 444 uasm_i_mthi(&p, K0); 445 446 UASM_i_LW(&p, K0, offsetof(struct kvm_vcpu_arch, lo), K1); 447 uasm_i_mtlo(&p, K0); 448 #endif 449 450 /* Restore the guest's k0/k1 registers */ 451 UASM_i_LW(&p, K0, offsetof(struct kvm_vcpu_arch, gprs[K0]), K1); 452 UASM_i_LW(&p, K1, offsetof(struct kvm_vcpu_arch, gprs[K1]), K1); 453 454 /* Jump to guest */ 455 uasm_i_eret(&p); 456 457 uasm_resolve_relocs(relocs, labels); 458 459 return p; 460 } 461 462 /** 463 * kvm_mips_build_tlb_refill_exception() - Assemble TLB refill handler. 464 * @addr: Address to start writing code. 465 * @handler: Address of common handler (within range of @addr). 466 * 467 * Assemble TLB refill exception fast path handler for guest execution. 468 * 469 * Returns: Next address after end of written function. 470 */ 471 void *kvm_mips_build_tlb_refill_exception(void *addr, void *handler) 472 { 473 u32 *p = addr; 474 struct uasm_label labels[2]; 475 struct uasm_reloc relocs[2]; 476 #ifndef CONFIG_CPU_LOONGSON64 477 struct uasm_label *l = labels; 478 struct uasm_reloc *r = relocs; 479 #endif 480 481 memset(labels, 0, sizeof(labels)); 482 memset(relocs, 0, sizeof(relocs)); 483 484 /* Save guest k1 into scratch register */ 485 UASM_i_MTC0(&p, K1, scratch_tmp[0], scratch_tmp[1]); 486 487 /* Get the VCPU pointer from the VCPU scratch register */ 488 UASM_i_MFC0(&p, K1, scratch_vcpu[0], scratch_vcpu[1]); 489 490 /* Save guest k0 into VCPU structure */ 491 UASM_i_SW(&p, K0, offsetof(struct kvm_vcpu, arch.gprs[K0]), K1); 492 493 /* 494 * Some of the common tlbex code uses current_cpu_type(). For KVM we 495 * assume symmetry and just disable preemption to silence the warning. 496 */ 497 preempt_disable(); 498 499 #ifdef CONFIG_CPU_LOONGSON64 500 UASM_i_MFC0(&p, K1, C0_PGD); 501 uasm_i_lddir(&p, K0, K1, 3); /* global page dir */ 502 #ifndef __PAGETABLE_PMD_FOLDED 503 uasm_i_lddir(&p, K1, K0, 1); /* middle page dir */ 504 #endif 505 uasm_i_ldpte(&p, K1, 0); /* even */ 506 uasm_i_ldpte(&p, K1, 1); /* odd */ 507 uasm_i_tlbwr(&p); 508 #else 509 /* 510 * Now for the actual refill bit. A lot of this can be common with the 511 * Linux TLB refill handler, however we don't need to handle so many 512 * cases. We only need to handle user mode refills, and user mode runs 513 * with 32-bit addressing. 514 * 515 * Therefore the branch to label_vmalloc generated by build_get_pmde64() 516 * that isn't resolved should never actually get taken and is harmless 517 * to leave in place for now. 518 */ 519 520 #ifdef CONFIG_64BIT 521 build_get_pmde64(&p, &l, &r, K0, K1); /* get pmd in K1 */ 522 #else 523 build_get_pgde32(&p, K0, K1); /* get pgd in K1 */ 524 #endif 525 526 /* we don't support huge pages yet */ 527 528 build_get_ptep(&p, K0, K1); 529 build_update_entries(&p, K0, K1); 530 build_tlb_write_entry(&p, &l, &r, tlb_random); 531 #endif 532 533 preempt_enable(); 534 535 /* Get the VCPU pointer from the VCPU scratch register again */ 536 UASM_i_MFC0(&p, K1, scratch_vcpu[0], scratch_vcpu[1]); 537 538 /* Restore the guest's k0/k1 registers */ 539 UASM_i_LW(&p, K0, offsetof(struct kvm_vcpu, arch.gprs[K0]), K1); 540 uasm_i_ehb(&p); 541 UASM_i_MFC0(&p, K1, scratch_tmp[0], scratch_tmp[1]); 542 543 /* Jump to guest */ 544 uasm_i_eret(&p); 545 546 return p; 547 } 548 549 /** 550 * kvm_mips_build_exception() - Assemble first level guest exception handler. 551 * @addr: Address to start writing code. 552 * @handler: Address of common handler (within range of @addr). 553 * 554 * Assemble exception vector code for guest execution. The generated vector will 555 * branch to the common exception handler generated by kvm_mips_build_exit(). 556 * 557 * Returns: Next address after end of written function. 558 */ 559 void *kvm_mips_build_exception(void *addr, void *handler) 560 { 561 u32 *p = addr; 562 struct uasm_label labels[2]; 563 struct uasm_reloc relocs[2]; 564 struct uasm_label *l = labels; 565 struct uasm_reloc *r = relocs; 566 567 memset(labels, 0, sizeof(labels)); 568 memset(relocs, 0, sizeof(relocs)); 569 570 /* Save guest k1 into scratch register */ 571 UASM_i_MTC0(&p, K1, scratch_tmp[0], scratch_tmp[1]); 572 573 /* Get the VCPU pointer from the VCPU scratch register */ 574 UASM_i_MFC0(&p, K1, scratch_vcpu[0], scratch_vcpu[1]); 575 UASM_i_ADDIU(&p, K1, K1, offsetof(struct kvm_vcpu, arch)); 576 577 /* Save guest k0 into VCPU structure */ 578 UASM_i_SW(&p, K0, offsetof(struct kvm_vcpu_arch, gprs[K0]), K1); 579 580 /* Branch to the common handler */ 581 uasm_il_b(&p, &r, label_exit_common); 582 uasm_i_nop(&p); 583 584 uasm_l_exit_common(&l, handler); 585 uasm_resolve_relocs(relocs, labels); 586 587 return p; 588 } 589 590 /** 591 * kvm_mips_build_exit() - Assemble common guest exit handler. 592 * @addr: Address to start writing code. 593 * 594 * Assemble the generic guest exit handling code. This is called by the 595 * exception vectors (generated by kvm_mips_build_exception()), and calls 596 * kvm_mips_handle_exit(), then either resumes the guest or returns to the host 597 * depending on the return value. 598 * 599 * Returns: Next address after end of written function. 600 */ 601 void *kvm_mips_build_exit(void *addr) 602 { 603 u32 *p = addr; 604 unsigned int i; 605 struct uasm_label labels[3]; 606 struct uasm_reloc relocs[3]; 607 struct uasm_label *l = labels; 608 struct uasm_reloc *r = relocs; 609 610 memset(labels, 0, sizeof(labels)); 611 memset(relocs, 0, sizeof(relocs)); 612 613 /* 614 * Generic Guest exception handler. We end up here when the guest 615 * does something that causes a trap to kernel mode. 616 * 617 * Both k0/k1 registers will have already been saved (k0 into the vcpu 618 * structure, and k1 into the scratch_tmp register). 619 * 620 * The k1 register will already contain the kvm_vcpu_arch pointer. 621 */ 622 623 /* Start saving Guest context to VCPU */ 624 for (i = 0; i < 32; ++i) { 625 /* Guest k0/k1 saved later */ 626 if (i == K0 || i == K1) 627 continue; 628 UASM_i_SW(&p, i, offsetof(struct kvm_vcpu_arch, gprs[i]), K1); 629 } 630 631 #ifndef CONFIG_CPU_MIPSR6 632 /* We need to save hi/lo and restore them on the way out */ 633 uasm_i_mfhi(&p, T0); 634 UASM_i_SW(&p, T0, offsetof(struct kvm_vcpu_arch, hi), K1); 635 636 uasm_i_mflo(&p, T0); 637 UASM_i_SW(&p, T0, offsetof(struct kvm_vcpu_arch, lo), K1); 638 #endif 639 640 /* Finally save guest k1 to VCPU */ 641 uasm_i_ehb(&p); 642 UASM_i_MFC0(&p, T0, scratch_tmp[0], scratch_tmp[1]); 643 UASM_i_SW(&p, T0, offsetof(struct kvm_vcpu_arch, gprs[K1]), K1); 644 645 /* Now that context has been saved, we can use other registers */ 646 647 /* Restore vcpu */ 648 UASM_i_MFC0(&p, S1, scratch_vcpu[0], scratch_vcpu[1]); 649 650 /* Restore run (vcpu->run) */ 651 UASM_i_LW(&p, S0, offsetof(struct kvm_vcpu, run), S1); 652 653 /* 654 * Save Host level EPC, BadVaddr and Cause to VCPU, useful to process 655 * the exception 656 */ 657 UASM_i_MFC0(&p, K0, C0_EPC); 658 UASM_i_SW(&p, K0, offsetof(struct kvm_vcpu_arch, pc), K1); 659 660 UASM_i_MFC0(&p, K0, C0_BADVADDR); 661 UASM_i_SW(&p, K0, offsetof(struct kvm_vcpu_arch, host_cp0_badvaddr), 662 K1); 663 664 uasm_i_mfc0(&p, K0, C0_CAUSE); 665 uasm_i_sw(&p, K0, offsetof(struct kvm_vcpu_arch, host_cp0_cause), K1); 666 667 if (cpu_has_badinstr) { 668 uasm_i_mfc0(&p, K0, C0_BADINSTR); 669 uasm_i_sw(&p, K0, offsetof(struct kvm_vcpu_arch, 670 host_cp0_badinstr), K1); 671 } 672 673 if (cpu_has_badinstrp) { 674 uasm_i_mfc0(&p, K0, C0_BADINSTRP); 675 uasm_i_sw(&p, K0, offsetof(struct kvm_vcpu_arch, 676 host_cp0_badinstrp), K1); 677 } 678 679 /* Now restore the host state just enough to run the handlers */ 680 681 /* Switch EBASE to the one used by Linux */ 682 /* load up the host EBASE */ 683 uasm_i_mfc0(&p, V0, C0_STATUS); 684 685 uasm_i_lui(&p, AT, ST0_BEV >> 16); 686 uasm_i_or(&p, K0, V0, AT); 687 688 uasm_i_mtc0(&p, K0, C0_STATUS); 689 uasm_i_ehb(&p); 690 691 UASM_i_LA_mostly(&p, K0, (long)&ebase); 692 UASM_i_LW(&p, K0, uasm_rel_lo((long)&ebase), K0); 693 build_set_exc_base(&p, K0); 694 695 if (raw_cpu_has_fpu) { 696 /* 697 * If FPU is enabled, save FCR31 and clear it so that later 698 * ctc1's don't trigger FPE for pending exceptions. 699 */ 700 uasm_i_lui(&p, AT, ST0_CU1 >> 16); 701 uasm_i_and(&p, V1, V0, AT); 702 uasm_il_beqz(&p, &r, V1, label_fpu_1); 703 uasm_i_nop(&p); 704 uasm_i_cfc1(&p, T0, 31); 705 uasm_i_sw(&p, T0, offsetof(struct kvm_vcpu_arch, fpu.fcr31), 706 K1); 707 uasm_i_ctc1(&p, ZERO, 31); 708 uasm_l_fpu_1(&l, p); 709 } 710 711 if (cpu_has_msa) { 712 /* 713 * If MSA is enabled, save MSACSR and clear it so that later 714 * instructions don't trigger MSAFPE for pending exceptions. 715 */ 716 uasm_i_mfc0(&p, T0, C0_CONFIG5); 717 uasm_i_ext(&p, T0, T0, 27, 1); /* MIPS_CONF5_MSAEN */ 718 uasm_il_beqz(&p, &r, T0, label_msa_1); 719 uasm_i_nop(&p); 720 uasm_i_cfcmsa(&p, T0, MSA_CSR); 721 uasm_i_sw(&p, T0, offsetof(struct kvm_vcpu_arch, fpu.msacsr), 722 K1); 723 uasm_i_ctcmsa(&p, MSA_CSR, ZERO); 724 uasm_l_msa_1(&l, p); 725 } 726 727 #ifdef CONFIG_KVM_MIPS_VZ 728 /* Restore host ASID */ 729 if (!cpu_has_guestid) { 730 UASM_i_LW(&p, K0, offsetof(struct kvm_vcpu_arch, host_entryhi), 731 K1); 732 UASM_i_MTC0(&p, K0, C0_ENTRYHI); 733 } 734 735 /* 736 * Set up normal Linux process pgd. 737 * This does roughly the same as TLBMISS_HANDLER_SETUP_PGD(): 738 * - call tlbmiss_handler_setup_pgd(mm->pgd) 739 * - write mm->pgd into CP0_PWBase 740 */ 741 UASM_i_LW(&p, A0, 742 offsetof(struct kvm_vcpu_arch, host_pgd), K1); 743 UASM_i_LA(&p, T9, (unsigned long)tlbmiss_handler_setup_pgd); 744 uasm_i_jalr(&p, RA, T9); 745 /* delay slot */ 746 if (cpu_has_htw) 747 UASM_i_MTC0(&p, A0, C0_PWBASE); 748 else 749 uasm_i_nop(&p); 750 751 /* Clear GM bit so we don't enter guest mode when EXL is cleared */ 752 uasm_i_mfc0(&p, K0, C0_GUESTCTL0); 753 uasm_i_ins(&p, K0, ZERO, MIPS_GCTL0_GM_SHIFT, 1); 754 uasm_i_mtc0(&p, K0, C0_GUESTCTL0); 755 756 /* Save GuestCtl0 so we can access GExcCode after CPU migration */ 757 uasm_i_sw(&p, K0, 758 offsetof(struct kvm_vcpu_arch, host_cp0_guestctl0), K1); 759 760 if (cpu_has_guestid) { 761 /* 762 * Clear root mode GuestID, so that root TLB operations use the 763 * root GuestID in the root TLB. 764 */ 765 uasm_i_mfc0(&p, T0, C0_GUESTCTL1); 766 /* Set GuestCtl1.RID = MIPS_GCTL1_ROOT_GUESTID (i.e. 0) */ 767 uasm_i_ins(&p, T0, ZERO, MIPS_GCTL1_RID_SHIFT, 768 MIPS_GCTL1_RID_WIDTH); 769 uasm_i_mtc0(&p, T0, C0_GUESTCTL1); 770 } 771 #endif 772 773 /* Now that the new EBASE has been loaded, unset BEV and KSU_USER */ 774 uasm_i_addiu(&p, AT, ZERO, ~(ST0_EXL | KSU_USER | ST0_IE)); 775 uasm_i_and(&p, V0, V0, AT); 776 uasm_i_lui(&p, AT, ST0_CU0 >> 16); 777 uasm_i_or(&p, V0, V0, AT); 778 #ifdef CONFIG_64BIT 779 uasm_i_ori(&p, V0, V0, ST0_SX | ST0_UX); 780 #endif 781 uasm_i_mtc0(&p, V0, C0_STATUS); 782 uasm_i_ehb(&p); 783 784 /* Load up host GP */ 785 UASM_i_LW(&p, GP, offsetof(struct kvm_vcpu_arch, host_gp), K1); 786 787 /* Need a stack before we can jump to "C" */ 788 UASM_i_LW(&p, SP, offsetof(struct kvm_vcpu_arch, host_stack), K1); 789 790 /* Saved host state */ 791 UASM_i_ADDIU(&p, SP, SP, -(int)sizeof(struct pt_regs)); 792 793 /* 794 * XXXKYMA do we need to load the host ASID, maybe not because the 795 * kernel entries are marked GLOBAL, need to verify 796 */ 797 798 /* Restore host scratch registers, as we'll have clobbered them */ 799 kvm_mips_build_restore_scratch(&p, K0, SP); 800 801 /* Restore RDHWR access */ 802 UASM_i_LA_mostly(&p, K0, (long)&hwrena); 803 uasm_i_lw(&p, K0, uasm_rel_lo((long)&hwrena), K0); 804 uasm_i_mtc0(&p, K0, C0_HWRENA); 805 806 /* Jump to handler */ 807 /* 808 * XXXKYMA: not sure if this is safe, how large is the stack?? 809 * Now jump to the kvm_mips_handle_exit() to see if we can deal 810 * with this in the kernel 811 */ 812 uasm_i_move(&p, A0, S0); 813 uasm_i_move(&p, A1, S1); 814 UASM_i_LA(&p, T9, (unsigned long)kvm_mips_handle_exit); 815 uasm_i_jalr(&p, RA, T9); 816 UASM_i_ADDIU(&p, SP, SP, -CALLFRAME_SIZ); 817 818 uasm_resolve_relocs(relocs, labels); 819 820 p = kvm_mips_build_ret_from_exit(p); 821 822 return p; 823 } 824 825 /** 826 * kvm_mips_build_ret_from_exit() - Assemble guest exit return handler. 827 * @addr: Address to start writing code. 828 * 829 * Assemble the code to handle the return from kvm_mips_handle_exit(), either 830 * resuming the guest or returning to the host depending on the return value. 831 * 832 * Returns: Next address after end of written function. 833 */ 834 static void *kvm_mips_build_ret_from_exit(void *addr) 835 { 836 u32 *p = addr; 837 struct uasm_label labels[2]; 838 struct uasm_reloc relocs[2]; 839 struct uasm_label *l = labels; 840 struct uasm_reloc *r = relocs; 841 842 memset(labels, 0, sizeof(labels)); 843 memset(relocs, 0, sizeof(relocs)); 844 845 /* Return from handler Make sure interrupts are disabled */ 846 uasm_i_di(&p, ZERO); 847 uasm_i_ehb(&p); 848 849 /* 850 * XXXKYMA: k0/k1 could have been blown away if we processed 851 * an exception while we were handling the exception from the 852 * guest, reload k1 853 */ 854 855 uasm_i_move(&p, K1, S1); 856 UASM_i_ADDIU(&p, K1, K1, offsetof(struct kvm_vcpu, arch)); 857 858 /* 859 * Check return value, should tell us if we are returning to the 860 * host (handle I/O etc)or resuming the guest 861 */ 862 uasm_i_andi(&p, T0, V0, RESUME_HOST); 863 uasm_il_bnez(&p, &r, T0, label_return_to_host); 864 uasm_i_nop(&p); 865 866 p = kvm_mips_build_ret_to_guest(p); 867 868 uasm_l_return_to_host(&l, p); 869 p = kvm_mips_build_ret_to_host(p); 870 871 uasm_resolve_relocs(relocs, labels); 872 873 return p; 874 } 875 876 /** 877 * kvm_mips_build_ret_to_guest() - Assemble code to return to the guest. 878 * @addr: Address to start writing code. 879 * 880 * Assemble the code to handle return from the guest exit handler 881 * (kvm_mips_handle_exit()) back to the guest. 882 * 883 * Returns: Next address after end of written function. 884 */ 885 static void *kvm_mips_build_ret_to_guest(void *addr) 886 { 887 u32 *p = addr; 888 889 /* Put the saved pointer to vcpu (s1) back into the scratch register */ 890 UASM_i_MTC0(&p, S1, scratch_vcpu[0], scratch_vcpu[1]); 891 892 /* Load up the Guest EBASE to minimize the window where BEV is set */ 893 UASM_i_LW(&p, T0, offsetof(struct kvm_vcpu_arch, guest_ebase), K1); 894 895 /* Switch EBASE back to the one used by KVM */ 896 uasm_i_mfc0(&p, V1, C0_STATUS); 897 uasm_i_lui(&p, AT, ST0_BEV >> 16); 898 uasm_i_or(&p, K0, V1, AT); 899 uasm_i_mtc0(&p, K0, C0_STATUS); 900 uasm_i_ehb(&p); 901 build_set_exc_base(&p, T0); 902 903 /* Setup status register for running guest in UM */ 904 uasm_i_ori(&p, V1, V1, ST0_EXL | KSU_USER | ST0_IE); 905 UASM_i_LA(&p, AT, ~(ST0_CU0 | ST0_MX | ST0_SX | ST0_UX)); 906 uasm_i_and(&p, V1, V1, AT); 907 uasm_i_mtc0(&p, V1, C0_STATUS); 908 uasm_i_ehb(&p); 909 910 p = kvm_mips_build_enter_guest(p); 911 912 return p; 913 } 914 915 /** 916 * kvm_mips_build_ret_to_host() - Assemble code to return to the host. 917 * @addr: Address to start writing code. 918 * 919 * Assemble the code to handle return from the guest exit handler 920 * (kvm_mips_handle_exit()) back to the host, i.e. to the caller of the vcpu_run 921 * function generated by kvm_mips_build_vcpu_run(). 922 * 923 * Returns: Next address after end of written function. 924 */ 925 static void *kvm_mips_build_ret_to_host(void *addr) 926 { 927 u32 *p = addr; 928 unsigned int i; 929 930 /* EBASE is already pointing to Linux */ 931 UASM_i_LW(&p, K1, offsetof(struct kvm_vcpu_arch, host_stack), K1); 932 UASM_i_ADDIU(&p, K1, K1, -(int)sizeof(struct pt_regs)); 933 934 /* 935 * r2/v0 is the return code, shift it down by 2 (arithmetic) 936 * to recover the err code 937 */ 938 uasm_i_sra(&p, K0, V0, 2); 939 uasm_i_move(&p, V0, K0); 940 941 /* Load context saved on the host stack */ 942 for (i = 16; i < 31; ++i) { 943 if (i == 24) 944 i = 28; 945 UASM_i_LW(&p, i, offsetof(struct pt_regs, regs[i]), K1); 946 } 947 948 /* Restore RDHWR access */ 949 UASM_i_LA_mostly(&p, K0, (long)&hwrena); 950 uasm_i_lw(&p, K0, uasm_rel_lo((long)&hwrena), K0); 951 uasm_i_mtc0(&p, K0, C0_HWRENA); 952 953 /* Restore RA, which is the address we will return to */ 954 UASM_i_LW(&p, RA, offsetof(struct pt_regs, regs[RA]), K1); 955 uasm_i_jr(&p, RA); 956 uasm_i_nop(&p); 957 958 return p; 959 } 960 961