xref: /linux/arch/mips/kernel/smp.c (revision 7b12b9137930eb821b68e1bfa11e9de692208620)
1 /*
2  * This program is free software; you can redistribute it and/or
3  * modify it under the terms of the GNU General Public License
4  * as published by the Free Software Foundation; either version 2
5  * of the License, or (at your option) any later version.
6  *
7  * This program is distributed in the hope that it will be useful,
8  * but WITHOUT ANY WARRANTY; without even the implied warranty of
9  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
10  * GNU General Public License for more details.
11  *
12  * You should have received a copy of the GNU General Public License
13  * along with this program; if not, write to the Free Software
14  * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.
15  *
16  * Copyright (C) 2000, 2001 Kanoj Sarcar
17  * Copyright (C) 2000, 2001 Ralf Baechle
18  * Copyright (C) 2000, 2001 Silicon Graphics, Inc.
19  * Copyright (C) 2000, 2001, 2003 Broadcom Corporation
20  */
21 #include <linux/cache.h>
22 #include <linux/delay.h>
23 #include <linux/init.h>
24 #include <linux/interrupt.h>
25 #include <linux/spinlock.h>
26 #include <linux/threads.h>
27 #include <linux/module.h>
28 #include <linux/time.h>
29 #include <linux/timex.h>
30 #include <linux/sched.h>
31 #include <linux/cpumask.h>
32 #include <linux/cpu.h>
33 
34 #include <asm/atomic.h>
35 #include <asm/cpu.h>
36 #include <asm/processor.h>
37 #include <asm/system.h>
38 #include <asm/mmu_context.h>
39 #include <asm/smp.h>
40 
41 #ifdef CONFIG_MIPS_MT_SMTC
42 #include <asm/mipsmtregs.h>
43 #endif /* CONFIG_MIPS_MT_SMTC */
44 
45 cpumask_t phys_cpu_present_map;		/* Bitmask of available CPUs */
46 volatile cpumask_t cpu_callin_map;	/* Bitmask of started secondaries */
47 cpumask_t cpu_online_map;		/* Bitmask of currently online CPUs */
48 int __cpu_number_map[NR_CPUS];		/* Map physical to logical */
49 int __cpu_logical_map[NR_CPUS];		/* Map logical to physical */
50 
51 EXPORT_SYMBOL(phys_cpu_present_map);
52 EXPORT_SYMBOL(cpu_online_map);
53 
54 static void smp_tune_scheduling (void)
55 {
56 	struct cache_desc *cd = &current_cpu_data.scache;
57 	unsigned long cachesize;       /* kB   */
58 	unsigned long cpu_khz;
59 
60 	/*
61 	 * Crude estimate until we actually meassure ...
62 	 */
63 	cpu_khz = loops_per_jiffy * 2 * HZ / 1000;
64 
65 	/*
66 	 * Rough estimation for SMP scheduling, this is the number of
67 	 * cycles it takes for a fully memory-limited process to flush
68 	 * the SMP-local cache.
69 	 *
70 	 * (For a P5 this pretty much means we will choose another idle
71 	 *  CPU almost always at wakeup time (this is due to the small
72 	 *  L1 cache), on PIIs it's around 50-100 usecs, depending on
73 	 *  the cache size)
74 	 */
75 	if (!cpu_khz)
76 		return;
77 
78 	cachesize = cd->linesz * cd->sets * cd->ways;
79 }
80 
81 extern void __init calibrate_delay(void);
82 extern ATTRIB_NORET void cpu_idle(void);
83 
84 /*
85  * First C code run on the secondary CPUs after being started up by
86  * the master.
87  */
88 asmlinkage void start_secondary(void)
89 {
90 	unsigned int cpu;
91 
92 #ifdef CONFIG_MIPS_MT_SMTC
93 	/* Only do cpu_probe for first TC of CPU */
94 	if ((read_c0_tcbind() & TCBIND_CURTC) == 0)
95 #endif /* CONFIG_MIPS_MT_SMTC */
96 	cpu_probe();
97 	cpu_report();
98 	per_cpu_trap_init();
99 	prom_init_secondary();
100 
101 	/*
102 	 * XXX parity protection should be folded in here when it's converted
103 	 * to an option instead of something based on .cputype
104 	 */
105 
106 	calibrate_delay();
107 	preempt_disable();
108 	cpu = smp_processor_id();
109 	cpu_data[cpu].udelay_val = loops_per_jiffy;
110 
111 	prom_smp_finish();
112 
113 	cpu_set(cpu, cpu_callin_map);
114 
115 	cpu_idle();
116 }
117 
118 DEFINE_SPINLOCK(smp_call_lock);
119 
120 struct call_data_struct *call_data;
121 
122 /*
123  * Run a function on all other CPUs.
124  *  <func>      The function to run. This must be fast and non-blocking.
125  *  <info>      An arbitrary pointer to pass to the function.
126  *  <retry>     If true, keep retrying until ready.
127  *  <wait>      If true, wait until function has completed on other CPUs.
128  *  [RETURNS]   0 on success, else a negative status code.
129  *
130  * Does not return until remote CPUs are nearly ready to execute <func>
131  * or are or have executed.
132  *
133  * You must not call this function with disabled interrupts or from a
134  * hardware interrupt handler or from a bottom half handler:
135  *
136  * CPU A                               CPU B
137  * Disable interrupts
138  *                                     smp_call_function()
139  *                                     Take call_lock
140  *                                     Send IPIs
141  *                                     Wait for all cpus to acknowledge IPI
142  *                                     CPU A has not responded, spin waiting
143  *                                     for cpu A to respond, holding call_lock
144  * smp_call_function()
145  * Spin waiting for call_lock
146  * Deadlock                            Deadlock
147  */
148 int smp_call_function (void (*func) (void *info), void *info, int retry,
149 								int wait)
150 {
151 	struct call_data_struct data;
152 	int i, cpus = num_online_cpus() - 1;
153 	int cpu = smp_processor_id();
154 
155 	/*
156 	 * Can die spectacularly if this CPU isn't yet marked online
157 	 */
158 	BUG_ON(!cpu_online(cpu));
159 
160 	if (!cpus)
161 		return 0;
162 
163 	/* Can deadlock when called with interrupts disabled */
164 	WARN_ON(irqs_disabled());
165 
166 	data.func = func;
167 	data.info = info;
168 	atomic_set(&data.started, 0);
169 	data.wait = wait;
170 	if (wait)
171 		atomic_set(&data.finished, 0);
172 
173 	spin_lock(&smp_call_lock);
174 	call_data = &data;
175 	mb();
176 
177 	/* Send a message to all other CPUs and wait for them to respond */
178 	for_each_online_cpu(i)
179 		if (i != cpu)
180 			core_send_ipi(i, SMP_CALL_FUNCTION);
181 
182 	/* Wait for response */
183 	/* FIXME: lock-up detection, backtrace on lock-up */
184 	while (atomic_read(&data.started) != cpus)
185 		barrier();
186 
187 	if (wait)
188 		while (atomic_read(&data.finished) != cpus)
189 			barrier();
190 	call_data = NULL;
191 	spin_unlock(&smp_call_lock);
192 
193 	return 0;
194 }
195 
196 
197 void smp_call_function_interrupt(void)
198 {
199 	void (*func) (void *info) = call_data->func;
200 	void *info = call_data->info;
201 	int wait = call_data->wait;
202 
203 	/*
204 	 * Notify initiating CPU that I've grabbed the data and am
205 	 * about to execute the function.
206 	 */
207 	mb();
208 	atomic_inc(&call_data->started);
209 
210 	/*
211 	 * At this point the info structure may be out of scope unless wait==1.
212 	 */
213 	irq_enter();
214 	(*func)(info);
215 	irq_exit();
216 
217 	if (wait) {
218 		mb();
219 		atomic_inc(&call_data->finished);
220 	}
221 }
222 
223 static void stop_this_cpu(void *dummy)
224 {
225 	/*
226 	 * Remove this CPU:
227 	 */
228 	cpu_clear(smp_processor_id(), cpu_online_map);
229 	local_irq_enable();	/* May need to service _machine_restart IPI */
230 	for (;;);		/* Wait if available. */
231 }
232 
233 void smp_send_stop(void)
234 {
235 	smp_call_function(stop_this_cpu, NULL, 1, 0);
236 }
237 
238 void __init smp_cpus_done(unsigned int max_cpus)
239 {
240 	prom_cpus_done();
241 }
242 
243 /* called from main before smp_init() */
244 void __init smp_prepare_cpus(unsigned int max_cpus)
245 {
246 	init_new_context(current, &init_mm);
247 	current_thread_info()->cpu = 0;
248 	smp_tune_scheduling();
249 	plat_prepare_cpus(max_cpus);
250 }
251 
252 /* preload SMP state for boot cpu */
253 void __devinit smp_prepare_boot_cpu(void)
254 {
255 	/*
256 	 * This assumes that bootup is always handled by the processor
257 	 * with the logic and physical number 0.
258 	 */
259 	__cpu_number_map[0] = 0;
260 	__cpu_logical_map[0] = 0;
261 	cpu_set(0, phys_cpu_present_map);
262 	cpu_set(0, cpu_online_map);
263 	cpu_set(0, cpu_callin_map);
264 }
265 
266 /*
267  * Called once for each "cpu_possible(cpu)".  Needs to spin up the cpu
268  * and keep control until "cpu_online(cpu)" is set.  Note: cpu is
269  * physical, not logical.
270  */
271 int __devinit __cpu_up(unsigned int cpu)
272 {
273 	struct task_struct *idle;
274 
275 	/*
276 	 * Processor goes to start_secondary(), sets online flag
277 	 * The following code is purely to make sure
278 	 * Linux can schedule processes on this slave.
279 	 */
280 	idle = fork_idle(cpu);
281 	if (IS_ERR(idle))
282 		panic(KERN_ERR "Fork failed for CPU %d", cpu);
283 
284 	prom_boot_secondary(cpu, idle);
285 
286 	/*
287 	 * Trust is futile.  We should really have timeouts ...
288 	 */
289 	while (!cpu_isset(cpu, cpu_callin_map))
290 		udelay(100);
291 
292 	cpu_set(cpu, cpu_online_map);
293 
294 	return 0;
295 }
296 
297 /* Not really SMP stuff ... */
298 int setup_profiling_timer(unsigned int multiplier)
299 {
300 	return 0;
301 }
302 
303 static void flush_tlb_all_ipi(void *info)
304 {
305 	local_flush_tlb_all();
306 }
307 
308 void flush_tlb_all(void)
309 {
310 	on_each_cpu(flush_tlb_all_ipi, 0, 1, 1);
311 }
312 
313 static void flush_tlb_mm_ipi(void *mm)
314 {
315 	local_flush_tlb_mm((struct mm_struct *)mm);
316 }
317 
318 /*
319  * The following tlb flush calls are invoked when old translations are
320  * being torn down, or pte attributes are changing. For single threaded
321  * address spaces, a new context is obtained on the current cpu, and tlb
322  * context on other cpus are invalidated to force a new context allocation
323  * at switch_mm time, should the mm ever be used on other cpus. For
324  * multithreaded address spaces, intercpu interrupts have to be sent.
325  * Another case where intercpu interrupts are required is when the target
326  * mm might be active on another cpu (eg debuggers doing the flushes on
327  * behalf of debugees, kswapd stealing pages from another process etc).
328  * Kanoj 07/00.
329  */
330 
331 void flush_tlb_mm(struct mm_struct *mm)
332 {
333 	preempt_disable();
334 
335 	if ((atomic_read(&mm->mm_users) != 1) || (current->mm != mm)) {
336 		smp_call_function(flush_tlb_mm_ipi, (void *)mm, 1, 1);
337 	} else {
338 		int i;
339 		for (i = 0; i < num_online_cpus(); i++)
340 			if (smp_processor_id() != i)
341 				cpu_context(i, mm) = 0;
342 	}
343 	local_flush_tlb_mm(mm);
344 
345 	preempt_enable();
346 }
347 
348 struct flush_tlb_data {
349 	struct vm_area_struct *vma;
350 	unsigned long addr1;
351 	unsigned long addr2;
352 };
353 
354 static void flush_tlb_range_ipi(void *info)
355 {
356 	struct flush_tlb_data *fd = (struct flush_tlb_data *)info;
357 
358 	local_flush_tlb_range(fd->vma, fd->addr1, fd->addr2);
359 }
360 
361 void flush_tlb_range(struct vm_area_struct *vma, unsigned long start, unsigned long end)
362 {
363 	struct mm_struct *mm = vma->vm_mm;
364 
365 	preempt_disable();
366 	if ((atomic_read(&mm->mm_users) != 1) || (current->mm != mm)) {
367 		struct flush_tlb_data fd;
368 
369 		fd.vma = vma;
370 		fd.addr1 = start;
371 		fd.addr2 = end;
372 		smp_call_function(flush_tlb_range_ipi, (void *)&fd, 1, 1);
373 	} else {
374 		int i;
375 		for (i = 0; i < num_online_cpus(); i++)
376 			if (smp_processor_id() != i)
377 				cpu_context(i, mm) = 0;
378 	}
379 	local_flush_tlb_range(vma, start, end);
380 	preempt_enable();
381 }
382 
383 static void flush_tlb_kernel_range_ipi(void *info)
384 {
385 	struct flush_tlb_data *fd = (struct flush_tlb_data *)info;
386 
387 	local_flush_tlb_kernel_range(fd->addr1, fd->addr2);
388 }
389 
390 void flush_tlb_kernel_range(unsigned long start, unsigned long end)
391 {
392 	struct flush_tlb_data fd;
393 
394 	fd.addr1 = start;
395 	fd.addr2 = end;
396 	on_each_cpu(flush_tlb_kernel_range_ipi, (void *)&fd, 1, 1);
397 }
398 
399 static void flush_tlb_page_ipi(void *info)
400 {
401 	struct flush_tlb_data *fd = (struct flush_tlb_data *)info;
402 
403 	local_flush_tlb_page(fd->vma, fd->addr1);
404 }
405 
406 void flush_tlb_page(struct vm_area_struct *vma, unsigned long page)
407 {
408 	preempt_disable();
409 	if ((atomic_read(&vma->vm_mm->mm_users) != 1) || (current->mm != vma->vm_mm)) {
410 		struct flush_tlb_data fd;
411 
412 		fd.vma = vma;
413 		fd.addr1 = page;
414 		smp_call_function(flush_tlb_page_ipi, (void *)&fd, 1, 1);
415 	} else {
416 		int i;
417 		for (i = 0; i < num_online_cpus(); i++)
418 			if (smp_processor_id() != i)
419 				cpu_context(i, vma->vm_mm) = 0;
420 	}
421 	local_flush_tlb_page(vma, page);
422 	preempt_enable();
423 }
424 
425 static void flush_tlb_one_ipi(void *info)
426 {
427 	unsigned long vaddr = (unsigned long) info;
428 
429 	local_flush_tlb_one(vaddr);
430 }
431 
432 void flush_tlb_one(unsigned long vaddr)
433 {
434 	smp_call_function(flush_tlb_one_ipi, (void *) vaddr, 1, 1);
435 	local_flush_tlb_one(vaddr);
436 }
437 
438 static DEFINE_PER_CPU(struct cpu, cpu_devices);
439 
440 static int __init topology_init(void)
441 {
442 	int cpu;
443 	int ret;
444 
445 	for_each_cpu(cpu) {
446 		ret = register_cpu(&per_cpu(cpu_devices, cpu), cpu, NULL);
447 		if (ret)
448 			printk(KERN_WARNING "topology_init: register_cpu %d "
449 			       "failed (%d)\n", cpu, ret);
450 	}
451 
452 	return 0;
453 }
454 
455 subsys_initcall(topology_init);
456 
457 EXPORT_SYMBOL(flush_tlb_page);
458 EXPORT_SYMBOL(flush_tlb_one);
459