1 /* 2 * This program is free software; you can distribute it and/or modify it 3 * under the terms of the GNU General Public License (Version 2) as 4 * published by the Free Software Foundation. 5 * 6 * This program is distributed in the hope it will be useful, but WITHOUT 7 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 8 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 9 * for more details. 10 * 11 * You should have received a copy of the GNU General Public License along 12 * with this program; if not, write to the Free Software Foundation, Inc., 13 * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. 14 * 15 * Copyright (C) 2004, 05, 06 MIPS Technologies, Inc. 16 * Elizabeth Clarke (beth@mips.com) 17 * Ralf Baechle (ralf@linux-mips.org) 18 * Copyright (C) 2006 Ralf Baechle (ralf@linux-mips.org) 19 */ 20 #include <linux/kernel.h> 21 #include <linux/sched.h> 22 #include <linux/cpumask.h> 23 #include <linux/interrupt.h> 24 #include <linux/compiler.h> 25 26 #include <asm/atomic.h> 27 #include <asm/cacheflush.h> 28 #include <asm/cpu.h> 29 #include <asm/processor.h> 30 #include <asm/system.h> 31 #include <asm/hardirq.h> 32 #include <asm/mmu_context.h> 33 #include <asm/smp.h> 34 #include <asm/time.h> 35 #include <asm/mipsregs.h> 36 #include <asm/mipsmtregs.h> 37 #include <asm/mips_mt.h> 38 #include <asm/mips-boards/maltaint.h> /* This is f*cking wrong */ 39 40 #define MIPS_CPU_IPI_RESCHED_IRQ 0 41 #define MIPS_CPU_IPI_CALL_IRQ 1 42 43 static int cpu_ipi_resched_irq, cpu_ipi_call_irq; 44 45 #if 0 46 static void dump_mtregisters(int vpe, int tc) 47 { 48 printk("vpe %d tc %d\n", vpe, tc); 49 50 settc(tc); 51 52 printk(" c0 status 0x%lx\n", read_vpe_c0_status()); 53 printk(" vpecontrol 0x%lx\n", read_vpe_c0_vpecontrol()); 54 printk(" vpeconf0 0x%lx\n", read_vpe_c0_vpeconf0()); 55 printk(" tcstatus 0x%lx\n", read_tc_c0_tcstatus()); 56 printk(" tcrestart 0x%lx\n", read_tc_c0_tcrestart()); 57 printk(" tcbind 0x%lx\n", read_tc_c0_tcbind()); 58 printk(" tchalt 0x%lx\n", read_tc_c0_tchalt()); 59 } 60 #endif 61 62 void __init sanitize_tlb_entries(void) 63 { 64 int i, tlbsiz; 65 unsigned long mvpconf0, ncpu; 66 67 if (!cpu_has_mipsmt) 68 return; 69 70 /* Enable VPC */ 71 set_c0_mvpcontrol(MVPCONTROL_VPC); 72 73 back_to_back_c0_hazard(); 74 75 /* Disable TLB sharing */ 76 clear_c0_mvpcontrol(MVPCONTROL_STLB); 77 78 mvpconf0 = read_c0_mvpconf0(); 79 80 printk(KERN_INFO "MVPConf0 0x%lx TLBS %lx PTLBE %ld\n", mvpconf0, 81 (mvpconf0 & MVPCONF0_TLBS) >> MVPCONF0_TLBS_SHIFT, 82 (mvpconf0 & MVPCONF0_PTLBE) >> MVPCONF0_PTLBE_SHIFT); 83 84 tlbsiz = (mvpconf0 & MVPCONF0_PTLBE) >> MVPCONF0_PTLBE_SHIFT; 85 ncpu = ((mvpconf0 & MVPCONF0_PVPE) >> MVPCONF0_PVPE_SHIFT) + 1; 86 87 printk(" tlbsiz %d ncpu %ld\n", tlbsiz, ncpu); 88 89 if (tlbsiz > 0) { 90 /* share them out across the vpe's */ 91 tlbsiz /= ncpu; 92 93 printk(KERN_INFO "setting Config1.MMU_size to %d\n", tlbsiz); 94 95 for (i = 0; i < ncpu; i++) { 96 settc(i); 97 98 if (i == 0) 99 write_c0_config1((read_c0_config1() & ~(0x3f << 25)) | (tlbsiz << 25)); 100 else 101 write_vpe_c0_config1((read_vpe_c0_config1() & ~(0x3f << 25)) | 102 (tlbsiz << 25)); 103 } 104 } 105 106 clear_c0_mvpcontrol(MVPCONTROL_VPC); 107 } 108 109 static void ipi_resched_dispatch (struct pt_regs *regs) 110 { 111 do_IRQ(MIPSCPU_INT_BASE + MIPS_CPU_IPI_RESCHED_IRQ, regs); 112 } 113 114 static void ipi_call_dispatch (struct pt_regs *regs) 115 { 116 do_IRQ(MIPSCPU_INT_BASE + MIPS_CPU_IPI_CALL_IRQ, regs); 117 } 118 119 irqreturn_t ipi_resched_interrupt(int irq, void *dev_id, struct pt_regs *regs) 120 { 121 return IRQ_HANDLED; 122 } 123 124 irqreturn_t ipi_call_interrupt(int irq, void *dev_id, struct pt_regs *regs) 125 { 126 smp_call_function_interrupt(); 127 128 return IRQ_HANDLED; 129 } 130 131 static struct irqaction irq_resched = { 132 .handler = ipi_resched_interrupt, 133 .flags = IRQF_DISABLED, 134 .name = "IPI_resched" 135 }; 136 137 static struct irqaction irq_call = { 138 .handler = ipi_call_interrupt, 139 .flags = IRQF_DISABLED, 140 .name = "IPI_call" 141 }; 142 143 /* 144 * Common setup before any secondaries are started 145 * Make sure all CPU's are in a sensible state before we boot any of the 146 * secondarys 147 */ 148 void plat_smp_setup(void) 149 { 150 unsigned long val; 151 int i, num; 152 153 #ifdef CONFIG_MIPS_MT_FPAFF 154 /* If we have an FPU, enroll ourselves in the FPU-full mask */ 155 if (cpu_has_fpu) 156 cpu_set(0, mt_fpu_cpumask); 157 #endif /* CONFIG_MIPS_MT_FPAFF */ 158 if (!cpu_has_mipsmt) 159 return; 160 161 /* disable MT so we can configure */ 162 dvpe(); 163 dmt(); 164 165 mips_mt_set_cpuoptions(); 166 167 /* Put MVPE's into 'configuration state' */ 168 set_c0_mvpcontrol(MVPCONTROL_VPC); 169 170 val = read_c0_mvpconf0(); 171 172 /* we'll always have more TC's than VPE's, so loop setting everything 173 to a sensible state */ 174 for (i = 0, num = 0; i <= ((val & MVPCONF0_PTC) >> MVPCONF0_PTC_SHIFT); i++) { 175 settc(i); 176 177 /* VPE's */ 178 if (i <= ((val & MVPCONF0_PVPE) >> MVPCONF0_PVPE_SHIFT)) { 179 180 /* deactivate all but vpe0 */ 181 if (i != 0) { 182 unsigned long tmp = read_vpe_c0_vpeconf0(); 183 184 tmp &= ~VPECONF0_VPA; 185 186 /* master VPE */ 187 tmp |= VPECONF0_MVP; 188 write_vpe_c0_vpeconf0(tmp); 189 190 /* Record this as available CPU */ 191 cpu_set(i, phys_cpu_present_map); 192 __cpu_number_map[i] = ++num; 193 __cpu_logical_map[num] = i; 194 } 195 196 /* disable multi-threading with TC's */ 197 write_vpe_c0_vpecontrol(read_vpe_c0_vpecontrol() & ~VPECONTROL_TE); 198 199 if (i != 0) { 200 write_vpe_c0_status((read_c0_status() & ~(ST0_IM | ST0_IE | ST0_KSU)) | ST0_CU0); 201 202 /* set config to be the same as vpe0, particularly kseg0 coherency alg */ 203 write_vpe_c0_config( read_c0_config()); 204 205 /* make sure there are no software interrupts pending */ 206 write_vpe_c0_cause(read_vpe_c0_cause() & ~(C_SW1|C_SW0)); 207 208 /* Propagate Config7 */ 209 write_vpe_c0_config7(read_c0_config7()); 210 } 211 212 } 213 214 /* TC's */ 215 216 if (i != 0) { 217 unsigned long tmp; 218 219 /* bind a TC to each VPE, May as well put all excess TC's 220 on the last VPE */ 221 if ( i >= (((val & MVPCONF0_PVPE) >> MVPCONF0_PVPE_SHIFT)+1) ) 222 write_tc_c0_tcbind(read_tc_c0_tcbind() | ((val & MVPCONF0_PVPE) >> MVPCONF0_PVPE_SHIFT) ); 223 else { 224 write_tc_c0_tcbind( read_tc_c0_tcbind() | i); 225 226 /* and set XTC */ 227 write_vpe_c0_vpeconf0( read_vpe_c0_vpeconf0() | (i << VPECONF0_XTC_SHIFT)); 228 } 229 230 tmp = read_tc_c0_tcstatus(); 231 232 /* mark not allocated and not dynamically allocatable */ 233 tmp &= ~(TCSTATUS_A | TCSTATUS_DA); 234 tmp |= TCSTATUS_IXMT; /* interrupt exempt */ 235 write_tc_c0_tcstatus(tmp); 236 237 write_tc_c0_tchalt(TCHALT_H); 238 } 239 } 240 241 /* Release config state */ 242 clear_c0_mvpcontrol(MVPCONTROL_VPC); 243 244 /* We'll wait until starting the secondaries before starting MVPE */ 245 246 printk(KERN_INFO "Detected %i available secondary CPU(s)\n", num); 247 } 248 249 void __init plat_prepare_cpus(unsigned int max_cpus) 250 { 251 /* set up ipi interrupts */ 252 if (cpu_has_vint) { 253 set_vi_handler (MIPS_CPU_IPI_RESCHED_IRQ, ipi_resched_dispatch); 254 set_vi_handler (MIPS_CPU_IPI_CALL_IRQ, ipi_call_dispatch); 255 } 256 257 cpu_ipi_resched_irq = MIPSCPU_INT_BASE + MIPS_CPU_IPI_RESCHED_IRQ; 258 cpu_ipi_call_irq = MIPSCPU_INT_BASE + MIPS_CPU_IPI_CALL_IRQ; 259 260 setup_irq(cpu_ipi_resched_irq, &irq_resched); 261 setup_irq(cpu_ipi_call_irq, &irq_call); 262 263 /* need to mark IPI's as IRQ_PER_CPU */ 264 irq_desc[cpu_ipi_resched_irq].status |= IRQ_PER_CPU; 265 irq_desc[cpu_ipi_call_irq].status |= IRQ_PER_CPU; 266 } 267 268 /* 269 * Setup the PC, SP, and GP of a secondary processor and start it 270 * running! 271 * smp_bootstrap is the place to resume from 272 * __KSTK_TOS(idle) is apparently the stack pointer 273 * (unsigned long)idle->thread_info the gp 274 * assumes a 1:1 mapping of TC => VPE 275 */ 276 void prom_boot_secondary(int cpu, struct task_struct *idle) 277 { 278 struct thread_info *gp = task_thread_info(idle); 279 dvpe(); 280 set_c0_mvpcontrol(MVPCONTROL_VPC); 281 282 settc(cpu); 283 284 /* restart */ 285 write_tc_c0_tcrestart((unsigned long)&smp_bootstrap); 286 287 /* enable the tc this vpe/cpu will be running */ 288 write_tc_c0_tcstatus((read_tc_c0_tcstatus() & ~TCSTATUS_IXMT) | TCSTATUS_A); 289 290 write_tc_c0_tchalt(0); 291 292 /* enable the VPE */ 293 write_vpe_c0_vpeconf0(read_vpe_c0_vpeconf0() | VPECONF0_VPA); 294 295 /* stack pointer */ 296 write_tc_gpr_sp( __KSTK_TOS(idle)); 297 298 /* global pointer */ 299 write_tc_gpr_gp((unsigned long)gp); 300 301 flush_icache_range((unsigned long)gp, 302 (unsigned long)(gp + sizeof(struct thread_info))); 303 304 /* finally out of configuration and into chaos */ 305 clear_c0_mvpcontrol(MVPCONTROL_VPC); 306 307 evpe(EVPE_ENABLE); 308 } 309 310 void prom_init_secondary(void) 311 { 312 write_c0_status((read_c0_status() & ~ST0_IM ) | 313 (STATUSF_IP0 | STATUSF_IP1 | STATUSF_IP7)); 314 } 315 316 void prom_smp_finish(void) 317 { 318 write_c0_compare(read_c0_count() + (8* mips_hpt_frequency/HZ)); 319 320 #ifdef CONFIG_MIPS_MT_FPAFF 321 /* If we have an FPU, enroll ourselves in the FPU-full mask */ 322 if (cpu_has_fpu) 323 cpu_set(smp_processor_id(), mt_fpu_cpumask); 324 #endif /* CONFIG_MIPS_MT_FPAFF */ 325 326 local_irq_enable(); 327 } 328 329 void prom_cpus_done(void) 330 { 331 } 332 333 void core_send_ipi(int cpu, unsigned int action) 334 { 335 int i; 336 unsigned long flags; 337 int vpflags; 338 339 local_irq_save (flags); 340 341 vpflags = dvpe(); /* cant access the other CPU's registers whilst MVPE enabled */ 342 343 switch (action) { 344 case SMP_CALL_FUNCTION: 345 i = C_SW1; 346 break; 347 348 case SMP_RESCHEDULE_YOURSELF: 349 default: 350 i = C_SW0; 351 break; 352 } 353 354 /* 1:1 mapping of vpe and tc... */ 355 settc(cpu); 356 write_vpe_c0_cause(read_vpe_c0_cause() | i); 357 evpe(vpflags); 358 359 local_irq_restore(flags); 360 } 361