1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * Copyright (C) 2013 Imagination Technologies 4 * Author: Paul Burton <paul.burton@mips.com> 5 */ 6 7 #include <linux/cpu.h> 8 #include <linux/delay.h> 9 #include <linux/io.h> 10 #include <linux/memblock.h> 11 #include <linux/sched/task_stack.h> 12 #include <linux/sched/hotplug.h> 13 #include <linux/slab.h> 14 #include <linux/smp.h> 15 #include <linux/types.h> 16 #include <linux/irq.h> 17 18 #include <asm/bcache.h> 19 #include <asm/mips-cps.h> 20 #include <asm/mips_mt.h> 21 #include <asm/mipsregs.h> 22 #include <asm/pm-cps.h> 23 #include <asm/r4kcache.h> 24 #include <asm/regdef.h> 25 #include <asm/smp.h> 26 #include <asm/smp-cps.h> 27 #include <asm/time.h> 28 #include <asm/uasm.h> 29 30 #define BEV_VEC_SIZE 0x500 31 #define BEV_VEC_ALIGN 0x1000 32 33 enum label_id { 34 label_not_nmi = 1, 35 }; 36 37 UASM_L_LA(_not_nmi) 38 39 static u64 core_entry_reg; 40 static phys_addr_t cps_vec_pa; 41 42 struct cluster_boot_config *mips_cps_cluster_bootcfg; 43 44 static void power_up_other_cluster(unsigned int cluster) 45 { 46 u32 stat, seq_state; 47 unsigned int timeout; 48 49 mips_cm_lock_other(cluster, CM_GCR_Cx_OTHER_CORE_CM, 0, 50 CM_GCR_Cx_OTHER_BLOCK_LOCAL); 51 stat = read_cpc_co_stat_conf(); 52 mips_cm_unlock_other(); 53 54 seq_state = stat & CPC_Cx_STAT_CONF_SEQSTATE; 55 seq_state >>= __ffs(CPC_Cx_STAT_CONF_SEQSTATE); 56 if (seq_state == CPC_Cx_STAT_CONF_SEQSTATE_U5) 57 return; 58 59 /* Set endianness & power up the CM */ 60 mips_cm_lock_other(cluster, 0, 0, CM_GCR_Cx_OTHER_BLOCK_GLOBAL); 61 write_cpc_redir_sys_config(IS_ENABLED(CONFIG_CPU_BIG_ENDIAN)); 62 write_cpc_redir_pwrup_ctl(1); 63 mips_cm_unlock_other(); 64 65 /* Wait for the CM to start up */ 66 timeout = 1000; 67 mips_cm_lock_other(cluster, CM_GCR_Cx_OTHER_CORE_CM, 0, 68 CM_GCR_Cx_OTHER_BLOCK_LOCAL); 69 while (1) { 70 stat = read_cpc_co_stat_conf(); 71 seq_state = stat & CPC_Cx_STAT_CONF_SEQSTATE; 72 seq_state >>= __ffs(CPC_Cx_STAT_CONF_SEQSTATE); 73 if (seq_state == CPC_Cx_STAT_CONF_SEQSTATE_U5) 74 break; 75 76 if (timeout) { 77 mdelay(1); 78 timeout--; 79 } else { 80 pr_warn("Waiting for cluster %u CM to power up... STAT_CONF=0x%x\n", 81 cluster, stat); 82 mdelay(1000); 83 } 84 } 85 86 mips_cm_unlock_other(); 87 } 88 89 static unsigned __init core_vpe_count(unsigned int cluster, unsigned core) 90 { 91 return min(smp_max_threads, mips_cps_numvps(cluster, core)); 92 } 93 94 static void __init *mips_cps_build_core_entry(void *addr) 95 { 96 extern void (*nmi_handler)(void); 97 u32 *p = addr; 98 u32 val; 99 struct uasm_label labels[2]; 100 struct uasm_reloc relocs[2]; 101 struct uasm_label *l = labels; 102 struct uasm_reloc *r = relocs; 103 104 memset(labels, 0, sizeof(labels)); 105 memset(relocs, 0, sizeof(relocs)); 106 107 uasm_i_mfc0(&p, GPR_K0, C0_STATUS); 108 UASM_i_LA(&p, GPR_T9, ST0_NMI); 109 uasm_i_and(&p, GPR_K0, GPR_K0, GPR_T9); 110 111 uasm_il_bnez(&p, &r, GPR_K0, label_not_nmi); 112 uasm_i_nop(&p); 113 UASM_i_LA(&p, GPR_K0, (long)&nmi_handler); 114 115 uasm_l_not_nmi(&l, p); 116 117 val = CAUSEF_IV; 118 uasm_i_lui(&p, GPR_K0, val >> 16); 119 uasm_i_ori(&p, GPR_K0, GPR_K0, val & 0xffff); 120 uasm_i_mtc0(&p, GPR_K0, C0_CAUSE); 121 val = ST0_CU1 | ST0_CU0 | ST0_BEV | ST0_KX_IF_64; 122 uasm_i_lui(&p, GPR_K0, val >> 16); 123 uasm_i_ori(&p, GPR_K0, GPR_K0, val & 0xffff); 124 uasm_i_mtc0(&p, GPR_K0, C0_STATUS); 125 uasm_i_ehb(&p); 126 uasm_i_ori(&p, GPR_A0, 0, read_c0_config() & CONF_CM_CMASK); 127 UASM_i_LA(&p, GPR_A1, (long)mips_gcr_base); 128 #if defined(KBUILD_64BIT_SYM32) || defined(CONFIG_32BIT) 129 UASM_i_LA(&p, GPR_T9, CKSEG1ADDR(__pa_symbol(mips_cps_core_boot))); 130 #else 131 UASM_i_LA(&p, GPR_T9, TO_UNCAC(__pa_symbol(mips_cps_core_boot))); 132 #endif 133 uasm_i_jr(&p, GPR_T9); 134 uasm_i_nop(&p); 135 136 uasm_resolve_relocs(relocs, labels); 137 138 return p; 139 } 140 141 static bool __init check_64bit_reset(void) 142 { 143 bool cx_64bit_reset = false; 144 145 mips_cm_lock_other(0, 0, 0, CM_GCR_Cx_OTHER_BLOCK_LOCAL); 146 write_gcr_co_reset64_base(CM_GCR_Cx_RESET64_BASE_BEVEXCBASE); 147 if ((read_gcr_co_reset64_base() & CM_GCR_Cx_RESET64_BASE_BEVEXCBASE) == 148 CM_GCR_Cx_RESET64_BASE_BEVEXCBASE) 149 cx_64bit_reset = true; 150 mips_cm_unlock_other(); 151 152 return cx_64bit_reset; 153 } 154 155 static int __init allocate_cps_vecs(void) 156 { 157 /* Try to allocate in KSEG1 first */ 158 cps_vec_pa = memblock_phys_alloc_range(BEV_VEC_SIZE, BEV_VEC_ALIGN, 159 0x0, CSEGX_SIZE - 1); 160 161 if (cps_vec_pa) 162 core_entry_reg = CKSEG1ADDR(cps_vec_pa) & 163 CM_GCR_Cx_RESET_BASE_BEVEXCBASE; 164 165 if (!cps_vec_pa && mips_cm_is64) { 166 phys_addr_t end; 167 168 if (check_64bit_reset()) { 169 pr_info("VP Local Reset Exception Base support 47 bits address\n"); 170 end = MEMBLOCK_ALLOC_ANYWHERE; 171 } else { 172 end = SZ_4G - 1; 173 } 174 cps_vec_pa = memblock_phys_alloc_range(BEV_VEC_SIZE, BEV_VEC_ALIGN, 0, end); 175 if (cps_vec_pa) { 176 if (check_64bit_reset()) 177 core_entry_reg = (cps_vec_pa & CM_GCR_Cx_RESET64_BASE_BEVEXCBASE) | 178 CM_GCR_Cx_RESET_BASE_MODE; 179 else 180 core_entry_reg = (cps_vec_pa & CM_GCR_Cx_RESET_BASE_BEVEXCBASE) | 181 CM_GCR_Cx_RESET_BASE_MODE; 182 } 183 } 184 185 if (!cps_vec_pa) 186 return -ENOMEM; 187 188 return 0; 189 } 190 191 static void __init setup_cps_vecs(void) 192 { 193 void *cps_vec; 194 195 cps_vec = (void *)CKSEG1ADDR_OR_64BIT(cps_vec_pa); 196 mips_cps_build_core_entry(cps_vec); 197 198 memcpy(cps_vec + 0x200, &excep_tlbfill, 0x80); 199 memcpy(cps_vec + 0x280, &excep_xtlbfill, 0x80); 200 memcpy(cps_vec + 0x300, &excep_cache, 0x80); 201 memcpy(cps_vec + 0x380, &excep_genex, 0x80); 202 memcpy(cps_vec + 0x400, &excep_intex, 0x80); 203 memcpy(cps_vec + 0x480, &excep_ejtag, 0x80); 204 205 /* Make sure no prefetched data in cache */ 206 blast_inv_dcache_range(CKSEG0ADDR_OR_64BIT(cps_vec_pa), CKSEG0ADDR_OR_64BIT(cps_vec_pa) + BEV_VEC_SIZE); 207 bc_inv(CKSEG0ADDR_OR_64BIT(cps_vec_pa), BEV_VEC_SIZE); 208 __sync(); 209 } 210 211 static void __init cps_smp_setup(void) 212 { 213 unsigned int nclusters, ncores, nvpes, core_vpes; 214 int cl, c, v; 215 216 /* Detect & record VPE topology */ 217 nvpes = 0; 218 nclusters = mips_cps_numclusters(); 219 pr_info("%s topology ", cpu_has_mips_r6 ? "VP" : "VPE"); 220 for (cl = 0; cl < nclusters; cl++) { 221 if (cl > 0) 222 pr_cont(","); 223 pr_cont("{"); 224 225 if (mips_cm_revision() >= CM_REV_CM3_5) 226 power_up_other_cluster(cl); 227 228 ncores = mips_cps_numcores(cl); 229 for (c = 0; c < ncores; c++) { 230 core_vpes = core_vpe_count(cl, c); 231 232 if (c > 0) 233 pr_cont(","); 234 pr_cont("%u", core_vpes); 235 236 /* Use the number of VPEs in cluster 0 core 0 for smp_num_siblings */ 237 if (!cl && !c) 238 smp_num_siblings = core_vpes; 239 cpumask_set_cpu(nvpes, &__cpu_primary_thread_mask); 240 241 for (v = 0; v < min_t(int, core_vpes, NR_CPUS - nvpes); v++) { 242 cpu_set_cluster(&cpu_data[nvpes + v], cl); 243 cpu_set_core(&cpu_data[nvpes + v], c); 244 cpu_set_vpe_id(&cpu_data[nvpes + v], v); 245 } 246 247 nvpes += core_vpes; 248 } 249 250 pr_cont("}"); 251 } 252 pr_cont(" total %u\n", nvpes); 253 254 /* Indicate present CPUs (CPU being synonymous with VPE) */ 255 for (v = 0; v < min_t(unsigned, nvpes, NR_CPUS); v++) { 256 set_cpu_possible(v, true); 257 set_cpu_present(v, true); 258 __cpu_number_map[v] = v; 259 __cpu_logical_map[v] = v; 260 } 261 262 /* Set a coherent default CCA (CWB) */ 263 change_c0_config(CONF_CM_CMASK, 0x5); 264 265 /* Initialise core 0 */ 266 mips_cps_core_init(); 267 268 /* Make core 0 coherent with everything */ 269 write_gcr_cl_coherence(0xff); 270 271 if (allocate_cps_vecs()) 272 pr_err("Failed to allocate CPS vectors\n"); 273 274 if (core_entry_reg && mips_cm_revision() >= CM_REV_CM3) 275 write_gcr_bev_base(core_entry_reg); 276 277 #ifdef CONFIG_MIPS_MT_FPAFF 278 /* If we have an FPU, enroll ourselves in the FPU-full mask */ 279 if (cpu_has_fpu) 280 cpumask_set_cpu(0, &mt_fpu_cpumask); 281 #endif /* CONFIG_MIPS_MT_FPAFF */ 282 } 283 284 static void __init cps_prepare_cpus(unsigned int max_cpus) 285 { 286 unsigned int nclusters, ncores, core_vpes, c, cl, cca; 287 bool cca_unsuitable, cores_limited; 288 struct cluster_boot_config *cluster_bootcfg; 289 struct core_boot_config *core_bootcfg; 290 291 mips_mt_set_cpuoptions(); 292 293 if (!core_entry_reg) { 294 pr_err("core_entry address unsuitable, disabling smp-cps\n"); 295 goto err_out; 296 } 297 298 /* Detect whether the CCA is unsuited to multi-core SMP */ 299 cca = read_c0_config() & CONF_CM_CMASK; 300 switch (cca) { 301 case 0x4: /* CWBE */ 302 case 0x5: /* CWB */ 303 /* The CCA is coherent, multi-core is fine */ 304 cca_unsuitable = false; 305 break; 306 307 default: 308 /* CCA is not coherent, multi-core is not usable */ 309 cca_unsuitable = true; 310 } 311 312 /* Warn the user if the CCA prevents multi-core */ 313 cores_limited = false; 314 if (cca_unsuitable || cpu_has_dc_aliases) { 315 for_each_present_cpu(c) { 316 if (cpus_are_siblings(smp_processor_id(), c)) 317 continue; 318 319 set_cpu_present(c, false); 320 cores_limited = true; 321 } 322 } 323 if (cores_limited) 324 pr_warn("Using only one core due to %s%s%s\n", 325 cca_unsuitable ? "unsuitable CCA" : "", 326 (cca_unsuitable && cpu_has_dc_aliases) ? " & " : "", 327 cpu_has_dc_aliases ? "dcache aliasing" : ""); 328 329 setup_cps_vecs(); 330 331 /* Allocate cluster boot configuration structs */ 332 nclusters = mips_cps_numclusters(); 333 mips_cps_cluster_bootcfg = kcalloc(nclusters, 334 sizeof(*mips_cps_cluster_bootcfg), 335 GFP_KERNEL); 336 337 if (nclusters > 1) 338 mips_cm_update_property(); 339 340 for (cl = 0; cl < nclusters; cl++) { 341 /* Allocate core boot configuration structs */ 342 ncores = mips_cps_numcores(cl); 343 core_bootcfg = kcalloc(ncores, sizeof(*core_bootcfg), 344 GFP_KERNEL); 345 if (!core_bootcfg) 346 goto err_out; 347 mips_cps_cluster_bootcfg[cl].core_config = core_bootcfg; 348 349 mips_cps_cluster_bootcfg[cl].core_power = 350 kcalloc(BITS_TO_LONGS(ncores), sizeof(unsigned long), 351 GFP_KERNEL); 352 353 /* Allocate VPE boot configuration structs */ 354 for (c = 0; c < ncores; c++) { 355 core_vpes = core_vpe_count(cl, c); 356 core_bootcfg[c].vpe_config = kcalloc(core_vpes, 357 sizeof(*core_bootcfg[c].vpe_config), 358 GFP_KERNEL); 359 if (!core_bootcfg[c].vpe_config) 360 goto err_out; 361 } 362 } 363 364 /* Mark this CPU as powered up & booted */ 365 cl = cpu_cluster(¤t_cpu_data); 366 c = cpu_core(¤t_cpu_data); 367 cluster_bootcfg = &mips_cps_cluster_bootcfg[cl]; 368 cpu_smt_set_num_threads(core_vpes, core_vpes); 369 core_bootcfg = &cluster_bootcfg->core_config[c]; 370 bitmap_set(cluster_bootcfg->core_power, cpu_core(¤t_cpu_data), 1); 371 atomic_set(&core_bootcfg->vpe_mask, 1 << cpu_vpe_id(¤t_cpu_data)); 372 373 return; 374 err_out: 375 /* Clean up allocations */ 376 if (mips_cps_cluster_bootcfg) { 377 for (cl = 0; cl < nclusters; cl++) { 378 cluster_bootcfg = &mips_cps_cluster_bootcfg[cl]; 379 ncores = mips_cps_numcores(cl); 380 for (c = 0; c < ncores; c++) { 381 core_bootcfg = &cluster_bootcfg->core_config[c]; 382 kfree(core_bootcfg->vpe_config); 383 } 384 kfree(mips_cps_cluster_bootcfg[c].core_config); 385 } 386 kfree(mips_cps_cluster_bootcfg); 387 mips_cps_cluster_bootcfg = NULL; 388 } 389 390 /* Effectively disable SMP by declaring CPUs not present */ 391 for_each_possible_cpu(c) { 392 if (c == 0) 393 continue; 394 set_cpu_present(c, false); 395 } 396 } 397 398 static void init_cluster_l2(void) 399 { 400 u32 l2_cfg, l2sm_cop, result; 401 402 while (!mips_cm_is_l2_hci_broken) { 403 l2_cfg = read_gcr_redir_l2_ram_config(); 404 405 /* If HCI is not supported, use the state machine below */ 406 if (!(l2_cfg & CM_GCR_L2_RAM_CONFIG_PRESENT)) 407 break; 408 if (!(l2_cfg & CM_GCR_L2_RAM_CONFIG_HCI_SUPPORTED)) 409 break; 410 411 /* If the HCI_DONE bit is set, we're finished */ 412 if (l2_cfg & CM_GCR_L2_RAM_CONFIG_HCI_DONE) 413 return; 414 } 415 416 l2sm_cop = read_gcr_redir_l2sm_cop(); 417 if (WARN(!(l2sm_cop & CM_GCR_L2SM_COP_PRESENT), 418 "L2 init not supported on this system yet")) 419 return; 420 421 /* Clear L2 tag registers */ 422 write_gcr_redir_l2_tag_state(0); 423 write_gcr_redir_l2_ecc(0); 424 425 /* Ensure the L2 tag writes complete before the state machine starts */ 426 mb(); 427 428 /* Wait for the L2 state machine to be idle */ 429 do { 430 l2sm_cop = read_gcr_redir_l2sm_cop(); 431 } while (l2sm_cop & CM_GCR_L2SM_COP_RUNNING); 432 433 /* Start a store tag operation */ 434 l2sm_cop = CM_GCR_L2SM_COP_TYPE_IDX_STORETAG; 435 l2sm_cop <<= __ffs(CM_GCR_L2SM_COP_TYPE); 436 l2sm_cop |= CM_GCR_L2SM_COP_CMD_START; 437 write_gcr_redir_l2sm_cop(l2sm_cop); 438 439 /* Ensure the state machine starts before we poll for completion */ 440 mb(); 441 442 /* Wait for the operation to be complete */ 443 do { 444 l2sm_cop = read_gcr_redir_l2sm_cop(); 445 result = l2sm_cop & CM_GCR_L2SM_COP_RESULT; 446 result >>= __ffs(CM_GCR_L2SM_COP_RESULT); 447 } while (!result); 448 449 WARN(result != CM_GCR_L2SM_COP_RESULT_DONE_OK, 450 "L2 state machine failed cache init with error %u\n", result); 451 } 452 453 static void boot_core(unsigned int cluster, unsigned int core, 454 unsigned int vpe_id) 455 { 456 struct cluster_boot_config *cluster_cfg; 457 u32 access, stat, seq_state; 458 unsigned int timeout, ncores; 459 460 cluster_cfg = &mips_cps_cluster_bootcfg[cluster]; 461 ncores = mips_cps_numcores(cluster); 462 463 if ((cluster != cpu_cluster(¤t_cpu_data)) && 464 bitmap_empty(cluster_cfg->core_power, ncores)) { 465 power_up_other_cluster(cluster); 466 467 mips_cm_lock_other(cluster, core, 0, 468 CM_GCR_Cx_OTHER_BLOCK_GLOBAL); 469 470 /* Ensure cluster GCRs are where we expect */ 471 write_gcr_redir_base(read_gcr_base()); 472 write_gcr_redir_cpc_base(read_gcr_cpc_base()); 473 write_gcr_redir_gic_base(read_gcr_gic_base()); 474 475 init_cluster_l2(); 476 477 /* Mirror L2 configuration */ 478 write_gcr_redir_l2_only_sync_base(read_gcr_l2_only_sync_base()); 479 write_gcr_redir_l2_pft_control(read_gcr_l2_pft_control()); 480 write_gcr_redir_l2_pft_control_b(read_gcr_l2_pft_control_b()); 481 482 /* Mirror ECC/parity setup */ 483 write_gcr_redir_err_control(read_gcr_err_control()); 484 485 /* Set BEV base */ 486 write_gcr_redir_bev_base(core_entry_reg); 487 488 mips_cm_unlock_other(); 489 } 490 491 if (cluster != cpu_cluster(¤t_cpu_data)) { 492 mips_cm_lock_other(cluster, core, 0, 493 CM_GCR_Cx_OTHER_BLOCK_GLOBAL); 494 495 /* Ensure the core can access the GCRs */ 496 access = read_gcr_redir_access(); 497 access |= BIT(core); 498 write_gcr_redir_access(access); 499 500 mips_cm_unlock_other(); 501 } else { 502 /* Ensure the core can access the GCRs */ 503 access = read_gcr_access(); 504 access |= BIT(core); 505 write_gcr_access(access); 506 } 507 508 /* Select the appropriate core */ 509 mips_cm_lock_other(cluster, core, 0, CM_GCR_Cx_OTHER_BLOCK_LOCAL); 510 511 /* Set its reset vector */ 512 if (mips_cm_is64) 513 write_gcr_co_reset64_base(core_entry_reg); 514 else 515 write_gcr_co_reset_base(core_entry_reg); 516 517 /* Ensure its coherency is disabled */ 518 write_gcr_co_coherence(0); 519 520 /* Start it with the legacy memory map and exception base */ 521 write_gcr_co_reset_ext_base(CM_GCR_Cx_RESET_EXT_BASE_UEB); 522 523 /* Ensure the core can access the GCRs */ 524 if (mips_cm_revision() < CM_REV_CM3) 525 set_gcr_access(1 << core); 526 else 527 set_gcr_access_cm3(1 << core); 528 529 if (mips_cpc_present()) { 530 /* Reset the core */ 531 mips_cpc_lock_other(core); 532 533 if (mips_cm_revision() >= CM_REV_CM3) { 534 /* Run only the requested VP following the reset */ 535 write_cpc_co_vp_stop(0xf); 536 write_cpc_co_vp_run(1 << vpe_id); 537 538 /* 539 * Ensure that the VP_RUN register is written before the 540 * core leaves reset. 541 */ 542 wmb(); 543 } 544 545 write_cpc_co_cmd(CPC_Cx_CMD_RESET); 546 547 timeout = 100; 548 while (true) { 549 stat = read_cpc_co_stat_conf(); 550 seq_state = stat & CPC_Cx_STAT_CONF_SEQSTATE; 551 seq_state >>= __ffs(CPC_Cx_STAT_CONF_SEQSTATE); 552 553 /* U6 == coherent execution, ie. the core is up */ 554 if (seq_state == CPC_Cx_STAT_CONF_SEQSTATE_U6) 555 break; 556 557 /* Delay a little while before we start warning */ 558 if (timeout) { 559 timeout--; 560 mdelay(10); 561 continue; 562 } 563 564 pr_warn("Waiting for core %u to start... STAT_CONF=0x%x\n", 565 core, stat); 566 mdelay(1000); 567 } 568 569 mips_cpc_unlock_other(); 570 } else { 571 /* Take the core out of reset */ 572 write_gcr_co_reset_release(0); 573 } 574 575 mips_cm_unlock_other(); 576 577 /* The core is now powered up */ 578 bitmap_set(cluster_cfg->core_power, core, 1); 579 580 /* 581 * Restore CM_PWRUP=0 so that the CM can power down if all the cores in 582 * the cluster do (eg. if they're all removed via hotplug. 583 */ 584 if (mips_cm_revision() >= CM_REV_CM3_5) { 585 mips_cm_lock_other(cluster, 0, 0, CM_GCR_Cx_OTHER_BLOCK_GLOBAL); 586 write_cpc_redir_pwrup_ctl(0); 587 mips_cm_unlock_other(); 588 } 589 } 590 591 static void remote_vpe_boot(void *dummy) 592 { 593 unsigned int cluster = cpu_cluster(¤t_cpu_data); 594 unsigned core = cpu_core(¤t_cpu_data); 595 struct cluster_boot_config *cluster_cfg = 596 &mips_cps_cluster_bootcfg[cluster]; 597 struct core_boot_config *core_cfg = &cluster_cfg->core_config[core]; 598 599 mips_cps_boot_vpes(core_cfg, cpu_vpe_id(¤t_cpu_data)); 600 } 601 602 static int cps_boot_secondary(int cpu, struct task_struct *idle) 603 { 604 unsigned int cluster = cpu_cluster(&cpu_data[cpu]); 605 unsigned core = cpu_core(&cpu_data[cpu]); 606 unsigned vpe_id = cpu_vpe_id(&cpu_data[cpu]); 607 struct cluster_boot_config *cluster_cfg = 608 &mips_cps_cluster_bootcfg[cluster]; 609 struct core_boot_config *core_cfg = &cluster_cfg->core_config[core]; 610 struct vpe_boot_config *vpe_cfg = &core_cfg->vpe_config[vpe_id]; 611 unsigned int remote; 612 int err; 613 614 vpe_cfg->pc = (unsigned long)&smp_bootstrap; 615 vpe_cfg->sp = __KSTK_TOS(idle); 616 vpe_cfg->gp = (unsigned long)task_thread_info(idle); 617 618 atomic_or(1 << cpu_vpe_id(&cpu_data[cpu]), &core_cfg->vpe_mask); 619 620 preempt_disable(); 621 622 if (!test_bit(core, cluster_cfg->core_power)) { 623 /* Boot a VPE on a powered down core */ 624 boot_core(cluster, core, vpe_id); 625 goto out; 626 } 627 628 if (cpu_has_vp) { 629 mips_cm_lock_other(cluster, core, vpe_id, 630 CM_GCR_Cx_OTHER_BLOCK_LOCAL); 631 if (mips_cm_is64) 632 write_gcr_co_reset64_base(core_entry_reg); 633 else 634 write_gcr_co_reset_base(core_entry_reg); 635 mips_cm_unlock_other(); 636 } 637 638 if (!cpus_are_siblings(cpu, smp_processor_id())) { 639 /* Boot a VPE on another powered up core */ 640 for (remote = 0; remote < NR_CPUS; remote++) { 641 if (!cpus_are_siblings(cpu, remote)) 642 continue; 643 if (cpu_online(remote)) 644 break; 645 } 646 if (remote >= NR_CPUS) { 647 pr_crit("No online CPU in core %u to start CPU%d\n", 648 core, cpu); 649 goto out; 650 } 651 652 err = smp_call_function_single(remote, remote_vpe_boot, 653 NULL, 1); 654 if (err) 655 panic("Failed to call remote CPU\n"); 656 goto out; 657 } 658 659 BUG_ON(!cpu_has_mipsmt && !cpu_has_vp); 660 661 /* Boot a VPE on this core */ 662 mips_cps_boot_vpes(core_cfg, vpe_id); 663 out: 664 preempt_enable(); 665 return 0; 666 } 667 668 static void cps_init_secondary(void) 669 { 670 int core = cpu_core(¤t_cpu_data); 671 672 /* Disable MT - we only want to run 1 TC per VPE */ 673 if (cpu_has_mipsmt) 674 dmt(); 675 676 if (mips_cm_revision() >= CM_REV_CM3) { 677 unsigned int ident = read_gic_vl_ident(); 678 679 /* 680 * Ensure that our calculation of the VP ID matches up with 681 * what the GIC reports, otherwise we'll have configured 682 * interrupts incorrectly. 683 */ 684 BUG_ON(ident != mips_cm_vp_id(smp_processor_id())); 685 } 686 687 if (core > 0 && !read_gcr_cl_coherence()) 688 pr_warn("Core %u is not in coherent domain\n", core); 689 690 if (cpu_has_veic) 691 clear_c0_status(ST0_IM); 692 else 693 change_c0_status(ST0_IM, STATUSF_IP2 | STATUSF_IP3 | 694 STATUSF_IP4 | STATUSF_IP5 | 695 STATUSF_IP6 | STATUSF_IP7); 696 } 697 698 static void cps_smp_finish(void) 699 { 700 write_c0_compare(read_c0_count() + (8 * mips_hpt_frequency / HZ)); 701 702 #ifdef CONFIG_MIPS_MT_FPAFF 703 /* If we have an FPU, enroll ourselves in the FPU-full mask */ 704 if (cpu_has_fpu) 705 cpumask_set_cpu(smp_processor_id(), &mt_fpu_cpumask); 706 #endif /* CONFIG_MIPS_MT_FPAFF */ 707 708 local_irq_enable(); 709 } 710 711 #if defined(CONFIG_HOTPLUG_CPU) || defined(CONFIG_KEXEC_CORE) 712 713 enum cpu_death { 714 CPU_DEATH_HALT, 715 CPU_DEATH_POWER, 716 }; 717 718 static void cps_shutdown_this_cpu(enum cpu_death death) 719 { 720 unsigned int cpu, core, vpe_id; 721 722 cpu = smp_processor_id(); 723 core = cpu_core(&cpu_data[cpu]); 724 725 if (death == CPU_DEATH_HALT) { 726 vpe_id = cpu_vpe_id(&cpu_data[cpu]); 727 728 pr_debug("Halting core %d VP%d\n", core, vpe_id); 729 if (cpu_has_mipsmt) { 730 /* Halt this TC */ 731 write_c0_tchalt(TCHALT_H); 732 instruction_hazard(); 733 } else if (cpu_has_vp) { 734 write_cpc_cl_vp_stop(1 << vpe_id); 735 736 /* Ensure that the VP_STOP register is written */ 737 wmb(); 738 } 739 } else { 740 if (IS_ENABLED(CONFIG_HOTPLUG_CPU)) { 741 pr_debug("Gating power to core %d\n", core); 742 /* Power down the core */ 743 cps_pm_enter_state(CPS_PM_POWER_GATED); 744 } 745 } 746 } 747 748 #ifdef CONFIG_KEXEC_CORE 749 750 static void cps_kexec_nonboot_cpu(void) 751 { 752 if (cpu_has_mipsmt || cpu_has_vp) 753 cps_shutdown_this_cpu(CPU_DEATH_HALT); 754 else 755 cps_shutdown_this_cpu(CPU_DEATH_POWER); 756 } 757 758 #endif /* CONFIG_KEXEC_CORE */ 759 760 #endif /* CONFIG_HOTPLUG_CPU || CONFIG_KEXEC_CORE */ 761 762 #ifdef CONFIG_HOTPLUG_CPU 763 764 static int cps_cpu_disable(void) 765 { 766 unsigned cpu = smp_processor_id(); 767 struct cluster_boot_config *cluster_cfg; 768 struct core_boot_config *core_cfg; 769 770 if (!cps_pm_support_state(CPS_PM_POWER_GATED)) 771 return -EINVAL; 772 773 cluster_cfg = &mips_cps_cluster_bootcfg[cpu_cluster(¤t_cpu_data)]; 774 core_cfg = &cluster_cfg->core_config[cpu_core(¤t_cpu_data)]; 775 atomic_sub(1 << cpu_vpe_id(¤t_cpu_data), &core_cfg->vpe_mask); 776 smp_mb__after_atomic(); 777 set_cpu_online(cpu, false); 778 calculate_cpu_foreign_map(); 779 irq_migrate_all_off_this_cpu(); 780 781 return 0; 782 } 783 784 static unsigned cpu_death_sibling; 785 static enum cpu_death cpu_death; 786 787 void play_dead(void) 788 { 789 unsigned int cpu; 790 791 local_irq_disable(); 792 idle_task_exit(); 793 cpu = smp_processor_id(); 794 cpu_death = CPU_DEATH_POWER; 795 796 pr_debug("CPU%d going offline\n", cpu); 797 798 if (cpu_has_mipsmt || cpu_has_vp) { 799 /* Look for another online VPE within the core */ 800 for_each_online_cpu(cpu_death_sibling) { 801 if (!cpus_are_siblings(cpu, cpu_death_sibling)) 802 continue; 803 804 /* 805 * There is an online VPE within the core. Just halt 806 * this TC and leave the core alone. 807 */ 808 cpu_death = CPU_DEATH_HALT; 809 break; 810 } 811 } 812 813 cpuhp_ap_report_dead(); 814 815 cps_shutdown_this_cpu(cpu_death); 816 817 /* This should never be reached */ 818 panic("Failed to offline CPU %u", cpu); 819 } 820 821 static void wait_for_sibling_halt(void *ptr_cpu) 822 { 823 unsigned cpu = (unsigned long)ptr_cpu; 824 unsigned vpe_id = cpu_vpe_id(&cpu_data[cpu]); 825 unsigned halted; 826 unsigned long flags; 827 828 do { 829 local_irq_save(flags); 830 settc(vpe_id); 831 halted = read_tc_c0_tchalt(); 832 local_irq_restore(flags); 833 } while (!(halted & TCHALT_H)); 834 } 835 836 static void cps_cpu_die(unsigned int cpu) { } 837 838 static void cps_cleanup_dead_cpu(unsigned cpu) 839 { 840 unsigned int cluster = cpu_cluster(&cpu_data[cpu]); 841 unsigned core = cpu_core(&cpu_data[cpu]); 842 unsigned int vpe_id = cpu_vpe_id(&cpu_data[cpu]); 843 ktime_t fail_time; 844 unsigned stat; 845 int err; 846 struct cluster_boot_config *cluster_cfg; 847 848 cluster_cfg = &mips_cps_cluster_bootcfg[cluster]; 849 850 /* 851 * Now wait for the CPU to actually offline. Without doing this that 852 * offlining may race with one or more of: 853 * 854 * - Onlining the CPU again. 855 * - Powering down the core if another VPE within it is offlined. 856 * - A sibling VPE entering a non-coherent state. 857 * 858 * In the non-MT halt case (ie. infinite loop) the CPU is doing nothing 859 * with which we could race, so do nothing. 860 */ 861 if (cpu_death == CPU_DEATH_POWER) { 862 /* 863 * Wait for the core to enter a powered down or clock gated 864 * state, the latter happening when a JTAG probe is connected 865 * in which case the CPC will refuse to power down the core. 866 */ 867 fail_time = ktime_add_ms(ktime_get(), 2000); 868 do { 869 mips_cm_lock_other(0, core, 0, CM_GCR_Cx_OTHER_BLOCK_LOCAL); 870 mips_cpc_lock_other(core); 871 stat = read_cpc_co_stat_conf(); 872 stat &= CPC_Cx_STAT_CONF_SEQSTATE; 873 stat >>= __ffs(CPC_Cx_STAT_CONF_SEQSTATE); 874 mips_cpc_unlock_other(); 875 mips_cm_unlock_other(); 876 877 if (stat == CPC_Cx_STAT_CONF_SEQSTATE_D0 || 878 stat == CPC_Cx_STAT_CONF_SEQSTATE_D2 || 879 stat == CPC_Cx_STAT_CONF_SEQSTATE_U2) 880 break; 881 882 /* 883 * The core ought to have powered down, but didn't & 884 * now we don't really know what state it's in. It's 885 * likely that its _pwr_up pin has been wired to logic 886 * 1 & it powered back up as soon as we powered it 887 * down... 888 * 889 * The best we can do is warn the user & continue in 890 * the hope that the core is doing nothing harmful & 891 * might behave properly if we online it later. 892 */ 893 if (WARN(ktime_after(ktime_get(), fail_time), 894 "CPU%u hasn't powered down, seq. state %u\n", 895 cpu, stat)) 896 break; 897 } while (1); 898 899 /* Indicate the core is powered off */ 900 bitmap_clear(cluster_cfg->core_power, core, 1); 901 } else if (cpu_has_mipsmt) { 902 /* 903 * Have a CPU with access to the offlined CPUs registers wait 904 * for its TC to halt. 905 */ 906 err = smp_call_function_single(cpu_death_sibling, 907 wait_for_sibling_halt, 908 (void *)(unsigned long)cpu, 1); 909 if (err) 910 panic("Failed to call remote sibling CPU\n"); 911 } else if (cpu_has_vp) { 912 do { 913 mips_cm_lock_other(0, core, vpe_id, CM_GCR_Cx_OTHER_BLOCK_LOCAL); 914 stat = read_cpc_co_vp_running(); 915 mips_cm_unlock_other(); 916 } while (stat & (1 << vpe_id)); 917 } 918 } 919 920 #endif /* CONFIG_HOTPLUG_CPU */ 921 922 static const struct plat_smp_ops cps_smp_ops = { 923 .smp_setup = cps_smp_setup, 924 .prepare_cpus = cps_prepare_cpus, 925 .boot_secondary = cps_boot_secondary, 926 .init_secondary = cps_init_secondary, 927 .smp_finish = cps_smp_finish, 928 .send_ipi_single = mips_smp_send_ipi_single, 929 .send_ipi_mask = mips_smp_send_ipi_mask, 930 #ifdef CONFIG_HOTPLUG_CPU 931 .cpu_disable = cps_cpu_disable, 932 .cpu_die = cps_cpu_die, 933 .cleanup_dead_cpu = cps_cleanup_dead_cpu, 934 #endif 935 #ifdef CONFIG_KEXEC_CORE 936 .kexec_nonboot_cpu = cps_kexec_nonboot_cpu, 937 #endif 938 }; 939 940 bool mips_cps_smp_in_use(void) 941 { 942 extern const struct plat_smp_ops *mp_ops; 943 return mp_ops == &cps_smp_ops; 944 } 945 946 int register_cps_smp_ops(void) 947 { 948 if (!mips_cm_present()) { 949 pr_warn("MIPS CPS SMP unable to proceed without a CM\n"); 950 return -ENODEV; 951 } 952 953 /* check we have a GIC - we need one for IPIs */ 954 if (!(read_gcr_gic_status() & CM_GCR_GIC_STATUS_EX)) { 955 pr_warn("MIPS CPS SMP unable to proceed without a GIC\n"); 956 return -ENODEV; 957 } 958 959 register_smp_ops(&cps_smp_ops); 960 return 0; 961 } 962