1 /* 2 * Copyright (C) 2013 Imagination Technologies 3 * Author: Paul Burton <paul.burton@imgtec.com> 4 * 5 * This program is free software; you can redistribute it and/or modify it 6 * under the terms of the GNU General Public License as published by the 7 * Free Software Foundation; either version 2 of the License, or (at your 8 * option) any later version. 9 */ 10 11 #include <linux/io.h> 12 #include <linux/sched.h> 13 #include <linux/slab.h> 14 #include <linux/smp.h> 15 #include <linux/types.h> 16 17 #include <asm/cacheflush.h> 18 #include <asm/gic.h> 19 #include <asm/mips-cm.h> 20 #include <asm/mips-cpc.h> 21 #include <asm/mips_mt.h> 22 #include <asm/mipsregs.h> 23 #include <asm/smp-cps.h> 24 #include <asm/time.h> 25 #include <asm/uasm.h> 26 27 static DECLARE_BITMAP(core_power, NR_CPUS); 28 29 struct boot_config mips_cps_bootcfg; 30 31 static void init_core(void) 32 { 33 unsigned int nvpes, t; 34 u32 mvpconf0, vpeconf0, vpecontrol, tcstatus, tcbind, status; 35 36 if (!cpu_has_mipsmt) 37 return; 38 39 /* Enter VPE configuration state */ 40 dvpe(); 41 set_c0_mvpcontrol(MVPCONTROL_VPC); 42 43 /* Retrieve the count of VPEs in this core */ 44 mvpconf0 = read_c0_mvpconf0(); 45 nvpes = ((mvpconf0 & MVPCONF0_PVPE) >> MVPCONF0_PVPE_SHIFT) + 1; 46 smp_num_siblings = nvpes; 47 48 for (t = 1; t < nvpes; t++) { 49 /* Use a 1:1 mapping of TC index to VPE index */ 50 settc(t); 51 52 /* Bind 1 TC to this VPE */ 53 tcbind = read_tc_c0_tcbind(); 54 tcbind &= ~TCBIND_CURVPE; 55 tcbind |= t << TCBIND_CURVPE_SHIFT; 56 write_tc_c0_tcbind(tcbind); 57 58 /* Set exclusive TC, non-active, master */ 59 vpeconf0 = read_vpe_c0_vpeconf0(); 60 vpeconf0 &= ~(VPECONF0_XTC | VPECONF0_VPA); 61 vpeconf0 |= t << VPECONF0_XTC_SHIFT; 62 vpeconf0 |= VPECONF0_MVP; 63 write_vpe_c0_vpeconf0(vpeconf0); 64 65 /* Declare TC non-active, non-allocatable & interrupt exempt */ 66 tcstatus = read_tc_c0_tcstatus(); 67 tcstatus &= ~(TCSTATUS_A | TCSTATUS_DA); 68 tcstatus |= TCSTATUS_IXMT; 69 write_tc_c0_tcstatus(tcstatus); 70 71 /* Halt the TC */ 72 write_tc_c0_tchalt(TCHALT_H); 73 74 /* Allow only 1 TC to execute */ 75 vpecontrol = read_vpe_c0_vpecontrol(); 76 vpecontrol &= ~VPECONTROL_TE; 77 write_vpe_c0_vpecontrol(vpecontrol); 78 79 /* Copy (most of) Status from VPE 0 */ 80 status = read_c0_status(); 81 status &= ~(ST0_IM | ST0_IE | ST0_KSU); 82 status |= ST0_CU0; 83 write_vpe_c0_status(status); 84 85 /* Copy Config from VPE 0 */ 86 write_vpe_c0_config(read_c0_config()); 87 write_vpe_c0_config7(read_c0_config7()); 88 89 /* Ensure no software interrupts are pending */ 90 write_vpe_c0_cause(0); 91 92 /* Sync Count */ 93 write_vpe_c0_count(read_c0_count()); 94 } 95 96 /* Leave VPE configuration state */ 97 clear_c0_mvpcontrol(MVPCONTROL_VPC); 98 } 99 100 static void __init cps_smp_setup(void) 101 { 102 unsigned int ncores, nvpes, core_vpes; 103 int c, v; 104 u32 core_cfg, *entry_code; 105 106 /* Detect & record VPE topology */ 107 ncores = mips_cm_numcores(); 108 pr_info("VPE topology "); 109 for (c = nvpes = 0; c < ncores; c++) { 110 if (cpu_has_mipsmt && config_enabled(CONFIG_MIPS_MT_SMP)) { 111 write_gcr_cl_other(c << CM_GCR_Cx_OTHER_CORENUM_SHF); 112 core_cfg = read_gcr_co_config(); 113 core_vpes = ((core_cfg & CM_GCR_Cx_CONFIG_PVPE_MSK) >> 114 CM_GCR_Cx_CONFIG_PVPE_SHF) + 1; 115 } else { 116 core_vpes = 1; 117 } 118 119 pr_cont("%c%u", c ? ',' : '{', core_vpes); 120 121 for (v = 0; v < min_t(int, core_vpes, NR_CPUS - nvpes); v++) { 122 cpu_data[nvpes + v].core = c; 123 #ifdef CONFIG_MIPS_MT_SMP 124 cpu_data[nvpes + v].vpe_id = v; 125 #endif 126 } 127 128 nvpes += core_vpes; 129 } 130 pr_cont("} total %u\n", nvpes); 131 132 /* Indicate present CPUs (CPU being synonymous with VPE) */ 133 for (v = 0; v < min_t(unsigned, nvpes, NR_CPUS); v++) { 134 set_cpu_possible(v, true); 135 set_cpu_present(v, true); 136 __cpu_number_map[v] = v; 137 __cpu_logical_map[v] = v; 138 } 139 140 /* Core 0 is powered up (we're running on it) */ 141 bitmap_set(core_power, 0, 1); 142 143 /* Disable MT - we only want to run 1 TC per VPE */ 144 if (cpu_has_mipsmt) 145 dmt(); 146 147 /* Initialise core 0 */ 148 init_core(); 149 150 /* Patch the start of mips_cps_core_entry to provide the CM base */ 151 entry_code = (u32 *)&mips_cps_core_entry; 152 UASM_i_LA(&entry_code, 3, (long)mips_cm_base); 153 154 /* Make core 0 coherent with everything */ 155 write_gcr_cl_coherence(0xff); 156 } 157 158 static void __init cps_prepare_cpus(unsigned int max_cpus) 159 { 160 mips_mt_set_cpuoptions(); 161 } 162 163 static void boot_core(struct boot_config *cfg) 164 { 165 u32 access; 166 167 /* Select the appropriate core */ 168 write_gcr_cl_other(cfg->core << CM_GCR_Cx_OTHER_CORENUM_SHF); 169 170 /* Set its reset vector */ 171 write_gcr_co_reset_base(CKSEG1ADDR((unsigned long)mips_cps_core_entry)); 172 173 /* Ensure its coherency is disabled */ 174 write_gcr_co_coherence(0); 175 176 /* Ensure the core can access the GCRs */ 177 access = read_gcr_access(); 178 access |= 1 << (CM_GCR_ACCESS_ACCESSEN_SHF + cfg->core); 179 write_gcr_access(access); 180 181 /* Copy cfg */ 182 mips_cps_bootcfg = *cfg; 183 184 if (mips_cpc_present()) { 185 /* Select the appropriate core */ 186 write_cpc_cl_other(cfg->core << CPC_Cx_OTHER_CORENUM_SHF); 187 188 /* Reset the core */ 189 write_cpc_co_cmd(CPC_Cx_CMD_RESET); 190 } else { 191 /* Take the core out of reset */ 192 write_gcr_co_reset_release(0); 193 } 194 195 /* The core is now powered up */ 196 bitmap_set(core_power, cfg->core, 1); 197 } 198 199 static void boot_vpe(void *info) 200 { 201 struct boot_config *cfg = info; 202 u32 tcstatus, vpeconf0; 203 204 /* Enter VPE configuration state */ 205 dvpe(); 206 set_c0_mvpcontrol(MVPCONTROL_VPC); 207 208 settc(cfg->vpe); 209 210 /* Set the TC restart PC */ 211 write_tc_c0_tcrestart((unsigned long)&smp_bootstrap); 212 213 /* Activate the TC, allow interrupts */ 214 tcstatus = read_tc_c0_tcstatus(); 215 tcstatus &= ~TCSTATUS_IXMT; 216 tcstatus |= TCSTATUS_A; 217 write_tc_c0_tcstatus(tcstatus); 218 219 /* Clear the TC halt bit */ 220 write_tc_c0_tchalt(0); 221 222 /* Activate the VPE */ 223 vpeconf0 = read_vpe_c0_vpeconf0(); 224 vpeconf0 |= VPECONF0_VPA; 225 write_vpe_c0_vpeconf0(vpeconf0); 226 227 /* Set the stack & global pointer registers */ 228 write_tc_gpr_sp(cfg->sp); 229 write_tc_gpr_gp(cfg->gp); 230 231 /* Leave VPE configuration state */ 232 clear_c0_mvpcontrol(MVPCONTROL_VPC); 233 234 /* Enable other VPEs to execute */ 235 evpe(EVPE_ENABLE); 236 } 237 238 static void cps_boot_secondary(int cpu, struct task_struct *idle) 239 { 240 struct boot_config cfg; 241 unsigned int remote; 242 int err; 243 244 cfg.core = cpu_data[cpu].core; 245 cfg.vpe = cpu_vpe_id(&cpu_data[cpu]); 246 cfg.pc = (unsigned long)&smp_bootstrap; 247 cfg.sp = __KSTK_TOS(idle); 248 cfg.gp = (unsigned long)task_thread_info(idle); 249 250 if (!test_bit(cfg.core, core_power)) { 251 /* Boot a VPE on a powered down core */ 252 boot_core(&cfg); 253 return; 254 } 255 256 if (cfg.core != current_cpu_data.core) { 257 /* Boot a VPE on another powered up core */ 258 for (remote = 0; remote < NR_CPUS; remote++) { 259 if (cpu_data[remote].core != cfg.core) 260 continue; 261 if (cpu_online(remote)) 262 break; 263 } 264 BUG_ON(remote >= NR_CPUS); 265 266 err = smp_call_function_single(remote, boot_vpe, &cfg, 1); 267 if (err) 268 panic("Failed to call remote CPU\n"); 269 return; 270 } 271 272 BUG_ON(!cpu_has_mipsmt); 273 274 /* Boot a VPE on this core */ 275 boot_vpe(&cfg); 276 } 277 278 static void cps_init_secondary(void) 279 { 280 /* Disable MT - we only want to run 1 TC per VPE */ 281 if (cpu_has_mipsmt) 282 dmt(); 283 284 /* TODO: revisit this assumption once hotplug is implemented */ 285 if (cpu_vpe_id(¤t_cpu_data) == 0) 286 init_core(); 287 288 change_c0_status(ST0_IM, STATUSF_IP3 | STATUSF_IP4 | 289 STATUSF_IP6 | STATUSF_IP7); 290 } 291 292 static void cps_smp_finish(void) 293 { 294 write_c0_compare(read_c0_count() + (8 * mips_hpt_frequency / HZ)); 295 296 #ifdef CONFIG_MIPS_MT_FPAFF 297 /* If we have an FPU, enroll ourselves in the FPU-full mask */ 298 if (cpu_has_fpu) 299 cpu_set(smp_processor_id(), mt_fpu_cpumask); 300 #endif /* CONFIG_MIPS_MT_FPAFF */ 301 302 local_irq_enable(); 303 } 304 305 static void cps_cpus_done(void) 306 { 307 } 308 309 static struct plat_smp_ops cps_smp_ops = { 310 .smp_setup = cps_smp_setup, 311 .prepare_cpus = cps_prepare_cpus, 312 .boot_secondary = cps_boot_secondary, 313 .init_secondary = cps_init_secondary, 314 .smp_finish = cps_smp_finish, 315 .send_ipi_single = gic_send_ipi_single, 316 .send_ipi_mask = gic_send_ipi_mask, 317 .cpus_done = cps_cpus_done, 318 }; 319 320 int register_cps_smp_ops(void) 321 { 322 if (!mips_cm_present()) { 323 pr_warn("MIPS CPS SMP unable to proceed without a CM\n"); 324 return -ENODEV; 325 } 326 327 /* check we have a GIC - we need one for IPIs */ 328 if (!(read_gcr_gic_status() & CM_GCR_GIC_STATUS_EX_MSK)) { 329 pr_warn("MIPS CPS SMP unable to proceed without a GIC\n"); 330 return -ENODEV; 331 } 332 333 register_smp_ops(&cps_smp_ops); 334 return 0; 335 } 336