1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * Copyright (C) 2013 Imagination Technologies 4 * Author: Paul Burton <paul.burton@mips.com> 5 */ 6 7 #include <linux/cpu.h> 8 #include <linux/delay.h> 9 #include <linux/io.h> 10 #include <linux/memblock.h> 11 #include <linux/sched/task_stack.h> 12 #include <linux/sched/hotplug.h> 13 #include <linux/slab.h> 14 #include <linux/smp.h> 15 #include <linux/types.h> 16 #include <linux/irq.h> 17 18 #include <asm/bcache.h> 19 #include <asm/mips-cps.h> 20 #include <asm/mips_mt.h> 21 #include <asm/mipsregs.h> 22 #include <asm/pm-cps.h> 23 #include <asm/r4kcache.h> 24 #include <asm/regdef.h> 25 #include <asm/smp.h> 26 #include <asm/smp-cps.h> 27 #include <asm/time.h> 28 #include <asm/uasm.h> 29 30 #define BEV_VEC_SIZE 0x500 31 #define BEV_VEC_ALIGN 0x1000 32 33 enum label_id { 34 label_not_nmi = 1, 35 }; 36 37 UASM_L_LA(_not_nmi) 38 39 static u64 core_entry_reg; 40 static phys_addr_t cps_vec_pa; 41 42 struct cluster_boot_config *mips_cps_cluster_bootcfg; 43 44 static void power_up_other_cluster(unsigned int cluster) 45 { 46 u32 stat, seq_state; 47 unsigned int timeout; 48 49 mips_cm_lock_other(cluster, CM_GCR_Cx_OTHER_CORE_CM, 0, 50 CM_GCR_Cx_OTHER_BLOCK_LOCAL); 51 stat = read_cpc_co_stat_conf(); 52 mips_cm_unlock_other(); 53 54 seq_state = stat & CPC_Cx_STAT_CONF_SEQSTATE; 55 seq_state >>= __ffs(CPC_Cx_STAT_CONF_SEQSTATE); 56 if (seq_state == CPC_Cx_STAT_CONF_SEQSTATE_U5) 57 return; 58 59 /* Set endianness & power up the CM */ 60 mips_cm_lock_other(cluster, 0, 0, CM_GCR_Cx_OTHER_BLOCK_GLOBAL); 61 write_cpc_redir_sys_config(IS_ENABLED(CONFIG_CPU_BIG_ENDIAN)); 62 write_cpc_redir_pwrup_ctl(1); 63 mips_cm_unlock_other(); 64 65 /* Wait for the CM to start up */ 66 timeout = 1000; 67 mips_cm_lock_other(cluster, CM_GCR_Cx_OTHER_CORE_CM, 0, 68 CM_GCR_Cx_OTHER_BLOCK_LOCAL); 69 while (1) { 70 stat = read_cpc_co_stat_conf(); 71 seq_state = stat & CPC_Cx_STAT_CONF_SEQSTATE; 72 seq_state >>= __ffs(CPC_Cx_STAT_CONF_SEQSTATE); 73 if (seq_state == CPC_Cx_STAT_CONF_SEQSTATE_U5) 74 break; 75 76 if (timeout) { 77 mdelay(1); 78 timeout--; 79 } else { 80 pr_warn("Waiting for cluster %u CM to power up... STAT_CONF=0x%x\n", 81 cluster, stat); 82 mdelay(1000); 83 } 84 } 85 86 mips_cm_unlock_other(); 87 } 88 89 static unsigned __init core_vpe_count(unsigned int cluster, unsigned core) 90 { 91 return min(smp_max_threads, mips_cps_numvps(cluster, core)); 92 } 93 94 static void __init *mips_cps_build_core_entry(void *addr) 95 { 96 extern void (*nmi_handler)(void); 97 u32 *p = addr; 98 u32 val; 99 struct uasm_label labels[2]; 100 struct uasm_reloc relocs[2]; 101 struct uasm_label *l = labels; 102 struct uasm_reloc *r = relocs; 103 104 memset(labels, 0, sizeof(labels)); 105 memset(relocs, 0, sizeof(relocs)); 106 107 uasm_i_mfc0(&p, GPR_K0, C0_STATUS); 108 UASM_i_LA(&p, GPR_T9, ST0_NMI); 109 uasm_i_and(&p, GPR_K0, GPR_K0, GPR_T9); 110 111 uasm_il_bnez(&p, &r, GPR_K0, label_not_nmi); 112 uasm_i_nop(&p); 113 UASM_i_LA(&p, GPR_K0, (long)&nmi_handler); 114 115 uasm_l_not_nmi(&l, p); 116 117 val = CAUSEF_IV; 118 uasm_i_lui(&p, GPR_K0, val >> 16); 119 uasm_i_ori(&p, GPR_K0, GPR_K0, val & 0xffff); 120 uasm_i_mtc0(&p, GPR_K0, C0_CAUSE); 121 val = ST0_CU1 | ST0_CU0 | ST0_BEV | ST0_KX_IF_64; 122 uasm_i_lui(&p, GPR_K0, val >> 16); 123 uasm_i_ori(&p, GPR_K0, GPR_K0, val & 0xffff); 124 uasm_i_mtc0(&p, GPR_K0, C0_STATUS); 125 uasm_i_ehb(&p); 126 uasm_i_ori(&p, GPR_A0, 0, read_c0_config() & CONF_CM_CMASK); 127 UASM_i_LA(&p, GPR_A1, (long)mips_gcr_base); 128 #if defined(KBUILD_64BIT_SYM32) || defined(CONFIG_32BIT) 129 UASM_i_LA(&p, GPR_T9, CKSEG1ADDR(__pa_symbol(mips_cps_core_boot))); 130 #else 131 UASM_i_LA(&p, GPR_T9, TO_UNCAC(__pa_symbol(mips_cps_core_boot))); 132 #endif 133 uasm_i_jr(&p, GPR_T9); 134 uasm_i_nop(&p); 135 136 uasm_resolve_relocs(relocs, labels); 137 138 return p; 139 } 140 141 static bool __init check_64bit_reset(void) 142 { 143 bool cx_64bit_reset = false; 144 145 mips_cm_lock_other(0, 0, 0, CM_GCR_Cx_OTHER_BLOCK_LOCAL); 146 write_gcr_co_reset64_base(CM_GCR_Cx_RESET64_BASE_BEVEXCBASE); 147 if ((read_gcr_co_reset64_base() & CM_GCR_Cx_RESET64_BASE_BEVEXCBASE) == 148 CM_GCR_Cx_RESET64_BASE_BEVEXCBASE) 149 cx_64bit_reset = true; 150 mips_cm_unlock_other(); 151 152 return cx_64bit_reset; 153 } 154 155 static int __init allocate_cps_vecs(void) 156 { 157 /* Try to allocate in KSEG1 first */ 158 cps_vec_pa = memblock_phys_alloc_range(BEV_VEC_SIZE, BEV_VEC_ALIGN, 159 0x0, CSEGX_SIZE - 1); 160 161 if (cps_vec_pa) 162 core_entry_reg = CKSEG1ADDR(cps_vec_pa) & 163 CM_GCR_Cx_RESET_BASE_BEVEXCBASE; 164 165 if (!cps_vec_pa && mips_cm_is64) { 166 phys_addr_t end; 167 168 if (check_64bit_reset()) { 169 pr_info("VP Local Reset Exception Base support 47 bits address\n"); 170 end = MEMBLOCK_ALLOC_ANYWHERE; 171 } else { 172 end = SZ_4G - 1; 173 } 174 cps_vec_pa = memblock_phys_alloc_range(BEV_VEC_SIZE, BEV_VEC_ALIGN, 0, end); 175 if (cps_vec_pa) { 176 if (check_64bit_reset()) 177 core_entry_reg = (cps_vec_pa & CM_GCR_Cx_RESET64_BASE_BEVEXCBASE) | 178 CM_GCR_Cx_RESET_BASE_MODE; 179 else 180 core_entry_reg = (cps_vec_pa & CM_GCR_Cx_RESET_BASE_BEVEXCBASE) | 181 CM_GCR_Cx_RESET_BASE_MODE; 182 } 183 } 184 185 if (!cps_vec_pa) 186 return -ENOMEM; 187 188 return 0; 189 } 190 191 static void __init setup_cps_vecs(void) 192 { 193 void *cps_vec; 194 195 cps_vec = (void *)CKSEG1ADDR_OR_64BIT(cps_vec_pa); 196 mips_cps_build_core_entry(cps_vec); 197 198 memcpy(cps_vec + 0x200, &excep_tlbfill, 0x80); 199 memcpy(cps_vec + 0x280, &excep_xtlbfill, 0x80); 200 memcpy(cps_vec + 0x300, &excep_cache, 0x80); 201 memcpy(cps_vec + 0x380, &excep_genex, 0x80); 202 memcpy(cps_vec + 0x400, &excep_intex, 0x80); 203 memcpy(cps_vec + 0x480, &excep_ejtag, 0x80); 204 205 /* Make sure no prefetched data in cache */ 206 blast_inv_dcache_range(CKSEG0ADDR_OR_64BIT(cps_vec_pa), CKSEG0ADDR_OR_64BIT(cps_vec_pa) + BEV_VEC_SIZE); 207 bc_inv(CKSEG0ADDR_OR_64BIT(cps_vec_pa), BEV_VEC_SIZE); 208 __sync(); 209 } 210 211 static void __init cps_smp_setup(void) 212 { 213 unsigned int nclusters, ncores, nvpes, core_vpes; 214 int cl, c, v; 215 216 /* Detect & record VPE topology */ 217 nvpes = 0; 218 nclusters = mips_cps_numclusters(); 219 pr_info("%s topology ", cpu_has_mips_r6 ? "VP" : "VPE"); 220 for (cl = 0; cl < nclusters; cl++) { 221 if (cl > 0) 222 pr_cont(","); 223 pr_cont("{"); 224 225 if (mips_cm_revision() >= CM_REV_CM3_5) 226 power_up_other_cluster(cl); 227 228 ncores = mips_cps_numcores(cl); 229 for (c = 0; c < ncores; c++) { 230 core_vpes = core_vpe_count(cl, c); 231 232 if (c > 0) 233 pr_cont(","); 234 pr_cont("%u", core_vpes); 235 236 /* Use the number of VPEs in cluster 0 core 0 for smp_num_siblings */ 237 if (!cl && !c) 238 smp_num_siblings = core_vpes; 239 cpumask_set_cpu(nvpes, &__cpu_primary_thread_mask); 240 241 for (v = 0; v < min_t(int, core_vpes, NR_CPUS - nvpes); v++) { 242 cpu_set_cluster(&cpu_data[nvpes + v], cl); 243 cpu_set_core(&cpu_data[nvpes + v], c); 244 cpu_set_vpe_id(&cpu_data[nvpes + v], v); 245 } 246 247 nvpes += core_vpes; 248 } 249 250 pr_cont("}"); 251 } 252 pr_cont(" total %u\n", nvpes); 253 254 /* Indicate present CPUs (CPU being synonymous with VPE) */ 255 for (v = 0; v < min_t(unsigned, nvpes, NR_CPUS); v++) { 256 set_cpu_possible(v, true); 257 set_cpu_present(v, true); 258 __cpu_number_map[v] = v; 259 __cpu_logical_map[v] = v; 260 } 261 262 /* Set a coherent default CCA (CWB) */ 263 change_c0_config(CONF_CM_CMASK, 0x5); 264 265 /* Initialise core 0 */ 266 mips_cps_core_init(); 267 268 /* Make core 0 coherent with everything */ 269 write_gcr_cl_coherence(0xff); 270 271 if (allocate_cps_vecs()) 272 pr_err("Failed to allocate CPS vectors\n"); 273 274 if (core_entry_reg && mips_cm_revision() >= CM_REV_CM3) 275 write_gcr_bev_base(core_entry_reg); 276 277 #ifdef CONFIG_MIPS_MT_FPAFF 278 /* If we have an FPU, enroll ourselves in the FPU-full mask */ 279 if (cpu_has_fpu) 280 cpumask_set_cpu(0, &mt_fpu_cpumask); 281 #endif /* CONFIG_MIPS_MT_FPAFF */ 282 } 283 284 static void __init cps_prepare_cpus(unsigned int max_cpus) 285 { 286 unsigned int nclusters, ncores, core_vpes, c, cl, cca; 287 bool cca_unsuitable, cores_limited; 288 struct cluster_boot_config *cluster_bootcfg; 289 struct core_boot_config *core_bootcfg; 290 291 mips_mt_set_cpuoptions(); 292 293 if (!core_entry_reg) { 294 pr_err("core_entry address unsuitable, disabling smp-cps\n"); 295 goto err_out; 296 } 297 298 /* Detect whether the CCA is unsuited to multi-core SMP */ 299 cca = read_c0_config() & CONF_CM_CMASK; 300 switch (cca) { 301 case 0x4: /* CWBE */ 302 case 0x5: /* CWB */ 303 /* The CCA is coherent, multi-core is fine */ 304 cca_unsuitable = false; 305 break; 306 307 default: 308 /* CCA is not coherent, multi-core is not usable */ 309 cca_unsuitable = true; 310 } 311 312 /* Warn the user if the CCA prevents multi-core */ 313 cores_limited = false; 314 if (cca_unsuitable || cpu_has_dc_aliases) { 315 for_each_present_cpu(c) { 316 if (cpus_are_siblings(smp_processor_id(), c)) 317 continue; 318 319 set_cpu_present(c, false); 320 cores_limited = true; 321 } 322 } 323 if (cores_limited) 324 pr_warn("Using only one core due to %s%s%s\n", 325 cca_unsuitable ? "unsuitable CCA" : "", 326 (cca_unsuitable && cpu_has_dc_aliases) ? " & " : "", 327 cpu_has_dc_aliases ? "dcache aliasing" : ""); 328 329 setup_cps_vecs(); 330 331 /* Allocate cluster boot configuration structs */ 332 nclusters = mips_cps_numclusters(); 333 mips_cps_cluster_bootcfg = kcalloc(nclusters, 334 sizeof(*mips_cps_cluster_bootcfg), 335 GFP_KERNEL); 336 if (!mips_cps_cluster_bootcfg) 337 goto err_out; 338 339 if (nclusters > 1) 340 mips_cm_update_property(); 341 342 for (cl = 0; cl < nclusters; cl++) { 343 /* Allocate core boot configuration structs */ 344 ncores = mips_cps_numcores(cl); 345 core_bootcfg = kcalloc(ncores, sizeof(*core_bootcfg), 346 GFP_KERNEL); 347 if (!core_bootcfg) 348 goto err_out; 349 mips_cps_cluster_bootcfg[cl].core_config = core_bootcfg; 350 351 mips_cps_cluster_bootcfg[cl].core_power = 352 kcalloc(BITS_TO_LONGS(ncores), sizeof(unsigned long), 353 GFP_KERNEL); 354 if (!mips_cps_cluster_bootcfg[cl].core_power) 355 goto err_out; 356 357 /* Allocate VPE boot configuration structs */ 358 for (c = 0; c < ncores; c++) { 359 core_vpes = core_vpe_count(cl, c); 360 core_bootcfg[c].vpe_config = kcalloc(core_vpes, 361 sizeof(*core_bootcfg[c].vpe_config), 362 GFP_KERNEL); 363 if (!core_bootcfg[c].vpe_config) 364 goto err_out; 365 } 366 } 367 368 /* Mark this CPU as powered up & booted */ 369 cl = cpu_cluster(¤t_cpu_data); 370 c = cpu_core(¤t_cpu_data); 371 cluster_bootcfg = &mips_cps_cluster_bootcfg[cl]; 372 cpu_smt_set_num_threads(core_vpes, core_vpes); 373 core_bootcfg = &cluster_bootcfg->core_config[c]; 374 bitmap_set(cluster_bootcfg->core_power, cpu_core(¤t_cpu_data), 1); 375 atomic_set(&core_bootcfg->vpe_mask, 1 << cpu_vpe_id(¤t_cpu_data)); 376 377 return; 378 err_out: 379 /* Clean up allocations */ 380 if (mips_cps_cluster_bootcfg) { 381 for (cl = 0; cl < nclusters; cl++) { 382 cluster_bootcfg = &mips_cps_cluster_bootcfg[cl]; 383 ncores = mips_cps_numcores(cl); 384 for (c = 0; c < ncores; c++) { 385 core_bootcfg = &cluster_bootcfg->core_config[c]; 386 kfree(core_bootcfg->vpe_config); 387 } 388 kfree(mips_cps_cluster_bootcfg[c].core_config); 389 } 390 kfree(mips_cps_cluster_bootcfg); 391 mips_cps_cluster_bootcfg = NULL; 392 } 393 394 /* Effectively disable SMP by declaring CPUs not present */ 395 for_each_possible_cpu(c) { 396 if (c == 0) 397 continue; 398 set_cpu_present(c, false); 399 } 400 } 401 402 static void init_cluster_l2(void) 403 { 404 u32 l2_cfg, l2sm_cop, result; 405 406 while (!mips_cm_is_l2_hci_broken) { 407 l2_cfg = read_gcr_redir_l2_ram_config(); 408 409 /* If HCI is not supported, use the state machine below */ 410 if (!(l2_cfg & CM_GCR_L2_RAM_CONFIG_PRESENT)) 411 break; 412 if (!(l2_cfg & CM_GCR_L2_RAM_CONFIG_HCI_SUPPORTED)) 413 break; 414 415 /* If the HCI_DONE bit is set, we're finished */ 416 if (l2_cfg & CM_GCR_L2_RAM_CONFIG_HCI_DONE) 417 return; 418 } 419 420 l2sm_cop = read_gcr_redir_l2sm_cop(); 421 if (WARN(!(l2sm_cop & CM_GCR_L2SM_COP_PRESENT), 422 "L2 init not supported on this system yet")) 423 return; 424 425 /* Clear L2 tag registers */ 426 write_gcr_redir_l2_tag_state(0); 427 write_gcr_redir_l2_ecc(0); 428 429 /* Ensure the L2 tag writes complete before the state machine starts */ 430 mb(); 431 432 /* Wait for the L2 state machine to be idle */ 433 do { 434 l2sm_cop = read_gcr_redir_l2sm_cop(); 435 } while (l2sm_cop & CM_GCR_L2SM_COP_RUNNING); 436 437 /* Start a store tag operation */ 438 l2sm_cop = CM_GCR_L2SM_COP_TYPE_IDX_STORETAG; 439 l2sm_cop <<= __ffs(CM_GCR_L2SM_COP_TYPE); 440 l2sm_cop |= CM_GCR_L2SM_COP_CMD_START; 441 write_gcr_redir_l2sm_cop(l2sm_cop); 442 443 /* Ensure the state machine starts before we poll for completion */ 444 mb(); 445 446 /* Wait for the operation to be complete */ 447 do { 448 l2sm_cop = read_gcr_redir_l2sm_cop(); 449 result = l2sm_cop & CM_GCR_L2SM_COP_RESULT; 450 result >>= __ffs(CM_GCR_L2SM_COP_RESULT); 451 } while (!result); 452 453 WARN(result != CM_GCR_L2SM_COP_RESULT_DONE_OK, 454 "L2 state machine failed cache init with error %u\n", result); 455 } 456 457 static void boot_core(unsigned int cluster, unsigned int core, 458 unsigned int vpe_id) 459 { 460 struct cluster_boot_config *cluster_cfg; 461 u32 access, stat, seq_state; 462 unsigned int timeout, ncores; 463 464 cluster_cfg = &mips_cps_cluster_bootcfg[cluster]; 465 ncores = mips_cps_numcores(cluster); 466 467 if ((cluster != cpu_cluster(¤t_cpu_data)) && 468 bitmap_empty(cluster_cfg->core_power, ncores)) { 469 power_up_other_cluster(cluster); 470 471 mips_cm_lock_other(cluster, core, 0, 472 CM_GCR_Cx_OTHER_BLOCK_GLOBAL); 473 474 /* Ensure cluster GCRs are where we expect */ 475 write_gcr_redir_base(read_gcr_base()); 476 write_gcr_redir_cpc_base(read_gcr_cpc_base()); 477 write_gcr_redir_gic_base(read_gcr_gic_base()); 478 479 init_cluster_l2(); 480 481 /* Mirror L2 configuration */ 482 write_gcr_redir_l2_only_sync_base(read_gcr_l2_only_sync_base()); 483 write_gcr_redir_l2_pft_control(read_gcr_l2_pft_control()); 484 write_gcr_redir_l2_pft_control_b(read_gcr_l2_pft_control_b()); 485 486 /* Mirror ECC/parity setup */ 487 write_gcr_redir_err_control(read_gcr_err_control()); 488 489 /* Set BEV base */ 490 write_gcr_redir_bev_base(core_entry_reg); 491 492 mips_cm_unlock_other(); 493 } 494 495 if (cluster != cpu_cluster(¤t_cpu_data)) { 496 mips_cm_lock_other(cluster, core, 0, 497 CM_GCR_Cx_OTHER_BLOCK_GLOBAL); 498 499 /* Ensure the core can access the GCRs */ 500 access = read_gcr_redir_access(); 501 access |= BIT(core); 502 write_gcr_redir_access(access); 503 504 mips_cm_unlock_other(); 505 } else { 506 /* Ensure the core can access the GCRs */ 507 access = read_gcr_access(); 508 access |= BIT(core); 509 write_gcr_access(access); 510 } 511 512 /* Select the appropriate core */ 513 mips_cm_lock_other(cluster, core, 0, CM_GCR_Cx_OTHER_BLOCK_LOCAL); 514 515 /* Set its reset vector */ 516 if (mips_cm_is64) 517 write_gcr_co_reset64_base(core_entry_reg); 518 else 519 write_gcr_co_reset_base(core_entry_reg); 520 521 /* Ensure its coherency is disabled */ 522 write_gcr_co_coherence(0); 523 524 /* Start it with the legacy memory map and exception base */ 525 write_gcr_co_reset_ext_base(CM_GCR_Cx_RESET_EXT_BASE_UEB); 526 527 /* Ensure the core can access the GCRs */ 528 if (mips_cm_revision() < CM_REV_CM3) 529 set_gcr_access(1 << core); 530 else 531 set_gcr_access_cm3(1 << core); 532 533 if (mips_cpc_present()) { 534 /* Reset the core */ 535 mips_cpc_lock_other(core); 536 537 if (mips_cm_revision() >= CM_REV_CM3) { 538 /* Run only the requested VP following the reset */ 539 write_cpc_co_vp_stop(0xf); 540 write_cpc_co_vp_run(1 << vpe_id); 541 542 /* 543 * Ensure that the VP_RUN register is written before the 544 * core leaves reset. 545 */ 546 wmb(); 547 } 548 549 write_cpc_co_cmd(CPC_Cx_CMD_RESET); 550 551 timeout = 100; 552 while (true) { 553 stat = read_cpc_co_stat_conf(); 554 seq_state = stat & CPC_Cx_STAT_CONF_SEQSTATE; 555 seq_state >>= __ffs(CPC_Cx_STAT_CONF_SEQSTATE); 556 557 /* U6 == coherent execution, ie. the core is up */ 558 if (seq_state == CPC_Cx_STAT_CONF_SEQSTATE_U6) 559 break; 560 561 /* Delay a little while before we start warning */ 562 if (timeout) { 563 timeout--; 564 mdelay(10); 565 continue; 566 } 567 568 pr_warn("Waiting for core %u to start... STAT_CONF=0x%x\n", 569 core, stat); 570 mdelay(1000); 571 } 572 573 mips_cpc_unlock_other(); 574 } else { 575 /* Take the core out of reset */ 576 write_gcr_co_reset_release(0); 577 } 578 579 mips_cm_unlock_other(); 580 581 /* The core is now powered up */ 582 bitmap_set(cluster_cfg->core_power, core, 1); 583 584 /* 585 * Restore CM_PWRUP=0 so that the CM can power down if all the cores in 586 * the cluster do (eg. if they're all removed via hotplug. 587 */ 588 if (mips_cm_revision() >= CM_REV_CM3_5) { 589 mips_cm_lock_other(cluster, 0, 0, CM_GCR_Cx_OTHER_BLOCK_GLOBAL); 590 write_cpc_redir_pwrup_ctl(0); 591 mips_cm_unlock_other(); 592 } 593 } 594 595 static void remote_vpe_boot(void *dummy) 596 { 597 unsigned int cluster = cpu_cluster(¤t_cpu_data); 598 unsigned core = cpu_core(¤t_cpu_data); 599 struct cluster_boot_config *cluster_cfg = 600 &mips_cps_cluster_bootcfg[cluster]; 601 struct core_boot_config *core_cfg = &cluster_cfg->core_config[core]; 602 603 mips_cps_boot_vpes(core_cfg, cpu_vpe_id(¤t_cpu_data)); 604 } 605 606 static int cps_boot_secondary(int cpu, struct task_struct *idle) 607 { 608 unsigned int cluster = cpu_cluster(&cpu_data[cpu]); 609 unsigned core = cpu_core(&cpu_data[cpu]); 610 unsigned vpe_id = cpu_vpe_id(&cpu_data[cpu]); 611 struct cluster_boot_config *cluster_cfg = 612 &mips_cps_cluster_bootcfg[cluster]; 613 struct core_boot_config *core_cfg = &cluster_cfg->core_config[core]; 614 struct vpe_boot_config *vpe_cfg = &core_cfg->vpe_config[vpe_id]; 615 unsigned int remote; 616 int err; 617 618 vpe_cfg->pc = (unsigned long)&smp_bootstrap; 619 vpe_cfg->sp = __KSTK_TOS(idle); 620 vpe_cfg->gp = (unsigned long)task_thread_info(idle); 621 622 atomic_or(1 << cpu_vpe_id(&cpu_data[cpu]), &core_cfg->vpe_mask); 623 624 preempt_disable(); 625 626 if (!test_bit(core, cluster_cfg->core_power)) { 627 /* Boot a VPE on a powered down core */ 628 boot_core(cluster, core, vpe_id); 629 goto out; 630 } 631 632 if (cpu_has_vp) { 633 mips_cm_lock_other(cluster, core, vpe_id, 634 CM_GCR_Cx_OTHER_BLOCK_LOCAL); 635 if (mips_cm_is64) 636 write_gcr_co_reset64_base(core_entry_reg); 637 else 638 write_gcr_co_reset_base(core_entry_reg); 639 mips_cm_unlock_other(); 640 } 641 642 if (!cpus_are_siblings(cpu, smp_processor_id())) { 643 /* Boot a VPE on another powered up core */ 644 for (remote = 0; remote < NR_CPUS; remote++) { 645 if (!cpus_are_siblings(cpu, remote)) 646 continue; 647 if (cpu_online(remote)) 648 break; 649 } 650 if (remote >= NR_CPUS) { 651 pr_crit("No online CPU in core %u to start CPU%d\n", 652 core, cpu); 653 goto out; 654 } 655 656 err = smp_call_function_single(remote, remote_vpe_boot, 657 NULL, 1); 658 if (err) 659 panic("Failed to call remote CPU\n"); 660 goto out; 661 } 662 663 BUG_ON(!cpu_has_mipsmt && !cpu_has_vp); 664 665 /* Boot a VPE on this core */ 666 mips_cps_boot_vpes(core_cfg, vpe_id); 667 out: 668 preempt_enable(); 669 return 0; 670 } 671 672 static void cps_init_secondary(void) 673 { 674 int core = cpu_core(¤t_cpu_data); 675 676 /* Disable MT - we only want to run 1 TC per VPE */ 677 if (cpu_has_mipsmt) 678 dmt(); 679 680 if (mips_cm_revision() >= CM_REV_CM3) { 681 unsigned int ident = read_gic_vl_ident(); 682 683 /* 684 * Ensure that our calculation of the VP ID matches up with 685 * what the GIC reports, otherwise we'll have configured 686 * interrupts incorrectly. 687 */ 688 BUG_ON(ident != mips_cm_vp_id(smp_processor_id())); 689 } 690 691 if (core > 0 && !read_gcr_cl_coherence()) 692 pr_warn("Core %u is not in coherent domain\n", core); 693 694 if (cpu_has_veic) 695 clear_c0_status(ST0_IM); 696 else 697 change_c0_status(ST0_IM, STATUSF_IP2 | STATUSF_IP3 | 698 STATUSF_IP4 | STATUSF_IP5 | 699 STATUSF_IP6 | STATUSF_IP7); 700 } 701 702 static void cps_smp_finish(void) 703 { 704 write_c0_compare(read_c0_count() + (8 * mips_hpt_frequency / HZ)); 705 706 #ifdef CONFIG_MIPS_MT_FPAFF 707 /* If we have an FPU, enroll ourselves in the FPU-full mask */ 708 if (cpu_has_fpu) 709 cpumask_set_cpu(smp_processor_id(), &mt_fpu_cpumask); 710 #endif /* CONFIG_MIPS_MT_FPAFF */ 711 712 local_irq_enable(); 713 } 714 715 #if defined(CONFIG_HOTPLUG_CPU) || defined(CONFIG_KEXEC_CORE) 716 717 enum cpu_death { 718 CPU_DEATH_HALT, 719 CPU_DEATH_POWER, 720 }; 721 722 static void cps_shutdown_this_cpu(enum cpu_death death) 723 { 724 unsigned int cpu, core, vpe_id; 725 726 cpu = smp_processor_id(); 727 core = cpu_core(&cpu_data[cpu]); 728 729 if (death == CPU_DEATH_HALT) { 730 vpe_id = cpu_vpe_id(&cpu_data[cpu]); 731 732 pr_debug("Halting core %d VP%d\n", core, vpe_id); 733 if (cpu_has_mipsmt) { 734 /* Halt this TC */ 735 write_c0_tchalt(TCHALT_H); 736 instruction_hazard(); 737 } else if (cpu_has_vp) { 738 write_cpc_cl_vp_stop(1 << vpe_id); 739 740 /* Ensure that the VP_STOP register is written */ 741 wmb(); 742 } 743 } else { 744 if (IS_ENABLED(CONFIG_HOTPLUG_CPU)) { 745 pr_debug("Gating power to core %d\n", core); 746 /* Power down the core */ 747 cps_pm_enter_state(CPS_PM_POWER_GATED); 748 } 749 } 750 } 751 752 #ifdef CONFIG_KEXEC_CORE 753 754 static void cps_kexec_nonboot_cpu(void) 755 { 756 if (cpu_has_mipsmt || cpu_has_vp) 757 cps_shutdown_this_cpu(CPU_DEATH_HALT); 758 else 759 cps_shutdown_this_cpu(CPU_DEATH_POWER); 760 } 761 762 #endif /* CONFIG_KEXEC_CORE */ 763 764 #endif /* CONFIG_HOTPLUG_CPU || CONFIG_KEXEC_CORE */ 765 766 #ifdef CONFIG_HOTPLUG_CPU 767 768 static int cps_cpu_disable(void) 769 { 770 unsigned cpu = smp_processor_id(); 771 struct cluster_boot_config *cluster_cfg; 772 struct core_boot_config *core_cfg; 773 774 if (!cps_pm_support_state(CPS_PM_POWER_GATED)) 775 return -EINVAL; 776 777 cluster_cfg = &mips_cps_cluster_bootcfg[cpu_cluster(¤t_cpu_data)]; 778 core_cfg = &cluster_cfg->core_config[cpu_core(¤t_cpu_data)]; 779 atomic_sub(1 << cpu_vpe_id(¤t_cpu_data), &core_cfg->vpe_mask); 780 smp_mb__after_atomic(); 781 set_cpu_online(cpu, false); 782 calculate_cpu_foreign_map(); 783 irq_migrate_all_off_this_cpu(); 784 785 return 0; 786 } 787 788 static unsigned cpu_death_sibling; 789 static enum cpu_death cpu_death; 790 791 void play_dead(void) 792 { 793 unsigned int cpu; 794 795 local_irq_disable(); 796 idle_task_exit(); 797 cpu = smp_processor_id(); 798 cpu_death = CPU_DEATH_POWER; 799 800 pr_debug("CPU%d going offline\n", cpu); 801 802 if (cpu_has_mipsmt || cpu_has_vp) { 803 /* Look for another online VPE within the core */ 804 for_each_online_cpu(cpu_death_sibling) { 805 if (!cpus_are_siblings(cpu, cpu_death_sibling)) 806 continue; 807 808 /* 809 * There is an online VPE within the core. Just halt 810 * this TC and leave the core alone. 811 */ 812 cpu_death = CPU_DEATH_HALT; 813 break; 814 } 815 } 816 817 cpuhp_ap_report_dead(); 818 819 cps_shutdown_this_cpu(cpu_death); 820 821 /* This should never be reached */ 822 panic("Failed to offline CPU %u", cpu); 823 } 824 825 static void wait_for_sibling_halt(void *ptr_cpu) 826 { 827 unsigned cpu = (unsigned long)ptr_cpu; 828 unsigned vpe_id = cpu_vpe_id(&cpu_data[cpu]); 829 unsigned halted; 830 unsigned long flags; 831 832 do { 833 local_irq_save(flags); 834 settc(vpe_id); 835 halted = read_tc_c0_tchalt(); 836 local_irq_restore(flags); 837 } while (!(halted & TCHALT_H)); 838 } 839 840 static void cps_cpu_die(unsigned int cpu) { } 841 842 static void cps_cleanup_dead_cpu(unsigned cpu) 843 { 844 unsigned int cluster = cpu_cluster(&cpu_data[cpu]); 845 unsigned core = cpu_core(&cpu_data[cpu]); 846 unsigned int vpe_id = cpu_vpe_id(&cpu_data[cpu]); 847 ktime_t fail_time; 848 unsigned stat; 849 int err; 850 struct cluster_boot_config *cluster_cfg; 851 852 cluster_cfg = &mips_cps_cluster_bootcfg[cluster]; 853 854 /* 855 * Now wait for the CPU to actually offline. Without doing this that 856 * offlining may race with one or more of: 857 * 858 * - Onlining the CPU again. 859 * - Powering down the core if another VPE within it is offlined. 860 * - A sibling VPE entering a non-coherent state. 861 * 862 * In the non-MT halt case (ie. infinite loop) the CPU is doing nothing 863 * with which we could race, so do nothing. 864 */ 865 if (cpu_death == CPU_DEATH_POWER) { 866 /* 867 * Wait for the core to enter a powered down or clock gated 868 * state, the latter happening when a JTAG probe is connected 869 * in which case the CPC will refuse to power down the core. 870 */ 871 fail_time = ktime_add_ms(ktime_get(), 2000); 872 do { 873 mips_cm_lock_other(0, core, 0, CM_GCR_Cx_OTHER_BLOCK_LOCAL); 874 mips_cpc_lock_other(core); 875 stat = read_cpc_co_stat_conf(); 876 stat &= CPC_Cx_STAT_CONF_SEQSTATE; 877 stat >>= __ffs(CPC_Cx_STAT_CONF_SEQSTATE); 878 mips_cpc_unlock_other(); 879 mips_cm_unlock_other(); 880 881 if (stat == CPC_Cx_STAT_CONF_SEQSTATE_D0 || 882 stat == CPC_Cx_STAT_CONF_SEQSTATE_D2 || 883 stat == CPC_Cx_STAT_CONF_SEQSTATE_U2) 884 break; 885 886 /* 887 * The core ought to have powered down, but didn't & 888 * now we don't really know what state it's in. It's 889 * likely that its _pwr_up pin has been wired to logic 890 * 1 & it powered back up as soon as we powered it 891 * down... 892 * 893 * The best we can do is warn the user & continue in 894 * the hope that the core is doing nothing harmful & 895 * might behave properly if we online it later. 896 */ 897 if (WARN(ktime_after(ktime_get(), fail_time), 898 "CPU%u hasn't powered down, seq. state %u\n", 899 cpu, stat)) 900 break; 901 } while (1); 902 903 /* Indicate the core is powered off */ 904 bitmap_clear(cluster_cfg->core_power, core, 1); 905 } else if (cpu_has_mipsmt) { 906 /* 907 * Have a CPU with access to the offlined CPUs registers wait 908 * for its TC to halt. 909 */ 910 err = smp_call_function_single(cpu_death_sibling, 911 wait_for_sibling_halt, 912 (void *)(unsigned long)cpu, 1); 913 if (err) 914 panic("Failed to call remote sibling CPU\n"); 915 } else if (cpu_has_vp) { 916 do { 917 mips_cm_lock_other(0, core, vpe_id, CM_GCR_Cx_OTHER_BLOCK_LOCAL); 918 stat = read_cpc_co_vp_running(); 919 mips_cm_unlock_other(); 920 } while (stat & (1 << vpe_id)); 921 } 922 } 923 924 #endif /* CONFIG_HOTPLUG_CPU */ 925 926 static const struct plat_smp_ops cps_smp_ops = { 927 .smp_setup = cps_smp_setup, 928 .prepare_cpus = cps_prepare_cpus, 929 .boot_secondary = cps_boot_secondary, 930 .init_secondary = cps_init_secondary, 931 .smp_finish = cps_smp_finish, 932 .send_ipi_single = mips_smp_send_ipi_single, 933 .send_ipi_mask = mips_smp_send_ipi_mask, 934 #ifdef CONFIG_HOTPLUG_CPU 935 .cpu_disable = cps_cpu_disable, 936 .cpu_die = cps_cpu_die, 937 .cleanup_dead_cpu = cps_cleanup_dead_cpu, 938 #endif 939 #ifdef CONFIG_KEXEC_CORE 940 .kexec_nonboot_cpu = cps_kexec_nonboot_cpu, 941 #endif 942 }; 943 944 bool mips_cps_smp_in_use(void) 945 { 946 extern const struct plat_smp_ops *mp_ops; 947 return mp_ops == &cps_smp_ops; 948 } 949 950 int register_cps_smp_ops(void) 951 { 952 if (!mips_cm_present()) { 953 pr_warn("MIPS CPS SMP unable to proceed without a CM\n"); 954 return -ENODEV; 955 } 956 957 /* check we have a GIC - we need one for IPIs */ 958 if (!(read_gcr_gic_status() & CM_GCR_GIC_STATUS_EX)) { 959 pr_warn("MIPS CPS SMP unable to proceed without a GIC\n"); 960 return -ENODEV; 961 } 962 963 register_smp_ops(&cps_smp_ops); 964 return 0; 965 } 966