1 /* 2 * This file is subject to the terms and conditions of the GNU General Public 3 * License. See the file "COPYING" in the main directory of this archive 4 * for more details. 5 * 6 * Copyright (C) 2011 by Kevin Cernekee (cernekee@gmail.com) 7 * 8 * SMP support for BMIPS 9 */ 10 11 #include <linux/init.h> 12 #include <linux/sched.h> 13 #include <linux/sched/hotplug.h> 14 #include <linux/sched/task_stack.h> 15 #include <linux/mm.h> 16 #include <linux/delay.h> 17 #include <linux/smp.h> 18 #include <linux/interrupt.h> 19 #include <linux/spinlock.h> 20 #include <linux/cpu.h> 21 #include <linux/cpumask.h> 22 #include <linux/reboot.h> 23 #include <linux/io.h> 24 #include <linux/compiler.h> 25 #include <linux/linkage.h> 26 #include <linux/bug.h> 27 #include <linux/kernel.h> 28 #include <linux/kexec.h> 29 #include <linux/irq.h> 30 31 #include <asm/time.h> 32 #include <asm/processor.h> 33 #include <asm/bootinfo.h> 34 #include <asm/cacheflush.h> 35 #include <asm/tlbflush.h> 36 #include <asm/mipsregs.h> 37 #include <asm/bmips.h> 38 #include <asm/traps.h> 39 #include <asm/barrier.h> 40 #include <asm/cpu-features.h> 41 42 static int __maybe_unused max_cpus = 1; 43 44 /* these may be configured by the platform code */ 45 int bmips_smp_enabled = 1; 46 int bmips_cpu_offset; 47 cpumask_t bmips_booted_mask; 48 unsigned long bmips_tp1_irqs = IE_IRQ1; 49 50 #define RESET_FROM_KSEG0 0x80080800 51 #define RESET_FROM_KSEG1 0xa0080800 52 53 static void bmips_set_reset_vec(int cpu, u32 val); 54 55 #ifdef CONFIG_SMP 56 57 #include <asm/smp.h> 58 59 /* initial $sp, $gp - used by arch/mips/kernel/bmips_vec.S */ 60 unsigned long bmips_smp_boot_sp; 61 unsigned long bmips_smp_boot_gp; 62 63 static void bmips43xx_send_ipi_single(int cpu, unsigned int action); 64 static void bmips5000_send_ipi_single(int cpu, unsigned int action); 65 static irqreturn_t bmips43xx_ipi_interrupt(int irq, void *dev_id); 66 static irqreturn_t bmips5000_ipi_interrupt(int irq, void *dev_id); 67 68 /* SW interrupts 0,1 are used for interprocessor signaling */ 69 #define IPI0_IRQ (MIPS_CPU_IRQ_BASE + 0) 70 #define IPI1_IRQ (MIPS_CPU_IRQ_BASE + 1) 71 72 #define CPUNUM(cpu, shift) (((cpu) + bmips_cpu_offset) << (shift)) 73 #define ACTION_CLR_IPI(cpu, ipi) (0x2000 | CPUNUM(cpu, 9) | ((ipi) << 8)) 74 #define ACTION_SET_IPI(cpu, ipi) (0x3000 | CPUNUM(cpu, 9) | ((ipi) << 8)) 75 #define ACTION_BOOT_THREAD(cpu) (0x08 | CPUNUM(cpu, 0)) 76 77 static void __init bmips_smp_setup(void) 78 { 79 int i, cpu = 1, boot_cpu = 0; 80 int cpu_hw_intr; 81 82 switch (current_cpu_type()) { 83 case CPU_BMIPS4350: 84 case CPU_BMIPS4380: 85 /* arbitration priority */ 86 clear_c0_brcm_cmt_ctrl(0x30); 87 88 /* NBK and weak order flags */ 89 set_c0_brcm_config_0(0x30000); 90 91 /* Find out if we are running on TP0 or TP1 */ 92 boot_cpu = !!(read_c0_brcm_cmt_local() & (1 << 31)); 93 94 /* 95 * MIPS interrupts 0,1 (SW INT 0,1) cross over to the other 96 * thread 97 * MIPS interrupt 2 (HW INT 0) is the CPU0 L1 controller output 98 * MIPS interrupt 3 (HW INT 1) is the CPU1 L1 controller output 99 */ 100 if (boot_cpu == 0) 101 cpu_hw_intr = 0x02; 102 else 103 cpu_hw_intr = 0x1d; 104 105 change_c0_brcm_cmt_intr(0xf8018000, 106 (cpu_hw_intr << 27) | (0x03 << 15)); 107 108 /* single core, 2 threads (2 pipelines) */ 109 max_cpus = 2; 110 111 break; 112 case CPU_BMIPS5000: 113 /* enable raceless SW interrupts */ 114 set_c0_brcm_config(0x03 << 22); 115 116 /* route HW interrupt 0 to CPU0, HW interrupt 1 to CPU1 */ 117 change_c0_brcm_mode(0x1f << 27, 0x02 << 27); 118 119 /* N cores, 2 threads per core */ 120 max_cpus = (((read_c0_brcm_config() >> 6) & 0x03) + 1) << 1; 121 122 /* clear any pending SW interrupts */ 123 for (i = 0; i < max_cpus; i++) { 124 write_c0_brcm_action(ACTION_CLR_IPI(i, 0)); 125 write_c0_brcm_action(ACTION_CLR_IPI(i, 1)); 126 } 127 128 break; 129 default: 130 max_cpus = 1; 131 } 132 133 if (!bmips_smp_enabled) 134 max_cpus = 1; 135 136 /* this can be overridden by the BSP */ 137 if (!board_ebase_setup) 138 board_ebase_setup = &bmips_ebase_setup; 139 140 if (max_cpus > 1) { 141 __cpu_number_map[boot_cpu] = 0; 142 __cpu_logical_map[0] = boot_cpu; 143 144 for (i = 0; i < max_cpus; i++) { 145 if (i != boot_cpu) { 146 __cpu_number_map[i] = cpu; 147 __cpu_logical_map[cpu] = i; 148 cpu++; 149 } 150 set_cpu_possible(i, 1); 151 set_cpu_present(i, 1); 152 } 153 } else { 154 __cpu_number_map[0] = boot_cpu; 155 __cpu_logical_map[0] = 0; 156 set_cpu_possible(0, 1); 157 set_cpu_present(0, 1); 158 } 159 } 160 161 /* 162 * IPI IRQ setup - runs on CPU0 163 */ 164 static void bmips_prepare_cpus(unsigned int max_cpus) 165 { 166 irqreturn_t (*bmips_ipi_interrupt)(int irq, void *dev_id); 167 168 switch (current_cpu_type()) { 169 case CPU_BMIPS4350: 170 case CPU_BMIPS4380: 171 bmips_ipi_interrupt = bmips43xx_ipi_interrupt; 172 break; 173 case CPU_BMIPS5000: 174 bmips_ipi_interrupt = bmips5000_ipi_interrupt; 175 break; 176 default: 177 return; 178 } 179 180 if (request_irq(IPI0_IRQ, bmips_ipi_interrupt, 181 IRQF_PERCPU | IRQF_NO_SUSPEND, "smp_ipi0", NULL)) 182 panic("Can't request IPI0 interrupt"); 183 if (request_irq(IPI1_IRQ, bmips_ipi_interrupt, 184 IRQF_PERCPU | IRQF_NO_SUSPEND, "smp_ipi1", NULL)) 185 panic("Can't request IPI1 interrupt"); 186 } 187 188 /* 189 * Tell the hardware to boot CPUx - runs on CPU0 190 */ 191 static int bmips_boot_secondary(int cpu, struct task_struct *idle) 192 { 193 bmips_smp_boot_sp = __KSTK_TOS(idle); 194 bmips_smp_boot_gp = (unsigned long)task_thread_info(idle); 195 mb(); 196 197 /* 198 * Initial boot sequence for secondary CPU: 199 * bmips_reset_nmi_vec @ a000_0000 -> 200 * bmips_smp_entry -> 201 * plat_wired_tlb_setup (cached function call; optional) -> 202 * start_secondary (cached jump) 203 * 204 * Warm restart sequence: 205 * play_dead WAIT loop -> 206 * bmips_smp_int_vec @ BMIPS_WARM_RESTART_VEC -> 207 * eret to play_dead -> 208 * bmips_secondary_reentry -> 209 * start_secondary 210 */ 211 212 pr_info("SMP: Booting CPU%d...\n", cpu); 213 214 if (cpumask_test_cpu(cpu, &bmips_booted_mask)) { 215 /* kseg1 might not exist if this CPU enabled XKS01 */ 216 bmips_set_reset_vec(cpu, RESET_FROM_KSEG0); 217 218 switch (current_cpu_type()) { 219 case CPU_BMIPS4350: 220 case CPU_BMIPS4380: 221 bmips43xx_send_ipi_single(cpu, 0); 222 break; 223 case CPU_BMIPS5000: 224 bmips5000_send_ipi_single(cpu, 0); 225 break; 226 } 227 } else { 228 bmips_set_reset_vec(cpu, RESET_FROM_KSEG1); 229 230 switch (current_cpu_type()) { 231 case CPU_BMIPS4350: 232 case CPU_BMIPS4380: 233 /* Reset slave TP1 if booting from TP0 */ 234 if (cpu_logical_map(cpu) == 1) 235 set_c0_brcm_cmt_ctrl(0x01); 236 break; 237 case CPU_BMIPS5000: 238 write_c0_brcm_action(ACTION_BOOT_THREAD(cpu)); 239 break; 240 } 241 cpumask_set_cpu(cpu, &bmips_booted_mask); 242 } 243 244 return 0; 245 } 246 247 /* 248 * Early setup - runs on secondary CPU after cache probe 249 */ 250 static void bmips_init_secondary(void) 251 { 252 bmips_cpu_setup(); 253 254 switch (current_cpu_type()) { 255 case CPU_BMIPS4350: 256 case CPU_BMIPS4380: 257 clear_c0_cause(smp_processor_id() ? C_SW1 : C_SW0); 258 break; 259 case CPU_BMIPS5000: 260 write_c0_brcm_action(ACTION_CLR_IPI(smp_processor_id(), 0)); 261 cpu_set_core(¤t_cpu_data, (read_c0_brcm_config() >> 25) & 3); 262 break; 263 } 264 } 265 266 /* 267 * Late setup - runs on secondary CPU before entering the idle loop 268 */ 269 static void bmips_smp_finish(void) 270 { 271 pr_info("SMP: CPU%d is running\n", smp_processor_id()); 272 273 /* make sure there won't be a timer interrupt for a little while */ 274 write_c0_compare(read_c0_count() + mips_hpt_frequency / HZ); 275 276 irq_enable_hazard(); 277 set_c0_status(IE_SW0 | IE_SW1 | bmips_tp1_irqs | IE_IRQ5 | ST0_IE); 278 irq_enable_hazard(); 279 } 280 281 /* 282 * BMIPS5000 raceless IPIs 283 * 284 * Each CPU has two inbound SW IRQs which are independent of all other CPUs. 285 * IPI0 is used for SMP_RESCHEDULE_YOURSELF 286 * IPI1 is used for SMP_CALL_FUNCTION 287 */ 288 289 static void bmips5000_send_ipi_single(int cpu, unsigned int action) 290 { 291 write_c0_brcm_action(ACTION_SET_IPI(cpu, action == SMP_CALL_FUNCTION)); 292 } 293 294 static irqreturn_t bmips5000_ipi_interrupt(int irq, void *dev_id) 295 { 296 int action = irq - IPI0_IRQ; 297 298 write_c0_brcm_action(ACTION_CLR_IPI(smp_processor_id(), action)); 299 300 if (action == 0) 301 scheduler_ipi(); 302 else 303 generic_smp_call_function_interrupt(); 304 305 return IRQ_HANDLED; 306 } 307 308 static void bmips5000_send_ipi_mask(const struct cpumask *mask, 309 unsigned int action) 310 { 311 unsigned int i; 312 313 for_each_cpu(i, mask) 314 bmips5000_send_ipi_single(i, action); 315 } 316 317 /* 318 * BMIPS43xx racey IPIs 319 * 320 * We use one inbound SW IRQ for each CPU. 321 * 322 * A spinlock must be held in order to keep CPUx from accidentally clearing 323 * an incoming IPI when it writes CP0 CAUSE to raise an IPI on CPUy. The 324 * same spinlock is used to protect the action masks. 325 */ 326 327 static DEFINE_SPINLOCK(ipi_lock); 328 static DEFINE_PER_CPU(int, ipi_action_mask); 329 330 static void bmips43xx_send_ipi_single(int cpu, unsigned int action) 331 { 332 unsigned long flags; 333 334 spin_lock_irqsave(&ipi_lock, flags); 335 set_c0_cause(cpu ? C_SW1 : C_SW0); 336 per_cpu(ipi_action_mask, cpu) |= action; 337 irq_enable_hazard(); 338 spin_unlock_irqrestore(&ipi_lock, flags); 339 } 340 341 static irqreturn_t bmips43xx_ipi_interrupt(int irq, void *dev_id) 342 { 343 unsigned long flags; 344 int action, cpu = irq - IPI0_IRQ; 345 346 spin_lock_irqsave(&ipi_lock, flags); 347 action = __this_cpu_read(ipi_action_mask); 348 per_cpu(ipi_action_mask, cpu) = 0; 349 clear_c0_cause(cpu ? C_SW1 : C_SW0); 350 spin_unlock_irqrestore(&ipi_lock, flags); 351 352 if (action & SMP_RESCHEDULE_YOURSELF) 353 scheduler_ipi(); 354 if (action & SMP_CALL_FUNCTION) 355 generic_smp_call_function_interrupt(); 356 357 return IRQ_HANDLED; 358 } 359 360 static void bmips43xx_send_ipi_mask(const struct cpumask *mask, 361 unsigned int action) 362 { 363 unsigned int i; 364 365 for_each_cpu(i, mask) 366 bmips43xx_send_ipi_single(i, action); 367 } 368 369 #ifdef CONFIG_HOTPLUG_CPU 370 371 static int bmips_cpu_disable(void) 372 { 373 unsigned int cpu = smp_processor_id(); 374 375 pr_info("SMP: CPU%d is offline\n", cpu); 376 377 set_cpu_online(cpu, false); 378 calculate_cpu_foreign_map(); 379 irq_migrate_all_off_this_cpu(); 380 clear_c0_status(IE_IRQ5); 381 382 local_flush_tlb_all(); 383 local_flush_icache_range(0, ~0); 384 385 return 0; 386 } 387 388 static void bmips_cpu_die(unsigned int cpu) 389 { 390 } 391 392 void __ref play_dead(void) 393 { 394 idle_task_exit(); 395 cpuhp_ap_report_dead(); 396 397 /* flush data cache */ 398 _dma_cache_wback_inv(0, ~0); 399 400 /* 401 * Wakeup is on SW0 or SW1; disable everything else 402 * Use BEV !IV (BMIPS_WARM_RESTART_VEC) to avoid the regular Linux 403 * IRQ handlers; this clears ST0_IE and returns immediately. 404 */ 405 clear_c0_cause(CAUSEF_IV | C_SW0 | C_SW1); 406 change_c0_status( 407 IE_IRQ5 | bmips_tp1_irqs | IE_SW0 | IE_SW1 | ST0_IE | ST0_BEV, 408 IE_SW0 | IE_SW1 | ST0_IE | ST0_BEV); 409 irq_disable_hazard(); 410 411 /* 412 * wait for SW interrupt from bmips_boot_secondary(), then jump 413 * back to start_secondary() 414 */ 415 __asm__ __volatile__( 416 " wait\n" 417 " j bmips_secondary_reentry\n" 418 : : : "memory"); 419 420 BUG(); 421 } 422 423 #endif /* CONFIG_HOTPLUG_CPU */ 424 425 const struct plat_smp_ops bmips43xx_smp_ops = { 426 .smp_setup = bmips_smp_setup, 427 .prepare_cpus = bmips_prepare_cpus, 428 .boot_secondary = bmips_boot_secondary, 429 .smp_finish = bmips_smp_finish, 430 .init_secondary = bmips_init_secondary, 431 .send_ipi_single = bmips43xx_send_ipi_single, 432 .send_ipi_mask = bmips43xx_send_ipi_mask, 433 #ifdef CONFIG_HOTPLUG_CPU 434 .cpu_disable = bmips_cpu_disable, 435 .cpu_die = bmips_cpu_die, 436 #endif 437 #ifdef CONFIG_KEXEC_CORE 438 .kexec_nonboot_cpu = kexec_nonboot_cpu_jump, 439 #endif 440 }; 441 442 const struct plat_smp_ops bmips5000_smp_ops = { 443 .smp_setup = bmips_smp_setup, 444 .prepare_cpus = bmips_prepare_cpus, 445 .boot_secondary = bmips_boot_secondary, 446 .smp_finish = bmips_smp_finish, 447 .init_secondary = bmips_init_secondary, 448 .send_ipi_single = bmips5000_send_ipi_single, 449 .send_ipi_mask = bmips5000_send_ipi_mask, 450 #ifdef CONFIG_HOTPLUG_CPU 451 .cpu_disable = bmips_cpu_disable, 452 .cpu_die = bmips_cpu_die, 453 #endif 454 #ifdef CONFIG_KEXEC_CORE 455 .kexec_nonboot_cpu = kexec_nonboot_cpu_jump, 456 #endif 457 }; 458 459 #endif /* CONFIG_SMP */ 460 461 /*********************************************************************** 462 * BMIPS vector relocation 463 * This is primarily used for SMP boot, but it is applicable to some 464 * UP BMIPS systems as well. 465 ***********************************************************************/ 466 467 static void bmips_wr_vec(unsigned long dst, char *start, char *end) 468 { 469 memcpy((void *)dst, start, end - start); 470 dma_cache_wback(dst, end - start); 471 local_flush_icache_range(dst, dst + (end - start)); 472 instruction_hazard(); 473 } 474 475 static inline void bmips_nmi_handler_setup(void) 476 { 477 bmips_wr_vec(BMIPS_NMI_RESET_VEC, bmips_reset_nmi_vec, 478 bmips_reset_nmi_vec_end); 479 bmips_wr_vec(BMIPS_WARM_RESTART_VEC, bmips_smp_int_vec, 480 bmips_smp_int_vec_end); 481 } 482 483 struct reset_vec_info { 484 int cpu; 485 u32 val; 486 }; 487 488 static void bmips_set_reset_vec_remote(void *vinfo) 489 { 490 struct reset_vec_info *info = vinfo; 491 int shift = info->cpu & 0x01 ? 16 : 0; 492 u32 mask = ~(0xffff << shift), val = info->val >> 16; 493 494 preempt_disable(); 495 if (smp_processor_id() > 0) { 496 smp_call_function_single(0, &bmips_set_reset_vec_remote, 497 info, 1); 498 } else { 499 if (info->cpu & 0x02) { 500 /* BMIPS5200 "should" use mask/shift, but it's buggy */ 501 bmips_write_zscm_reg(0xa0, (val << 16) | val); 502 bmips_read_zscm_reg(0xa0); 503 } else { 504 write_c0_brcm_bootvec((read_c0_brcm_bootvec() & mask) | 505 (val << shift)); 506 } 507 } 508 preempt_enable(); 509 } 510 511 static void bmips_set_reset_vec(int cpu, u32 val) 512 { 513 struct reset_vec_info info; 514 515 if (current_cpu_type() == CPU_BMIPS5000) { 516 /* this needs to run from CPU0 (which is always online) */ 517 info.cpu = cpu; 518 info.val = val; 519 bmips_set_reset_vec_remote(&info); 520 } else { 521 void __iomem *cbr = BMIPS_GET_CBR(); 522 523 if (cpu == 0) 524 __raw_writel(val, cbr + BMIPS_RELO_VECTOR_CONTROL_0); 525 else { 526 if (current_cpu_type() != CPU_BMIPS4380) 527 return; 528 __raw_writel(val, cbr + BMIPS_RELO_VECTOR_CONTROL_1); 529 } 530 } 531 __sync(); 532 back_to_back_c0_hazard(); 533 } 534 535 void bmips_ebase_setup(void) 536 { 537 unsigned long new_ebase = ebase; 538 539 BUG_ON(ebase != CKSEG0); 540 541 switch (current_cpu_type()) { 542 case CPU_BMIPS4350: 543 /* 544 * BMIPS4350 cannot relocate the normal vectors, but it 545 * can relocate the BEV=1 vectors. So CPU1 starts up at 546 * the relocated BEV=1, IV=0 general exception vector @ 547 * 0xa000_0380. 548 * 549 * set_uncached_handler() is used here because: 550 * - CPU1 will run this from uncached space 551 * - None of the cacheflush functions are set up yet 552 */ 553 set_uncached_handler(BMIPS_WARM_RESTART_VEC - CKSEG0, 554 &bmips_smp_int_vec, 0x80); 555 __sync(); 556 return; 557 case CPU_BMIPS3300: 558 case CPU_BMIPS4380: 559 /* 560 * 0x8000_0000: reset/NMI (initially in kseg1) 561 * 0x8000_0400: normal vectors 562 */ 563 new_ebase = 0x80000400; 564 bmips_set_reset_vec(0, RESET_FROM_KSEG0); 565 break; 566 case CPU_BMIPS5000: 567 /* 568 * 0x8000_0000: reset/NMI (initially in kseg1) 569 * 0x8000_1000: normal vectors 570 */ 571 new_ebase = 0x80001000; 572 bmips_set_reset_vec(0, RESET_FROM_KSEG0); 573 write_c0_ebase(new_ebase); 574 break; 575 default: 576 return; 577 } 578 579 board_nmi_handler_setup = &bmips_nmi_handler_setup; 580 ebase = new_ebase; 581 } 582 583 asmlinkage void __weak plat_wired_tlb_setup(void) 584 { 585 /* 586 * Called when starting/restarting a secondary CPU. 587 * Kernel stacks and other important data might only be accessible 588 * once the wired entries are present. 589 */ 590 } 591 592 void bmips_cpu_setup(void) 593 { 594 void __iomem __maybe_unused *cbr = BMIPS_GET_CBR(); 595 u32 __maybe_unused cfg; 596 597 switch (current_cpu_type()) { 598 case CPU_BMIPS3300: 599 /* Set BIU to async mode */ 600 set_c0_brcm_bus_pll(BIT(22)); 601 __sync(); 602 603 /* put the BIU back in sync mode */ 604 clear_c0_brcm_bus_pll(BIT(22)); 605 606 /* clear BHTD to enable branch history table */ 607 clear_c0_brcm_reset(BIT(16)); 608 609 /* Flush and enable RAC */ 610 cfg = __raw_readl(cbr + BMIPS_RAC_CONFIG); 611 __raw_writel(cfg | 0x100, cbr + BMIPS_RAC_CONFIG); 612 __raw_readl(cbr + BMIPS_RAC_CONFIG); 613 614 cfg = __raw_readl(cbr + BMIPS_RAC_CONFIG); 615 __raw_writel(cfg | 0xf, cbr + BMIPS_RAC_CONFIG); 616 __raw_readl(cbr + BMIPS_RAC_CONFIG); 617 618 cfg = __raw_readl(cbr + BMIPS_RAC_ADDRESS_RANGE); 619 __raw_writel(cfg | 0x0fff0000, cbr + BMIPS_RAC_ADDRESS_RANGE); 620 __raw_readl(cbr + BMIPS_RAC_ADDRESS_RANGE); 621 break; 622 623 case CPU_BMIPS4380: 624 /* CBG workaround for early BMIPS4380 CPUs */ 625 switch (read_c0_prid()) { 626 case 0x2a040: 627 case 0x2a042: 628 case 0x2a044: 629 case 0x2a060: 630 cfg = __raw_readl(cbr + BMIPS_L2_CONFIG); 631 __raw_writel(cfg & ~0x07000000, cbr + BMIPS_L2_CONFIG); 632 __raw_readl(cbr + BMIPS_L2_CONFIG); 633 } 634 635 /* clear BHTD to enable branch history table */ 636 clear_c0_brcm_config_0(BIT(21)); 637 638 /* XI/ROTR enable */ 639 set_c0_brcm_config_0(BIT(23)); 640 set_c0_brcm_cmt_ctrl(BIT(15)); 641 break; 642 643 case CPU_BMIPS5000: 644 /* enable RDHWR, BRDHWR */ 645 set_c0_brcm_config(BIT(17) | BIT(21)); 646 647 /* Disable JTB */ 648 __asm__ __volatile__( 649 " .set noreorder\n" 650 " li $8, 0x5a455048\n" 651 " .word 0x4088b00f\n" /* mtc0 t0, $22, 15 */ 652 " .word 0x4008b008\n" /* mfc0 t0, $22, 8 */ 653 " li $9, 0x00008000\n" 654 " or $8, $8, $9\n" 655 " .word 0x4088b008\n" /* mtc0 t0, $22, 8 */ 656 " sync\n" 657 " li $8, 0x0\n" 658 " .word 0x4088b00f\n" /* mtc0 t0, $22, 15 */ 659 " .set reorder\n" 660 : : : "$8", "$9"); 661 662 /* XI enable */ 663 set_c0_brcm_config(BIT(27)); 664 665 /* enable MIPS32R2 ROR instruction for XI TLB handlers */ 666 __asm__ __volatile__( 667 " li $8, 0x5a455048\n" 668 " .word 0x4088b00f\n" /* mtc0 $8, $22, 15 */ 669 " nop; nop; nop\n" 670 " .word 0x4008b008\n" /* mfc0 $8, $22, 8 */ 671 " lui $9, 0x0100\n" 672 " or $8, $9\n" 673 " .word 0x4088b008\n" /* mtc0 $8, $22, 8 */ 674 : : : "$8", "$9"); 675 break; 676 } 677 } 678