1 /* 2 * This file is subject to the terms and conditions of the GNU General Public 3 * License. See the file "COPYING" in the main directory of this archive 4 * for more details. 5 * 6 * Copyright (C) 2011 by Kevin Cernekee (cernekee@gmail.com) 7 * 8 * SMP support for BMIPS 9 */ 10 11 #include <linux/init.h> 12 #include <linux/sched.h> 13 #include <linux/mm.h> 14 #include <linux/delay.h> 15 #include <linux/smp.h> 16 #include <linux/interrupt.h> 17 #include <linux/spinlock.h> 18 #include <linux/cpu.h> 19 #include <linux/cpumask.h> 20 #include <linux/reboot.h> 21 #include <linux/io.h> 22 #include <linux/compiler.h> 23 #include <linux/linkage.h> 24 #include <linux/bug.h> 25 #include <linux/kernel.h> 26 27 #include <asm/time.h> 28 #include <asm/pgtable.h> 29 #include <asm/processor.h> 30 #include <asm/bootinfo.h> 31 #include <asm/pmon.h> 32 #include <asm/cacheflush.h> 33 #include <asm/tlbflush.h> 34 #include <asm/mipsregs.h> 35 #include <asm/bmips.h> 36 #include <asm/traps.h> 37 #include <asm/barrier.h> 38 #include <asm/cpu-features.h> 39 40 static int __maybe_unused max_cpus = 1; 41 42 /* these may be configured by the platform code */ 43 int bmips_smp_enabled = 1; 44 int bmips_cpu_offset; 45 cpumask_t bmips_booted_mask; 46 unsigned long bmips_tp1_irqs = IE_IRQ1; 47 48 #define RESET_FROM_KSEG0 0x80080800 49 #define RESET_FROM_KSEG1 0xa0080800 50 51 static void bmips_set_reset_vec(int cpu, u32 val); 52 53 #ifdef CONFIG_SMP 54 55 /* initial $sp, $gp - used by arch/mips/kernel/bmips_vec.S */ 56 unsigned long bmips_smp_boot_sp; 57 unsigned long bmips_smp_boot_gp; 58 59 static void bmips43xx_send_ipi_single(int cpu, unsigned int action); 60 static void bmips5000_send_ipi_single(int cpu, unsigned int action); 61 static irqreturn_t bmips43xx_ipi_interrupt(int irq, void *dev_id); 62 static irqreturn_t bmips5000_ipi_interrupt(int irq, void *dev_id); 63 64 /* SW interrupts 0,1 are used for interprocessor signaling */ 65 #define IPI0_IRQ (MIPS_CPU_IRQ_BASE + 0) 66 #define IPI1_IRQ (MIPS_CPU_IRQ_BASE + 1) 67 68 #define CPUNUM(cpu, shift) (((cpu) + bmips_cpu_offset) << (shift)) 69 #define ACTION_CLR_IPI(cpu, ipi) (0x2000 | CPUNUM(cpu, 9) | ((ipi) << 8)) 70 #define ACTION_SET_IPI(cpu, ipi) (0x3000 | CPUNUM(cpu, 9) | ((ipi) << 8)) 71 #define ACTION_BOOT_THREAD(cpu) (0x08 | CPUNUM(cpu, 0)) 72 73 static void __init bmips_smp_setup(void) 74 { 75 int i, cpu = 1, boot_cpu = 0; 76 int cpu_hw_intr; 77 78 switch (current_cpu_type()) { 79 case CPU_BMIPS4350: 80 case CPU_BMIPS4380: 81 /* arbitration priority */ 82 clear_c0_brcm_cmt_ctrl(0x30); 83 84 /* NBK and weak order flags */ 85 set_c0_brcm_config_0(0x30000); 86 87 /* Find out if we are running on TP0 or TP1 */ 88 boot_cpu = !!(read_c0_brcm_cmt_local() & (1 << 31)); 89 90 /* 91 * MIPS interrupts 0,1 (SW INT 0,1) cross over to the other 92 * thread 93 * MIPS interrupt 2 (HW INT 0) is the CPU0 L1 controller output 94 * MIPS interrupt 3 (HW INT 1) is the CPU1 L1 controller output 95 */ 96 if (boot_cpu == 0) 97 cpu_hw_intr = 0x02; 98 else 99 cpu_hw_intr = 0x1d; 100 101 change_c0_brcm_cmt_intr(0xf8018000, 102 (cpu_hw_intr << 27) | (0x03 << 15)); 103 104 /* single core, 2 threads (2 pipelines) */ 105 max_cpus = 2; 106 107 break; 108 case CPU_BMIPS5000: 109 /* enable raceless SW interrupts */ 110 set_c0_brcm_config(0x03 << 22); 111 112 /* route HW interrupt 0 to CPU0, HW interrupt 1 to CPU1 */ 113 change_c0_brcm_mode(0x1f << 27, 0x02 << 27); 114 115 /* N cores, 2 threads per core */ 116 max_cpus = (((read_c0_brcm_config() >> 6) & 0x03) + 1) << 1; 117 118 /* clear any pending SW interrupts */ 119 for (i = 0; i < max_cpus; i++) { 120 write_c0_brcm_action(ACTION_CLR_IPI(i, 0)); 121 write_c0_brcm_action(ACTION_CLR_IPI(i, 1)); 122 } 123 124 break; 125 default: 126 max_cpus = 1; 127 } 128 129 if (!bmips_smp_enabled) 130 max_cpus = 1; 131 132 /* this can be overridden by the BSP */ 133 if (!board_ebase_setup) 134 board_ebase_setup = &bmips_ebase_setup; 135 136 __cpu_number_map[boot_cpu] = 0; 137 __cpu_logical_map[0] = boot_cpu; 138 139 for (i = 0; i < max_cpus; i++) { 140 if (i != boot_cpu) { 141 __cpu_number_map[i] = cpu; 142 __cpu_logical_map[cpu] = i; 143 cpu++; 144 } 145 set_cpu_possible(i, 1); 146 set_cpu_present(i, 1); 147 } 148 } 149 150 /* 151 * IPI IRQ setup - runs on CPU0 152 */ 153 static void bmips_prepare_cpus(unsigned int max_cpus) 154 { 155 irqreturn_t (*bmips_ipi_interrupt)(int irq, void *dev_id); 156 157 switch (current_cpu_type()) { 158 case CPU_BMIPS4350: 159 case CPU_BMIPS4380: 160 bmips_ipi_interrupt = bmips43xx_ipi_interrupt; 161 break; 162 case CPU_BMIPS5000: 163 bmips_ipi_interrupt = bmips5000_ipi_interrupt; 164 break; 165 default: 166 return; 167 } 168 169 if (request_irq(IPI0_IRQ, bmips_ipi_interrupt, IRQF_PERCPU, 170 "smp_ipi0", NULL)) 171 panic("Can't request IPI0 interrupt"); 172 if (request_irq(IPI1_IRQ, bmips_ipi_interrupt, IRQF_PERCPU, 173 "smp_ipi1", NULL)) 174 panic("Can't request IPI1 interrupt"); 175 } 176 177 /* 178 * Tell the hardware to boot CPUx - runs on CPU0 179 */ 180 static void bmips_boot_secondary(int cpu, struct task_struct *idle) 181 { 182 bmips_smp_boot_sp = __KSTK_TOS(idle); 183 bmips_smp_boot_gp = (unsigned long)task_thread_info(idle); 184 mb(); 185 186 /* 187 * Initial boot sequence for secondary CPU: 188 * bmips_reset_nmi_vec @ a000_0000 -> 189 * bmips_smp_entry -> 190 * plat_wired_tlb_setup (cached function call; optional) -> 191 * start_secondary (cached jump) 192 * 193 * Warm restart sequence: 194 * play_dead WAIT loop -> 195 * bmips_smp_int_vec @ BMIPS_WARM_RESTART_VEC -> 196 * eret to play_dead -> 197 * bmips_secondary_reentry -> 198 * start_secondary 199 */ 200 201 pr_info("SMP: Booting CPU%d...\n", cpu); 202 203 if (cpumask_test_cpu(cpu, &bmips_booted_mask)) { 204 /* kseg1 might not exist if this CPU enabled XKS01 */ 205 bmips_set_reset_vec(cpu, RESET_FROM_KSEG0); 206 207 switch (current_cpu_type()) { 208 case CPU_BMIPS4350: 209 case CPU_BMIPS4380: 210 bmips43xx_send_ipi_single(cpu, 0); 211 break; 212 case CPU_BMIPS5000: 213 bmips5000_send_ipi_single(cpu, 0); 214 break; 215 } 216 } else { 217 bmips_set_reset_vec(cpu, RESET_FROM_KSEG1); 218 219 switch (current_cpu_type()) { 220 case CPU_BMIPS4350: 221 case CPU_BMIPS4380: 222 /* Reset slave TP1 if booting from TP0 */ 223 if (cpu_logical_map(cpu) == 1) 224 set_c0_brcm_cmt_ctrl(0x01); 225 break; 226 case CPU_BMIPS5000: 227 write_c0_brcm_action(ACTION_BOOT_THREAD(cpu)); 228 break; 229 } 230 cpumask_set_cpu(cpu, &bmips_booted_mask); 231 } 232 } 233 234 /* 235 * Early setup - runs on secondary CPU after cache probe 236 */ 237 static void bmips_init_secondary(void) 238 { 239 switch (current_cpu_type()) { 240 case CPU_BMIPS4350: 241 case CPU_BMIPS4380: 242 clear_c0_cause(smp_processor_id() ? C_SW1 : C_SW0); 243 break; 244 case CPU_BMIPS5000: 245 write_c0_brcm_action(ACTION_CLR_IPI(smp_processor_id(), 0)); 246 current_cpu_data.core = (read_c0_brcm_config() >> 25) & 3; 247 break; 248 } 249 } 250 251 /* 252 * Late setup - runs on secondary CPU before entering the idle loop 253 */ 254 static void bmips_smp_finish(void) 255 { 256 pr_info("SMP: CPU%d is running\n", smp_processor_id()); 257 258 /* make sure there won't be a timer interrupt for a little while */ 259 write_c0_compare(read_c0_count() + mips_hpt_frequency / HZ); 260 261 irq_enable_hazard(); 262 set_c0_status(IE_SW0 | IE_SW1 | bmips_tp1_irqs | IE_IRQ5 | ST0_IE); 263 irq_enable_hazard(); 264 } 265 266 /* 267 * BMIPS5000 raceless IPIs 268 * 269 * Each CPU has two inbound SW IRQs which are independent of all other CPUs. 270 * IPI0 is used for SMP_RESCHEDULE_YOURSELF 271 * IPI1 is used for SMP_CALL_FUNCTION 272 */ 273 274 static void bmips5000_send_ipi_single(int cpu, unsigned int action) 275 { 276 write_c0_brcm_action(ACTION_SET_IPI(cpu, action == SMP_CALL_FUNCTION)); 277 } 278 279 static irqreturn_t bmips5000_ipi_interrupt(int irq, void *dev_id) 280 { 281 int action = irq - IPI0_IRQ; 282 283 write_c0_brcm_action(ACTION_CLR_IPI(smp_processor_id(), action)); 284 285 if (action == 0) 286 scheduler_ipi(); 287 else 288 generic_smp_call_function_interrupt(); 289 290 return IRQ_HANDLED; 291 } 292 293 static void bmips5000_send_ipi_mask(const struct cpumask *mask, 294 unsigned int action) 295 { 296 unsigned int i; 297 298 for_each_cpu(i, mask) 299 bmips5000_send_ipi_single(i, action); 300 } 301 302 /* 303 * BMIPS43xx racey IPIs 304 * 305 * We use one inbound SW IRQ for each CPU. 306 * 307 * A spinlock must be held in order to keep CPUx from accidentally clearing 308 * an incoming IPI when it writes CP0 CAUSE to raise an IPI on CPUy. The 309 * same spinlock is used to protect the action masks. 310 */ 311 312 static DEFINE_SPINLOCK(ipi_lock); 313 static DEFINE_PER_CPU(int, ipi_action_mask); 314 315 static void bmips43xx_send_ipi_single(int cpu, unsigned int action) 316 { 317 unsigned long flags; 318 319 spin_lock_irqsave(&ipi_lock, flags); 320 set_c0_cause(cpu ? C_SW1 : C_SW0); 321 per_cpu(ipi_action_mask, cpu) |= action; 322 irq_enable_hazard(); 323 spin_unlock_irqrestore(&ipi_lock, flags); 324 } 325 326 static irqreturn_t bmips43xx_ipi_interrupt(int irq, void *dev_id) 327 { 328 unsigned long flags; 329 int action, cpu = irq - IPI0_IRQ; 330 331 spin_lock_irqsave(&ipi_lock, flags); 332 action = __this_cpu_read(ipi_action_mask); 333 per_cpu(ipi_action_mask, cpu) = 0; 334 clear_c0_cause(cpu ? C_SW1 : C_SW0); 335 spin_unlock_irqrestore(&ipi_lock, flags); 336 337 if (action & SMP_RESCHEDULE_YOURSELF) 338 scheduler_ipi(); 339 if (action & SMP_CALL_FUNCTION) 340 generic_smp_call_function_interrupt(); 341 342 return IRQ_HANDLED; 343 } 344 345 static void bmips43xx_send_ipi_mask(const struct cpumask *mask, 346 unsigned int action) 347 { 348 unsigned int i; 349 350 for_each_cpu(i, mask) 351 bmips43xx_send_ipi_single(i, action); 352 } 353 354 #ifdef CONFIG_HOTPLUG_CPU 355 356 static int bmips_cpu_disable(void) 357 { 358 unsigned int cpu = smp_processor_id(); 359 360 if (cpu == 0) 361 return -EBUSY; 362 363 pr_info("SMP: CPU%d is offline\n", cpu); 364 365 set_cpu_online(cpu, false); 366 cpumask_clear_cpu(cpu, &cpu_callin_map); 367 clear_c0_status(IE_IRQ5); 368 369 local_flush_tlb_all(); 370 local_flush_icache_range(0, ~0); 371 372 return 0; 373 } 374 375 static void bmips_cpu_die(unsigned int cpu) 376 { 377 } 378 379 void __ref play_dead(void) 380 { 381 idle_task_exit(); 382 383 /* flush data cache */ 384 _dma_cache_wback_inv(0, ~0); 385 386 /* 387 * Wakeup is on SW0 or SW1; disable everything else 388 * Use BEV !IV (BMIPS_WARM_RESTART_VEC) to avoid the regular Linux 389 * IRQ handlers; this clears ST0_IE and returns immediately. 390 */ 391 clear_c0_cause(CAUSEF_IV | C_SW0 | C_SW1); 392 change_c0_status( 393 IE_IRQ5 | bmips_tp1_irqs | IE_SW0 | IE_SW1 | ST0_IE | ST0_BEV, 394 IE_SW0 | IE_SW1 | ST0_IE | ST0_BEV); 395 irq_disable_hazard(); 396 397 /* 398 * wait for SW interrupt from bmips_boot_secondary(), then jump 399 * back to start_secondary() 400 */ 401 __asm__ __volatile__( 402 " wait\n" 403 " j bmips_secondary_reentry\n" 404 : : : "memory"); 405 } 406 407 #endif /* CONFIG_HOTPLUG_CPU */ 408 409 struct plat_smp_ops bmips43xx_smp_ops = { 410 .smp_setup = bmips_smp_setup, 411 .prepare_cpus = bmips_prepare_cpus, 412 .boot_secondary = bmips_boot_secondary, 413 .smp_finish = bmips_smp_finish, 414 .init_secondary = bmips_init_secondary, 415 .send_ipi_single = bmips43xx_send_ipi_single, 416 .send_ipi_mask = bmips43xx_send_ipi_mask, 417 #ifdef CONFIG_HOTPLUG_CPU 418 .cpu_disable = bmips_cpu_disable, 419 .cpu_die = bmips_cpu_die, 420 #endif 421 }; 422 423 struct plat_smp_ops bmips5000_smp_ops = { 424 .smp_setup = bmips_smp_setup, 425 .prepare_cpus = bmips_prepare_cpus, 426 .boot_secondary = bmips_boot_secondary, 427 .smp_finish = bmips_smp_finish, 428 .init_secondary = bmips_init_secondary, 429 .send_ipi_single = bmips5000_send_ipi_single, 430 .send_ipi_mask = bmips5000_send_ipi_mask, 431 #ifdef CONFIG_HOTPLUG_CPU 432 .cpu_disable = bmips_cpu_disable, 433 .cpu_die = bmips_cpu_die, 434 #endif 435 }; 436 437 #endif /* CONFIG_SMP */ 438 439 /*********************************************************************** 440 * BMIPS vector relocation 441 * This is primarily used for SMP boot, but it is applicable to some 442 * UP BMIPS systems as well. 443 ***********************************************************************/ 444 445 static void bmips_wr_vec(unsigned long dst, char *start, char *end) 446 { 447 memcpy((void *)dst, start, end - start); 448 dma_cache_wback(dst, end - start); 449 local_flush_icache_range(dst, dst + (end - start)); 450 instruction_hazard(); 451 } 452 453 static inline void bmips_nmi_handler_setup(void) 454 { 455 bmips_wr_vec(BMIPS_NMI_RESET_VEC, &bmips_reset_nmi_vec, 456 &bmips_reset_nmi_vec_end); 457 bmips_wr_vec(BMIPS_WARM_RESTART_VEC, &bmips_smp_int_vec, 458 &bmips_smp_int_vec_end); 459 } 460 461 struct reset_vec_info { 462 int cpu; 463 u32 val; 464 }; 465 466 static void bmips_set_reset_vec_remote(void *vinfo) 467 { 468 struct reset_vec_info *info = vinfo; 469 int shift = info->cpu & 0x01 ? 16 : 0; 470 u32 mask = ~(0xffff << shift), val = info->val >> 16; 471 472 preempt_disable(); 473 if (smp_processor_id() > 0) { 474 smp_call_function_single(0, &bmips_set_reset_vec_remote, 475 info, 1); 476 } else { 477 if (info->cpu & 0x02) { 478 /* BMIPS5200 "should" use mask/shift, but it's buggy */ 479 bmips_write_zscm_reg(0xa0, (val << 16) | val); 480 bmips_read_zscm_reg(0xa0); 481 } else { 482 write_c0_brcm_bootvec((read_c0_brcm_bootvec() & mask) | 483 (val << shift)); 484 } 485 } 486 preempt_enable(); 487 } 488 489 static void bmips_set_reset_vec(int cpu, u32 val) 490 { 491 struct reset_vec_info info; 492 493 if (current_cpu_type() == CPU_BMIPS5000) { 494 /* this needs to run from CPU0 (which is always online) */ 495 info.cpu = cpu; 496 info.val = val; 497 bmips_set_reset_vec_remote(&info); 498 } else { 499 void __iomem *cbr = BMIPS_GET_CBR(); 500 501 if (cpu == 0) 502 __raw_writel(val, cbr + BMIPS_RELO_VECTOR_CONTROL_0); 503 else { 504 if (current_cpu_type() != CPU_BMIPS4380) 505 return; 506 __raw_writel(val, cbr + BMIPS_RELO_VECTOR_CONTROL_1); 507 } 508 } 509 __sync(); 510 back_to_back_c0_hazard(); 511 } 512 513 void bmips_ebase_setup(void) 514 { 515 unsigned long new_ebase = ebase; 516 517 BUG_ON(ebase != CKSEG0); 518 519 switch (current_cpu_type()) { 520 case CPU_BMIPS4350: 521 /* 522 * BMIPS4350 cannot relocate the normal vectors, but it 523 * can relocate the BEV=1 vectors. So CPU1 starts up at 524 * the relocated BEV=1, IV=0 general exception vector @ 525 * 0xa000_0380. 526 * 527 * set_uncached_handler() is used here because: 528 * - CPU1 will run this from uncached space 529 * - None of the cacheflush functions are set up yet 530 */ 531 set_uncached_handler(BMIPS_WARM_RESTART_VEC - CKSEG0, 532 &bmips_smp_int_vec, 0x80); 533 __sync(); 534 return; 535 case CPU_BMIPS3300: 536 case CPU_BMIPS4380: 537 /* 538 * 0x8000_0000: reset/NMI (initially in kseg1) 539 * 0x8000_0400: normal vectors 540 */ 541 new_ebase = 0x80000400; 542 bmips_set_reset_vec(0, RESET_FROM_KSEG0); 543 break; 544 case CPU_BMIPS5000: 545 /* 546 * 0x8000_0000: reset/NMI (initially in kseg1) 547 * 0x8000_1000: normal vectors 548 */ 549 new_ebase = 0x80001000; 550 bmips_set_reset_vec(0, RESET_FROM_KSEG0); 551 write_c0_ebase(new_ebase); 552 break; 553 default: 554 return; 555 } 556 557 board_nmi_handler_setup = &bmips_nmi_handler_setup; 558 ebase = new_ebase; 559 } 560 561 asmlinkage void __weak plat_wired_tlb_setup(void) 562 { 563 /* 564 * Called when starting/restarting a secondary CPU. 565 * Kernel stacks and other important data might only be accessible 566 * once the wired entries are present. 567 */ 568 } 569 570 void __init bmips_cpu_setup(void) 571 { 572 void __iomem __maybe_unused *cbr = BMIPS_GET_CBR(); 573 u32 __maybe_unused cfg; 574 575 switch (current_cpu_type()) { 576 case CPU_BMIPS3300: 577 /* Set BIU to async mode */ 578 set_c0_brcm_bus_pll(BIT(22)); 579 __sync(); 580 581 /* put the BIU back in sync mode */ 582 clear_c0_brcm_bus_pll(BIT(22)); 583 584 /* clear BHTD to enable branch history table */ 585 clear_c0_brcm_reset(BIT(16)); 586 587 /* Flush and enable RAC */ 588 cfg = __raw_readl(cbr + BMIPS_RAC_CONFIG); 589 __raw_writel(cfg | 0x100, BMIPS_RAC_CONFIG); 590 __raw_readl(cbr + BMIPS_RAC_CONFIG); 591 592 cfg = __raw_readl(cbr + BMIPS_RAC_CONFIG); 593 __raw_writel(cfg | 0xf, BMIPS_RAC_CONFIG); 594 __raw_readl(cbr + BMIPS_RAC_CONFIG); 595 596 cfg = __raw_readl(cbr + BMIPS_RAC_ADDRESS_RANGE); 597 __raw_writel(cfg | 0x0fff0000, cbr + BMIPS_RAC_ADDRESS_RANGE); 598 __raw_readl(cbr + BMIPS_RAC_ADDRESS_RANGE); 599 break; 600 601 case CPU_BMIPS4380: 602 /* CBG workaround for early BMIPS4380 CPUs */ 603 switch (read_c0_prid()) { 604 case 0x2a040: 605 case 0x2a042: 606 case 0x2a044: 607 case 0x2a060: 608 cfg = __raw_readl(cbr + BMIPS_L2_CONFIG); 609 __raw_writel(cfg & ~0x07000000, cbr + BMIPS_L2_CONFIG); 610 __raw_readl(cbr + BMIPS_L2_CONFIG); 611 } 612 613 /* clear BHTD to enable branch history table */ 614 clear_c0_brcm_config_0(BIT(21)); 615 616 /* XI/ROTR enable */ 617 set_c0_brcm_config_0(BIT(23)); 618 set_c0_brcm_cmt_ctrl(BIT(15)); 619 break; 620 621 case CPU_BMIPS5000: 622 /* enable RDHWR, BRDHWR */ 623 set_c0_brcm_config(BIT(17) | BIT(21)); 624 625 /* Disable JTB */ 626 __asm__ __volatile__( 627 " .set noreorder\n" 628 " li $8, 0x5a455048\n" 629 " .word 0x4088b00f\n" /* mtc0 t0, $22, 15 */ 630 " .word 0x4008b008\n" /* mfc0 t0, $22, 8 */ 631 " li $9, 0x00008000\n" 632 " or $8, $8, $9\n" 633 " .word 0x4088b008\n" /* mtc0 t0, $22, 8 */ 634 " sync\n" 635 " li $8, 0x0\n" 636 " .word 0x4088b00f\n" /* mtc0 t0, $22, 15 */ 637 " .set reorder\n" 638 : : : "$8", "$9"); 639 640 /* XI enable */ 641 set_c0_brcm_config(BIT(27)); 642 643 /* enable MIPS32R2 ROR instruction for XI TLB handlers */ 644 __asm__ __volatile__( 645 " li $8, 0x5a455048\n" 646 " .word 0x4088b00f\n" /* mtc0 $8, $22, 15 */ 647 " nop; nop; nop\n" 648 " .word 0x4008b008\n" /* mfc0 $8, $22, 8 */ 649 " lui $9, 0x0100\n" 650 " or $8, $9\n" 651 " .word 0x4088b008\n" /* mtc0 $8, $22, 8 */ 652 : : : "$8", "$9"); 653 break; 654 } 655 } 656