1/* 2 * This file is subject to the terms and conditions of the GNU General Public 3 * License. See the file "COPYING" in the main directory of this archive 4 * for more details. 5 * 6 * Copyright (C) 1996, 98, 99, 2000, 01 Ralf Baechle 7 * 8 * Multi-arch abstraction and asm macros for easier reading: 9 * Copyright (C) 1996 David S. Miller (davem@davemloft.net) 10 * 11 * Carsten Langgaard, carstenl@mips.com 12 * Copyright (C) 2000 MIPS Technologies, Inc. 13 * Copyright (C) 1999, 2001 Silicon Graphics, Inc. 14 */ 15#include <asm/asm.h> 16#include <asm/errno.h> 17#include <asm/fpregdef.h> 18#include <asm/mipsregs.h> 19#include <asm/asm-offsets.h> 20#include <asm/regdef.h> 21 22 .macro EX insn, reg, src 23 .set push 24 .set nomacro 25.ex\@: \insn \reg, \src 26 .set pop 27 .section __ex_table,"a" 28 PTR .ex\@, fault 29 .previous 30 .endm 31 32 .set noreorder 33 .set mips3 34 35LEAF(_save_fp_context) 36 cfc1 t1, fcr31 37 38#ifdef CONFIG_64BIT 39 /* Store the 16 odd double precision registers */ 40 EX sdc1 $f1, SC_FPREGS+8(a0) 41 EX sdc1 $f3, SC_FPREGS+24(a0) 42 EX sdc1 $f5, SC_FPREGS+40(a0) 43 EX sdc1 $f7, SC_FPREGS+56(a0) 44 EX sdc1 $f9, SC_FPREGS+72(a0) 45 EX sdc1 $f11, SC_FPREGS+88(a0) 46 EX sdc1 $f13, SC_FPREGS+104(a0) 47 EX sdc1 $f15, SC_FPREGS+120(a0) 48 EX sdc1 $f17, SC_FPREGS+136(a0) 49 EX sdc1 $f19, SC_FPREGS+152(a0) 50 EX sdc1 $f21, SC_FPREGS+168(a0) 51 EX sdc1 $f23, SC_FPREGS+184(a0) 52 EX sdc1 $f25, SC_FPREGS+200(a0) 53 EX sdc1 $f27, SC_FPREGS+216(a0) 54 EX sdc1 $f29, SC_FPREGS+232(a0) 55 EX sdc1 $f31, SC_FPREGS+248(a0) 56#endif 57 58 /* Store the 16 even double precision registers */ 59 EX sdc1 $f0, SC_FPREGS+0(a0) 60 EX sdc1 $f2, SC_FPREGS+16(a0) 61 EX sdc1 $f4, SC_FPREGS+32(a0) 62 EX sdc1 $f6, SC_FPREGS+48(a0) 63 EX sdc1 $f8, SC_FPREGS+64(a0) 64 EX sdc1 $f10, SC_FPREGS+80(a0) 65 EX sdc1 $f12, SC_FPREGS+96(a0) 66 EX sdc1 $f14, SC_FPREGS+112(a0) 67 EX sdc1 $f16, SC_FPREGS+128(a0) 68 EX sdc1 $f18, SC_FPREGS+144(a0) 69 EX sdc1 $f20, SC_FPREGS+160(a0) 70 EX sdc1 $f22, SC_FPREGS+176(a0) 71 EX sdc1 $f24, SC_FPREGS+192(a0) 72 EX sdc1 $f26, SC_FPREGS+208(a0) 73 EX sdc1 $f28, SC_FPREGS+224(a0) 74 EX sdc1 $f30, SC_FPREGS+240(a0) 75 EX sw t1, SC_FPC_CSR(a0) 76 jr ra 77 li v0, 0 # success 78 END(_save_fp_context) 79 80#ifdef CONFIG_MIPS32_COMPAT 81 /* Save 32-bit process floating point context */ 82LEAF(_save_fp_context32) 83 cfc1 t1, fcr31 84 85 EX sdc1 $f0, SC32_FPREGS+0(a0) 86 EX sdc1 $f2, SC32_FPREGS+16(a0) 87 EX sdc1 $f4, SC32_FPREGS+32(a0) 88 EX sdc1 $f6, SC32_FPREGS+48(a0) 89 EX sdc1 $f8, SC32_FPREGS+64(a0) 90 EX sdc1 $f10, SC32_FPREGS+80(a0) 91 EX sdc1 $f12, SC32_FPREGS+96(a0) 92 EX sdc1 $f14, SC32_FPREGS+112(a0) 93 EX sdc1 $f16, SC32_FPREGS+128(a0) 94 EX sdc1 $f18, SC32_FPREGS+144(a0) 95 EX sdc1 $f20, SC32_FPREGS+160(a0) 96 EX sdc1 $f22, SC32_FPREGS+176(a0) 97 EX sdc1 $f24, SC32_FPREGS+192(a0) 98 EX sdc1 $f26, SC32_FPREGS+208(a0) 99 EX sdc1 $f28, SC32_FPREGS+224(a0) 100 EX sdc1 $f30, SC32_FPREGS+240(a0) 101 EX sw t1, SC32_FPC_CSR(a0) 102 cfc1 t0, $0 # implementation/version 103 EX sw t0, SC32_FPC_EIR(a0) 104 105 jr ra 106 li v0, 0 # success 107 END(_save_fp_context32) 108#endif 109 110/* 111 * Restore FPU state: 112 * - fp gp registers 113 * - cp1 status/control register 114 */ 115LEAF(_restore_fp_context) 116 EX lw t0, SC_FPC_CSR(a0) 117#ifdef CONFIG_64BIT 118 EX ldc1 $f1, SC_FPREGS+8(a0) 119 EX ldc1 $f3, SC_FPREGS+24(a0) 120 EX ldc1 $f5, SC_FPREGS+40(a0) 121 EX ldc1 $f7, SC_FPREGS+56(a0) 122 EX ldc1 $f9, SC_FPREGS+72(a0) 123 EX ldc1 $f11, SC_FPREGS+88(a0) 124 EX ldc1 $f13, SC_FPREGS+104(a0) 125 EX ldc1 $f15, SC_FPREGS+120(a0) 126 EX ldc1 $f17, SC_FPREGS+136(a0) 127 EX ldc1 $f19, SC_FPREGS+152(a0) 128 EX ldc1 $f21, SC_FPREGS+168(a0) 129 EX ldc1 $f23, SC_FPREGS+184(a0) 130 EX ldc1 $f25, SC_FPREGS+200(a0) 131 EX ldc1 $f27, SC_FPREGS+216(a0) 132 EX ldc1 $f29, SC_FPREGS+232(a0) 133 EX ldc1 $f31, SC_FPREGS+248(a0) 134#endif 135 EX ldc1 $f0, SC_FPREGS+0(a0) 136 EX ldc1 $f2, SC_FPREGS+16(a0) 137 EX ldc1 $f4, SC_FPREGS+32(a0) 138 EX ldc1 $f6, SC_FPREGS+48(a0) 139 EX ldc1 $f8, SC_FPREGS+64(a0) 140 EX ldc1 $f10, SC_FPREGS+80(a0) 141 EX ldc1 $f12, SC_FPREGS+96(a0) 142 EX ldc1 $f14, SC_FPREGS+112(a0) 143 EX ldc1 $f16, SC_FPREGS+128(a0) 144 EX ldc1 $f18, SC_FPREGS+144(a0) 145 EX ldc1 $f20, SC_FPREGS+160(a0) 146 EX ldc1 $f22, SC_FPREGS+176(a0) 147 EX ldc1 $f24, SC_FPREGS+192(a0) 148 EX ldc1 $f26, SC_FPREGS+208(a0) 149 EX ldc1 $f28, SC_FPREGS+224(a0) 150 EX ldc1 $f30, SC_FPREGS+240(a0) 151 ctc1 t0, fcr31 152 jr ra 153 li v0, 0 # success 154 END(_restore_fp_context) 155 156#ifdef CONFIG_MIPS32_COMPAT 157LEAF(_restore_fp_context32) 158 /* Restore an o32 sigcontext. */ 159 EX lw t0, SC32_FPC_CSR(a0) 160 EX ldc1 $f0, SC32_FPREGS+0(a0) 161 EX ldc1 $f2, SC32_FPREGS+16(a0) 162 EX ldc1 $f4, SC32_FPREGS+32(a0) 163 EX ldc1 $f6, SC32_FPREGS+48(a0) 164 EX ldc1 $f8, SC32_FPREGS+64(a0) 165 EX ldc1 $f10, SC32_FPREGS+80(a0) 166 EX ldc1 $f12, SC32_FPREGS+96(a0) 167 EX ldc1 $f14, SC32_FPREGS+112(a0) 168 EX ldc1 $f16, SC32_FPREGS+128(a0) 169 EX ldc1 $f18, SC32_FPREGS+144(a0) 170 EX ldc1 $f20, SC32_FPREGS+160(a0) 171 EX ldc1 $f22, SC32_FPREGS+176(a0) 172 EX ldc1 $f24, SC32_FPREGS+192(a0) 173 EX ldc1 $f26, SC32_FPREGS+208(a0) 174 EX ldc1 $f28, SC32_FPREGS+224(a0) 175 EX ldc1 $f30, SC32_FPREGS+240(a0) 176 ctc1 t0, fcr31 177 jr ra 178 li v0, 0 # success 179 END(_restore_fp_context32) 180#endif 181 182 .set reorder 183 184 .type fault@function 185 .ent fault 186fault: li v0, -EFAULT # failure 187 jr ra 188 .end fault 189