1 /* 2 * Linux performance counter support for MIPS. 3 * 4 * Copyright (C) 2010 MIPS Technologies, Inc. 5 * Copyright (C) 2011 Cavium Networks, Inc. 6 * Author: Deng-Cheng Zhu 7 * 8 * This code is based on the implementation for ARM, which is in turn 9 * based on the sparc64 perf event code and the x86 code. Performance 10 * counter access is based on the MIPS Oprofile code. And the callchain 11 * support references the code of MIPS stacktrace.c. 12 * 13 * This program is free software; you can redistribute it and/or modify 14 * it under the terms of the GNU General Public License version 2 as 15 * published by the Free Software Foundation. 16 */ 17 18 #include <linux/cpumask.h> 19 #include <linux/interrupt.h> 20 #include <linux/smp.h> 21 #include <linux/kernel.h> 22 #include <linux/perf_event.h> 23 #include <linux/uaccess.h> 24 25 #include <asm/irq.h> 26 #include <asm/irq_regs.h> 27 #include <asm/stacktrace.h> 28 #include <asm/time.h> /* For perf_irq */ 29 30 #define MIPS_MAX_HWEVENTS 4 31 #define MIPS_TCS_PER_COUNTER 2 32 #define MIPS_CPUID_TO_COUNTER_MASK (MIPS_TCS_PER_COUNTER - 1) 33 34 struct cpu_hw_events { 35 /* Array of events on this cpu. */ 36 struct perf_event *events[MIPS_MAX_HWEVENTS]; 37 38 /* 39 * Set the bit (indexed by the counter number) when the counter 40 * is used for an event. 41 */ 42 unsigned long used_mask[BITS_TO_LONGS(MIPS_MAX_HWEVENTS)]; 43 44 /* 45 * Software copy of the control register for each performance counter. 46 * MIPS CPUs vary in performance counters. They use this differently, 47 * and even may not use it. 48 */ 49 unsigned int saved_ctrl[MIPS_MAX_HWEVENTS]; 50 }; 51 DEFINE_PER_CPU(struct cpu_hw_events, cpu_hw_events) = { 52 .saved_ctrl = {0}, 53 }; 54 55 /* The description of MIPS performance events. */ 56 struct mips_perf_event { 57 unsigned int event_id; 58 /* 59 * MIPS performance counters are indexed starting from 0. 60 * CNTR_EVEN indicates the indexes of the counters to be used are 61 * even numbers. 62 */ 63 unsigned int cntr_mask; 64 #define CNTR_EVEN 0x55555555 65 #define CNTR_ODD 0xaaaaaaaa 66 #define CNTR_ALL 0xffffffff 67 #ifdef CONFIG_MIPS_MT_SMP 68 enum { 69 T = 0, 70 V = 1, 71 P = 2, 72 } range; 73 #else 74 #define T 75 #define V 76 #define P 77 #endif 78 }; 79 80 static struct mips_perf_event raw_event; 81 static DEFINE_MUTEX(raw_event_mutex); 82 83 #define C(x) PERF_COUNT_HW_CACHE_##x 84 85 struct mips_pmu { 86 u64 max_period; 87 u64 valid_count; 88 u64 overflow; 89 const char *name; 90 int irq; 91 u64 (*read_counter)(unsigned int idx); 92 void (*write_counter)(unsigned int idx, u64 val); 93 const struct mips_perf_event *(*map_raw_event)(u64 config); 94 const struct mips_perf_event (*general_event_map)[PERF_COUNT_HW_MAX]; 95 const struct mips_perf_event (*cache_event_map) 96 [PERF_COUNT_HW_CACHE_MAX] 97 [PERF_COUNT_HW_CACHE_OP_MAX] 98 [PERF_COUNT_HW_CACHE_RESULT_MAX]; 99 unsigned int num_counters; 100 }; 101 102 static struct mips_pmu mipspmu; 103 104 #define M_CONFIG1_PC (1 << 4) 105 106 #define M_PERFCTL_EXL (1 << 0) 107 #define M_PERFCTL_KERNEL (1 << 1) 108 #define M_PERFCTL_SUPERVISOR (1 << 2) 109 #define M_PERFCTL_USER (1 << 3) 110 #define M_PERFCTL_INTERRUPT_ENABLE (1 << 4) 111 #define M_PERFCTL_EVENT(event) (((event) & 0x3ff) << 5) 112 #define M_PERFCTL_VPEID(vpe) ((vpe) << 16) 113 114 #ifdef CONFIG_CPU_BMIPS5000 115 #define M_PERFCTL_MT_EN(filter) 0 116 #else /* !CONFIG_CPU_BMIPS5000 */ 117 #define M_PERFCTL_MT_EN(filter) ((filter) << 20) 118 #endif /* CONFIG_CPU_BMIPS5000 */ 119 120 #define M_TC_EN_ALL M_PERFCTL_MT_EN(0) 121 #define M_TC_EN_VPE M_PERFCTL_MT_EN(1) 122 #define M_TC_EN_TC M_PERFCTL_MT_EN(2) 123 #define M_PERFCTL_TCID(tcid) ((tcid) << 22) 124 #define M_PERFCTL_WIDE (1 << 30) 125 #define M_PERFCTL_MORE (1 << 31) 126 #define M_PERFCTL_TC (1 << 30) 127 128 #define M_PERFCTL_COUNT_EVENT_WHENEVER (M_PERFCTL_EXL | \ 129 M_PERFCTL_KERNEL | \ 130 M_PERFCTL_USER | \ 131 M_PERFCTL_SUPERVISOR | \ 132 M_PERFCTL_INTERRUPT_ENABLE) 133 134 #ifdef CONFIG_MIPS_MT_SMP 135 #define M_PERFCTL_CONFIG_MASK 0x3fff801f 136 #else 137 #define M_PERFCTL_CONFIG_MASK 0x1f 138 #endif 139 #define M_PERFCTL_EVENT_MASK 0xfe0 140 141 142 #ifdef CONFIG_MIPS_PERF_SHARED_TC_COUNTERS 143 static int cpu_has_mipsmt_pertccounters; 144 145 static DEFINE_RWLOCK(pmuint_rwlock); 146 147 #if defined(CONFIG_CPU_BMIPS5000) 148 #define vpe_id() (cpu_has_mipsmt_pertccounters ? \ 149 0 : (smp_processor_id() & MIPS_CPUID_TO_COUNTER_MASK)) 150 #else 151 /* 152 * FIXME: For VSMP, vpe_id() is redefined for Perf-events, because 153 * cpu_data[cpuid].vpe_id reports 0 for _both_ CPUs. 154 */ 155 #define vpe_id() (cpu_has_mipsmt_pertccounters ? \ 156 0 : smp_processor_id()) 157 #endif 158 159 /* Copied from op_model_mipsxx.c */ 160 static unsigned int vpe_shift(void) 161 { 162 if (num_possible_cpus() > 1) 163 return 1; 164 165 return 0; 166 } 167 168 static unsigned int counters_total_to_per_cpu(unsigned int counters) 169 { 170 return counters >> vpe_shift(); 171 } 172 173 #else /* !CONFIG_MIPS_PERF_SHARED_TC_COUNTERS */ 174 #define vpe_id() 0 175 176 #endif /* CONFIG_MIPS_PERF_SHARED_TC_COUNTERS */ 177 178 static void resume_local_counters(void); 179 static void pause_local_counters(void); 180 static irqreturn_t mipsxx_pmu_handle_irq(int, void *); 181 static int mipsxx_pmu_handle_shared_irq(void); 182 183 static unsigned int mipsxx_pmu_swizzle_perf_idx(unsigned int idx) 184 { 185 if (vpe_id() == 1) 186 idx = (idx + 2) & 3; 187 return idx; 188 } 189 190 static u64 mipsxx_pmu_read_counter(unsigned int idx) 191 { 192 idx = mipsxx_pmu_swizzle_perf_idx(idx); 193 194 switch (idx) { 195 case 0: 196 /* 197 * The counters are unsigned, we must cast to truncate 198 * off the high bits. 199 */ 200 return (u32)read_c0_perfcntr0(); 201 case 1: 202 return (u32)read_c0_perfcntr1(); 203 case 2: 204 return (u32)read_c0_perfcntr2(); 205 case 3: 206 return (u32)read_c0_perfcntr3(); 207 default: 208 WARN_ONCE(1, "Invalid performance counter number (%d)\n", idx); 209 return 0; 210 } 211 } 212 213 static u64 mipsxx_pmu_read_counter_64(unsigned int idx) 214 { 215 idx = mipsxx_pmu_swizzle_perf_idx(idx); 216 217 switch (idx) { 218 case 0: 219 return read_c0_perfcntr0_64(); 220 case 1: 221 return read_c0_perfcntr1_64(); 222 case 2: 223 return read_c0_perfcntr2_64(); 224 case 3: 225 return read_c0_perfcntr3_64(); 226 default: 227 WARN_ONCE(1, "Invalid performance counter number (%d)\n", idx); 228 return 0; 229 } 230 } 231 232 static void mipsxx_pmu_write_counter(unsigned int idx, u64 val) 233 { 234 idx = mipsxx_pmu_swizzle_perf_idx(idx); 235 236 switch (idx) { 237 case 0: 238 write_c0_perfcntr0(val); 239 return; 240 case 1: 241 write_c0_perfcntr1(val); 242 return; 243 case 2: 244 write_c0_perfcntr2(val); 245 return; 246 case 3: 247 write_c0_perfcntr3(val); 248 return; 249 } 250 } 251 252 static void mipsxx_pmu_write_counter_64(unsigned int idx, u64 val) 253 { 254 idx = mipsxx_pmu_swizzle_perf_idx(idx); 255 256 switch (idx) { 257 case 0: 258 write_c0_perfcntr0_64(val); 259 return; 260 case 1: 261 write_c0_perfcntr1_64(val); 262 return; 263 case 2: 264 write_c0_perfcntr2_64(val); 265 return; 266 case 3: 267 write_c0_perfcntr3_64(val); 268 return; 269 } 270 } 271 272 static unsigned int mipsxx_pmu_read_control(unsigned int idx) 273 { 274 idx = mipsxx_pmu_swizzle_perf_idx(idx); 275 276 switch (idx) { 277 case 0: 278 return read_c0_perfctrl0(); 279 case 1: 280 return read_c0_perfctrl1(); 281 case 2: 282 return read_c0_perfctrl2(); 283 case 3: 284 return read_c0_perfctrl3(); 285 default: 286 WARN_ONCE(1, "Invalid performance counter number (%d)\n", idx); 287 return 0; 288 } 289 } 290 291 static void mipsxx_pmu_write_control(unsigned int idx, unsigned int val) 292 { 293 idx = mipsxx_pmu_swizzle_perf_idx(idx); 294 295 switch (idx) { 296 case 0: 297 write_c0_perfctrl0(val); 298 return; 299 case 1: 300 write_c0_perfctrl1(val); 301 return; 302 case 2: 303 write_c0_perfctrl2(val); 304 return; 305 case 3: 306 write_c0_perfctrl3(val); 307 return; 308 } 309 } 310 311 static int mipsxx_pmu_alloc_counter(struct cpu_hw_events *cpuc, 312 struct hw_perf_event *hwc) 313 { 314 int i; 315 316 /* 317 * We only need to care the counter mask. The range has been 318 * checked definitely. 319 */ 320 unsigned long cntr_mask = (hwc->event_base >> 8) & 0xffff; 321 322 for (i = mipspmu.num_counters - 1; i >= 0; i--) { 323 /* 324 * Note that some MIPS perf events can be counted by both 325 * even and odd counters, wheresas many other are only by 326 * even _or_ odd counters. This introduces an issue that 327 * when the former kind of event takes the counter the 328 * latter kind of event wants to use, then the "counter 329 * allocation" for the latter event will fail. In fact if 330 * they can be dynamically swapped, they both feel happy. 331 * But here we leave this issue alone for now. 332 */ 333 if (test_bit(i, &cntr_mask) && 334 !test_and_set_bit(i, cpuc->used_mask)) 335 return i; 336 } 337 338 return -EAGAIN; 339 } 340 341 static void mipsxx_pmu_enable_event(struct hw_perf_event *evt, int idx) 342 { 343 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); 344 345 WARN_ON(idx < 0 || idx >= mipspmu.num_counters); 346 347 cpuc->saved_ctrl[idx] = M_PERFCTL_EVENT(evt->event_base & 0xff) | 348 (evt->config_base & M_PERFCTL_CONFIG_MASK) | 349 /* Make sure interrupt enabled. */ 350 M_PERFCTL_INTERRUPT_ENABLE; 351 if (IS_ENABLED(CONFIG_CPU_BMIPS5000)) 352 /* enable the counter for the calling thread */ 353 cpuc->saved_ctrl[idx] |= 354 (1 << (12 + vpe_id())) | M_PERFCTL_TC; 355 356 /* 357 * We do not actually let the counter run. Leave it until start(). 358 */ 359 } 360 361 static void mipsxx_pmu_disable_event(int idx) 362 { 363 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); 364 unsigned long flags; 365 366 WARN_ON(idx < 0 || idx >= mipspmu.num_counters); 367 368 local_irq_save(flags); 369 cpuc->saved_ctrl[idx] = mipsxx_pmu_read_control(idx) & 370 ~M_PERFCTL_COUNT_EVENT_WHENEVER; 371 mipsxx_pmu_write_control(idx, cpuc->saved_ctrl[idx]); 372 local_irq_restore(flags); 373 } 374 375 static int mipspmu_event_set_period(struct perf_event *event, 376 struct hw_perf_event *hwc, 377 int idx) 378 { 379 u64 left = local64_read(&hwc->period_left); 380 u64 period = hwc->sample_period; 381 int ret = 0; 382 383 if (unlikely((left + period) & (1ULL << 63))) { 384 /* left underflowed by more than period. */ 385 left = period; 386 local64_set(&hwc->period_left, left); 387 hwc->last_period = period; 388 ret = 1; 389 } else if (unlikely((left + period) <= period)) { 390 /* left underflowed by less than period. */ 391 left += period; 392 local64_set(&hwc->period_left, left); 393 hwc->last_period = period; 394 ret = 1; 395 } 396 397 if (left > mipspmu.max_period) { 398 left = mipspmu.max_period; 399 local64_set(&hwc->period_left, left); 400 } 401 402 local64_set(&hwc->prev_count, mipspmu.overflow - left); 403 404 mipspmu.write_counter(idx, mipspmu.overflow - left); 405 406 perf_event_update_userpage(event); 407 408 return ret; 409 } 410 411 static void mipspmu_event_update(struct perf_event *event, 412 struct hw_perf_event *hwc, 413 int idx) 414 { 415 u64 prev_raw_count, new_raw_count; 416 u64 delta; 417 418 again: 419 prev_raw_count = local64_read(&hwc->prev_count); 420 new_raw_count = mipspmu.read_counter(idx); 421 422 if (local64_cmpxchg(&hwc->prev_count, prev_raw_count, 423 new_raw_count) != prev_raw_count) 424 goto again; 425 426 delta = new_raw_count - prev_raw_count; 427 428 local64_add(delta, &event->count); 429 local64_sub(delta, &hwc->period_left); 430 } 431 432 static void mipspmu_start(struct perf_event *event, int flags) 433 { 434 struct hw_perf_event *hwc = &event->hw; 435 436 if (flags & PERF_EF_RELOAD) 437 WARN_ON_ONCE(!(hwc->state & PERF_HES_UPTODATE)); 438 439 hwc->state = 0; 440 441 /* Set the period for the event. */ 442 mipspmu_event_set_period(event, hwc, hwc->idx); 443 444 /* Enable the event. */ 445 mipsxx_pmu_enable_event(hwc, hwc->idx); 446 } 447 448 static void mipspmu_stop(struct perf_event *event, int flags) 449 { 450 struct hw_perf_event *hwc = &event->hw; 451 452 if (!(hwc->state & PERF_HES_STOPPED)) { 453 /* We are working on a local event. */ 454 mipsxx_pmu_disable_event(hwc->idx); 455 barrier(); 456 mipspmu_event_update(event, hwc, hwc->idx); 457 hwc->state |= PERF_HES_STOPPED | PERF_HES_UPTODATE; 458 } 459 } 460 461 static int mipspmu_add(struct perf_event *event, int flags) 462 { 463 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); 464 struct hw_perf_event *hwc = &event->hw; 465 int idx; 466 int err = 0; 467 468 perf_pmu_disable(event->pmu); 469 470 /* To look for a free counter for this event. */ 471 idx = mipsxx_pmu_alloc_counter(cpuc, hwc); 472 if (idx < 0) { 473 err = idx; 474 goto out; 475 } 476 477 /* 478 * If there is an event in the counter we are going to use then 479 * make sure it is disabled. 480 */ 481 event->hw.idx = idx; 482 mipsxx_pmu_disable_event(idx); 483 cpuc->events[idx] = event; 484 485 hwc->state = PERF_HES_STOPPED | PERF_HES_UPTODATE; 486 if (flags & PERF_EF_START) 487 mipspmu_start(event, PERF_EF_RELOAD); 488 489 /* Propagate our changes to the userspace mapping. */ 490 perf_event_update_userpage(event); 491 492 out: 493 perf_pmu_enable(event->pmu); 494 return err; 495 } 496 497 static void mipspmu_del(struct perf_event *event, int flags) 498 { 499 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); 500 struct hw_perf_event *hwc = &event->hw; 501 int idx = hwc->idx; 502 503 WARN_ON(idx < 0 || idx >= mipspmu.num_counters); 504 505 mipspmu_stop(event, PERF_EF_UPDATE); 506 cpuc->events[idx] = NULL; 507 clear_bit(idx, cpuc->used_mask); 508 509 perf_event_update_userpage(event); 510 } 511 512 static void mipspmu_read(struct perf_event *event) 513 { 514 struct hw_perf_event *hwc = &event->hw; 515 516 /* Don't read disabled counters! */ 517 if (hwc->idx < 0) 518 return; 519 520 mipspmu_event_update(event, hwc, hwc->idx); 521 } 522 523 static void mipspmu_enable(struct pmu *pmu) 524 { 525 #ifdef CONFIG_MIPS_PERF_SHARED_TC_COUNTERS 526 write_unlock(&pmuint_rwlock); 527 #endif 528 resume_local_counters(); 529 } 530 531 /* 532 * MIPS performance counters can be per-TC. The control registers can 533 * not be directly accessed accross CPUs. Hence if we want to do global 534 * control, we need cross CPU calls. on_each_cpu() can help us, but we 535 * can not make sure this function is called with interrupts enabled. So 536 * here we pause local counters and then grab a rwlock and leave the 537 * counters on other CPUs alone. If any counter interrupt raises while 538 * we own the write lock, simply pause local counters on that CPU and 539 * spin in the handler. Also we know we won't be switched to another 540 * CPU after pausing local counters and before grabbing the lock. 541 */ 542 static void mipspmu_disable(struct pmu *pmu) 543 { 544 pause_local_counters(); 545 #ifdef CONFIG_MIPS_PERF_SHARED_TC_COUNTERS 546 write_lock(&pmuint_rwlock); 547 #endif 548 } 549 550 static atomic_t active_events = ATOMIC_INIT(0); 551 static DEFINE_MUTEX(pmu_reserve_mutex); 552 static int (*save_perf_irq)(void); 553 554 static int mipspmu_get_irq(void) 555 { 556 int err; 557 558 if (mipspmu.irq >= 0) { 559 /* Request my own irq handler. */ 560 err = request_irq(mipspmu.irq, mipsxx_pmu_handle_irq, 561 IRQF_PERCPU | IRQF_NOBALANCING | IRQF_NO_THREAD, 562 "mips_perf_pmu", NULL); 563 if (err) { 564 pr_warn("Unable to request IRQ%d for MIPS performance counters!\n", 565 mipspmu.irq); 566 } 567 } else if (cp0_perfcount_irq < 0) { 568 /* 569 * We are sharing the irq number with the timer interrupt. 570 */ 571 save_perf_irq = perf_irq; 572 perf_irq = mipsxx_pmu_handle_shared_irq; 573 err = 0; 574 } else { 575 pr_warn("The platform hasn't properly defined its interrupt controller\n"); 576 err = -ENOENT; 577 } 578 579 return err; 580 } 581 582 static void mipspmu_free_irq(void) 583 { 584 if (mipspmu.irq >= 0) 585 free_irq(mipspmu.irq, NULL); 586 else if (cp0_perfcount_irq < 0) 587 perf_irq = save_perf_irq; 588 } 589 590 /* 591 * mipsxx/rm9000/loongson2 have different performance counters, they have 592 * specific low-level init routines. 593 */ 594 static void reset_counters(void *arg); 595 static int __hw_perf_event_init(struct perf_event *event); 596 597 static void hw_perf_event_destroy(struct perf_event *event) 598 { 599 if (atomic_dec_and_mutex_lock(&active_events, 600 &pmu_reserve_mutex)) { 601 /* 602 * We must not call the destroy function with interrupts 603 * disabled. 604 */ 605 on_each_cpu(reset_counters, 606 (void *)(long)mipspmu.num_counters, 1); 607 mipspmu_free_irq(); 608 mutex_unlock(&pmu_reserve_mutex); 609 } 610 } 611 612 static int mipspmu_event_init(struct perf_event *event) 613 { 614 int err = 0; 615 616 /* does not support taken branch sampling */ 617 if (has_branch_stack(event)) 618 return -EOPNOTSUPP; 619 620 switch (event->attr.type) { 621 case PERF_TYPE_RAW: 622 case PERF_TYPE_HARDWARE: 623 case PERF_TYPE_HW_CACHE: 624 break; 625 626 default: 627 return -ENOENT; 628 } 629 630 if (event->cpu >= nr_cpumask_bits || 631 (event->cpu >= 0 && !cpu_online(event->cpu))) 632 return -ENODEV; 633 634 if (!atomic_inc_not_zero(&active_events)) { 635 mutex_lock(&pmu_reserve_mutex); 636 if (atomic_read(&active_events) == 0) 637 err = mipspmu_get_irq(); 638 639 if (!err) 640 atomic_inc(&active_events); 641 mutex_unlock(&pmu_reserve_mutex); 642 } 643 644 if (err) 645 return err; 646 647 return __hw_perf_event_init(event); 648 } 649 650 static struct pmu pmu = { 651 .pmu_enable = mipspmu_enable, 652 .pmu_disable = mipspmu_disable, 653 .event_init = mipspmu_event_init, 654 .add = mipspmu_add, 655 .del = mipspmu_del, 656 .start = mipspmu_start, 657 .stop = mipspmu_stop, 658 .read = mipspmu_read, 659 }; 660 661 static unsigned int mipspmu_perf_event_encode(const struct mips_perf_event *pev) 662 { 663 /* 664 * Top 8 bits for range, next 16 bits for cntr_mask, lowest 8 bits for 665 * event_id. 666 */ 667 #ifdef CONFIG_MIPS_MT_SMP 668 return ((unsigned int)pev->range << 24) | 669 (pev->cntr_mask & 0xffff00) | 670 (pev->event_id & 0xff); 671 #else 672 return (pev->cntr_mask & 0xffff00) | 673 (pev->event_id & 0xff); 674 #endif 675 } 676 677 static const struct mips_perf_event *mipspmu_map_general_event(int idx) 678 { 679 680 if ((*mipspmu.general_event_map)[idx].cntr_mask == 0) 681 return ERR_PTR(-EOPNOTSUPP); 682 return &(*mipspmu.general_event_map)[idx]; 683 } 684 685 static const struct mips_perf_event *mipspmu_map_cache_event(u64 config) 686 { 687 unsigned int cache_type, cache_op, cache_result; 688 const struct mips_perf_event *pev; 689 690 cache_type = (config >> 0) & 0xff; 691 if (cache_type >= PERF_COUNT_HW_CACHE_MAX) 692 return ERR_PTR(-EINVAL); 693 694 cache_op = (config >> 8) & 0xff; 695 if (cache_op >= PERF_COUNT_HW_CACHE_OP_MAX) 696 return ERR_PTR(-EINVAL); 697 698 cache_result = (config >> 16) & 0xff; 699 if (cache_result >= PERF_COUNT_HW_CACHE_RESULT_MAX) 700 return ERR_PTR(-EINVAL); 701 702 pev = &((*mipspmu.cache_event_map) 703 [cache_type] 704 [cache_op] 705 [cache_result]); 706 707 if (pev->cntr_mask == 0) 708 return ERR_PTR(-EOPNOTSUPP); 709 710 return pev; 711 712 } 713 714 static int validate_group(struct perf_event *event) 715 { 716 struct perf_event *sibling, *leader = event->group_leader; 717 struct cpu_hw_events fake_cpuc; 718 719 memset(&fake_cpuc, 0, sizeof(fake_cpuc)); 720 721 if (mipsxx_pmu_alloc_counter(&fake_cpuc, &leader->hw) < 0) 722 return -EINVAL; 723 724 list_for_each_entry(sibling, &leader->sibling_list, group_entry) { 725 if (mipsxx_pmu_alloc_counter(&fake_cpuc, &sibling->hw) < 0) 726 return -EINVAL; 727 } 728 729 if (mipsxx_pmu_alloc_counter(&fake_cpuc, &event->hw) < 0) 730 return -EINVAL; 731 732 return 0; 733 } 734 735 /* This is needed by specific irq handlers in perf_event_*.c */ 736 static void handle_associated_event(struct cpu_hw_events *cpuc, 737 int idx, struct perf_sample_data *data, 738 struct pt_regs *regs) 739 { 740 struct perf_event *event = cpuc->events[idx]; 741 struct hw_perf_event *hwc = &event->hw; 742 743 mipspmu_event_update(event, hwc, idx); 744 data->period = event->hw.last_period; 745 if (!mipspmu_event_set_period(event, hwc, idx)) 746 return; 747 748 if (perf_event_overflow(event, data, regs)) 749 mipsxx_pmu_disable_event(idx); 750 } 751 752 753 static int __n_counters(void) 754 { 755 if (!(read_c0_config1() & M_CONFIG1_PC)) 756 return 0; 757 if (!(read_c0_perfctrl0() & M_PERFCTL_MORE)) 758 return 1; 759 if (!(read_c0_perfctrl1() & M_PERFCTL_MORE)) 760 return 2; 761 if (!(read_c0_perfctrl2() & M_PERFCTL_MORE)) 762 return 3; 763 764 return 4; 765 } 766 767 static int n_counters(void) 768 { 769 int counters; 770 771 switch (current_cpu_type()) { 772 case CPU_R10000: 773 counters = 2; 774 break; 775 776 case CPU_R12000: 777 case CPU_R14000: 778 counters = 4; 779 break; 780 781 default: 782 counters = __n_counters(); 783 } 784 785 return counters; 786 } 787 788 static void reset_counters(void *arg) 789 { 790 int counters = (int)(long)arg; 791 switch (counters) { 792 case 4: 793 mipsxx_pmu_write_control(3, 0); 794 mipspmu.write_counter(3, 0); 795 case 3: 796 mipsxx_pmu_write_control(2, 0); 797 mipspmu.write_counter(2, 0); 798 case 2: 799 mipsxx_pmu_write_control(1, 0); 800 mipspmu.write_counter(1, 0); 801 case 1: 802 mipsxx_pmu_write_control(0, 0); 803 mipspmu.write_counter(0, 0); 804 } 805 } 806 807 /* 24K/34K/1004K/interAptiv/loongson1 cores share the same event map. */ 808 static const struct mips_perf_event mipsxxcore_event_map 809 [PERF_COUNT_HW_MAX] = { 810 [PERF_COUNT_HW_CPU_CYCLES] = { 0x00, CNTR_EVEN | CNTR_ODD, P }, 811 [PERF_COUNT_HW_INSTRUCTIONS] = { 0x01, CNTR_EVEN | CNTR_ODD, T }, 812 [PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = { 0x02, CNTR_EVEN, T }, 813 [PERF_COUNT_HW_BRANCH_MISSES] = { 0x02, CNTR_ODD, T }, 814 }; 815 816 /* 74K/proAptiv core has different branch event code. */ 817 static const struct mips_perf_event mipsxxcore_event_map2 818 [PERF_COUNT_HW_MAX] = { 819 [PERF_COUNT_HW_CPU_CYCLES] = { 0x00, CNTR_EVEN | CNTR_ODD, P }, 820 [PERF_COUNT_HW_INSTRUCTIONS] = { 0x01, CNTR_EVEN | CNTR_ODD, T }, 821 [PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = { 0x27, CNTR_EVEN, T }, 822 [PERF_COUNT_HW_BRANCH_MISSES] = { 0x27, CNTR_ODD, T }, 823 }; 824 825 static const struct mips_perf_event octeon_event_map[PERF_COUNT_HW_MAX] = { 826 [PERF_COUNT_HW_CPU_CYCLES] = { 0x01, CNTR_ALL }, 827 [PERF_COUNT_HW_INSTRUCTIONS] = { 0x03, CNTR_ALL }, 828 [PERF_COUNT_HW_CACHE_REFERENCES] = { 0x2b, CNTR_ALL }, 829 [PERF_COUNT_HW_CACHE_MISSES] = { 0x2e, CNTR_ALL }, 830 [PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = { 0x08, CNTR_ALL }, 831 [PERF_COUNT_HW_BRANCH_MISSES] = { 0x09, CNTR_ALL }, 832 [PERF_COUNT_HW_BUS_CYCLES] = { 0x25, CNTR_ALL }, 833 }; 834 835 static const struct mips_perf_event bmips5000_event_map 836 [PERF_COUNT_HW_MAX] = { 837 [PERF_COUNT_HW_CPU_CYCLES] = { 0x00, CNTR_EVEN | CNTR_ODD, T }, 838 [PERF_COUNT_HW_INSTRUCTIONS] = { 0x01, CNTR_EVEN | CNTR_ODD, T }, 839 [PERF_COUNT_HW_BRANCH_MISSES] = { 0x02, CNTR_ODD, T }, 840 }; 841 842 static const struct mips_perf_event xlp_event_map[PERF_COUNT_HW_MAX] = { 843 [PERF_COUNT_HW_CPU_CYCLES] = { 0x01, CNTR_ALL }, 844 [PERF_COUNT_HW_INSTRUCTIONS] = { 0x18, CNTR_ALL }, /* PAPI_TOT_INS */ 845 [PERF_COUNT_HW_CACHE_REFERENCES] = { 0x04, CNTR_ALL }, /* PAPI_L1_ICA */ 846 [PERF_COUNT_HW_CACHE_MISSES] = { 0x07, CNTR_ALL }, /* PAPI_L1_ICM */ 847 [PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = { 0x1b, CNTR_ALL }, /* PAPI_BR_CN */ 848 [PERF_COUNT_HW_BRANCH_MISSES] = { 0x1c, CNTR_ALL }, /* PAPI_BR_MSP */ 849 }; 850 851 /* 24K/34K/1004K/interAptiv/loongson1 cores share the same cache event map. */ 852 static const struct mips_perf_event mipsxxcore_cache_map 853 [PERF_COUNT_HW_CACHE_MAX] 854 [PERF_COUNT_HW_CACHE_OP_MAX] 855 [PERF_COUNT_HW_CACHE_RESULT_MAX] = { 856 [C(L1D)] = { 857 /* 858 * Like some other architectures (e.g. ARM), the performance 859 * counters don't differentiate between read and write 860 * accesses/misses, so this isn't strictly correct, but it's the 861 * best we can do. Writes and reads get combined. 862 */ 863 [C(OP_READ)] = { 864 [C(RESULT_ACCESS)] = { 0x0a, CNTR_EVEN, T }, 865 [C(RESULT_MISS)] = { 0x0b, CNTR_EVEN | CNTR_ODD, T }, 866 }, 867 [C(OP_WRITE)] = { 868 [C(RESULT_ACCESS)] = { 0x0a, CNTR_EVEN, T }, 869 [C(RESULT_MISS)] = { 0x0b, CNTR_EVEN | CNTR_ODD, T }, 870 }, 871 }, 872 [C(L1I)] = { 873 [C(OP_READ)] = { 874 [C(RESULT_ACCESS)] = { 0x09, CNTR_EVEN, T }, 875 [C(RESULT_MISS)] = { 0x09, CNTR_ODD, T }, 876 }, 877 [C(OP_WRITE)] = { 878 [C(RESULT_ACCESS)] = { 0x09, CNTR_EVEN, T }, 879 [C(RESULT_MISS)] = { 0x09, CNTR_ODD, T }, 880 }, 881 [C(OP_PREFETCH)] = { 882 [C(RESULT_ACCESS)] = { 0x14, CNTR_EVEN, T }, 883 /* 884 * Note that MIPS has only "hit" events countable for 885 * the prefetch operation. 886 */ 887 }, 888 }, 889 [C(LL)] = { 890 [C(OP_READ)] = { 891 [C(RESULT_ACCESS)] = { 0x15, CNTR_ODD, P }, 892 [C(RESULT_MISS)] = { 0x16, CNTR_EVEN, P }, 893 }, 894 [C(OP_WRITE)] = { 895 [C(RESULT_ACCESS)] = { 0x15, CNTR_ODD, P }, 896 [C(RESULT_MISS)] = { 0x16, CNTR_EVEN, P }, 897 }, 898 }, 899 [C(DTLB)] = { 900 [C(OP_READ)] = { 901 [C(RESULT_ACCESS)] = { 0x06, CNTR_EVEN, T }, 902 [C(RESULT_MISS)] = { 0x06, CNTR_ODD, T }, 903 }, 904 [C(OP_WRITE)] = { 905 [C(RESULT_ACCESS)] = { 0x06, CNTR_EVEN, T }, 906 [C(RESULT_MISS)] = { 0x06, CNTR_ODD, T }, 907 }, 908 }, 909 [C(ITLB)] = { 910 [C(OP_READ)] = { 911 [C(RESULT_ACCESS)] = { 0x05, CNTR_EVEN, T }, 912 [C(RESULT_MISS)] = { 0x05, CNTR_ODD, T }, 913 }, 914 [C(OP_WRITE)] = { 915 [C(RESULT_ACCESS)] = { 0x05, CNTR_EVEN, T }, 916 [C(RESULT_MISS)] = { 0x05, CNTR_ODD, T }, 917 }, 918 }, 919 [C(BPU)] = { 920 /* Using the same code for *HW_BRANCH* */ 921 [C(OP_READ)] = { 922 [C(RESULT_ACCESS)] = { 0x02, CNTR_EVEN, T }, 923 [C(RESULT_MISS)] = { 0x02, CNTR_ODD, T }, 924 }, 925 [C(OP_WRITE)] = { 926 [C(RESULT_ACCESS)] = { 0x02, CNTR_EVEN, T }, 927 [C(RESULT_MISS)] = { 0x02, CNTR_ODD, T }, 928 }, 929 }, 930 }; 931 932 /* 74K/proAptiv core has completely different cache event map. */ 933 static const struct mips_perf_event mipsxxcore_cache_map2 934 [PERF_COUNT_HW_CACHE_MAX] 935 [PERF_COUNT_HW_CACHE_OP_MAX] 936 [PERF_COUNT_HW_CACHE_RESULT_MAX] = { 937 [C(L1D)] = { 938 /* 939 * Like some other architectures (e.g. ARM), the performance 940 * counters don't differentiate between read and write 941 * accesses/misses, so this isn't strictly correct, but it's the 942 * best we can do. Writes and reads get combined. 943 */ 944 [C(OP_READ)] = { 945 [C(RESULT_ACCESS)] = { 0x17, CNTR_ODD, T }, 946 [C(RESULT_MISS)] = { 0x18, CNTR_ODD, T }, 947 }, 948 [C(OP_WRITE)] = { 949 [C(RESULT_ACCESS)] = { 0x17, CNTR_ODD, T }, 950 [C(RESULT_MISS)] = { 0x18, CNTR_ODD, T }, 951 }, 952 }, 953 [C(L1I)] = { 954 [C(OP_READ)] = { 955 [C(RESULT_ACCESS)] = { 0x06, CNTR_EVEN, T }, 956 [C(RESULT_MISS)] = { 0x06, CNTR_ODD, T }, 957 }, 958 [C(OP_WRITE)] = { 959 [C(RESULT_ACCESS)] = { 0x06, CNTR_EVEN, T }, 960 [C(RESULT_MISS)] = { 0x06, CNTR_ODD, T }, 961 }, 962 [C(OP_PREFETCH)] = { 963 [C(RESULT_ACCESS)] = { 0x34, CNTR_EVEN, T }, 964 /* 965 * Note that MIPS has only "hit" events countable for 966 * the prefetch operation. 967 */ 968 }, 969 }, 970 [C(LL)] = { 971 [C(OP_READ)] = { 972 [C(RESULT_ACCESS)] = { 0x1c, CNTR_ODD, P }, 973 [C(RESULT_MISS)] = { 0x1d, CNTR_EVEN, P }, 974 }, 975 [C(OP_WRITE)] = { 976 [C(RESULT_ACCESS)] = { 0x1c, CNTR_ODD, P }, 977 [C(RESULT_MISS)] = { 0x1d, CNTR_EVEN, P }, 978 }, 979 }, 980 /* 981 * 74K core does not have specific DTLB events. proAptiv core has 982 * "speculative" DTLB events which are numbered 0x63 (even/odd) and 983 * not included here. One can use raw events if really needed. 984 */ 985 [C(ITLB)] = { 986 [C(OP_READ)] = { 987 [C(RESULT_ACCESS)] = { 0x04, CNTR_EVEN, T }, 988 [C(RESULT_MISS)] = { 0x04, CNTR_ODD, T }, 989 }, 990 [C(OP_WRITE)] = { 991 [C(RESULT_ACCESS)] = { 0x04, CNTR_EVEN, T }, 992 [C(RESULT_MISS)] = { 0x04, CNTR_ODD, T }, 993 }, 994 }, 995 [C(BPU)] = { 996 /* Using the same code for *HW_BRANCH* */ 997 [C(OP_READ)] = { 998 [C(RESULT_ACCESS)] = { 0x27, CNTR_EVEN, T }, 999 [C(RESULT_MISS)] = { 0x27, CNTR_ODD, T }, 1000 }, 1001 [C(OP_WRITE)] = { 1002 [C(RESULT_ACCESS)] = { 0x27, CNTR_EVEN, T }, 1003 [C(RESULT_MISS)] = { 0x27, CNTR_ODD, T }, 1004 }, 1005 }, 1006 }; 1007 1008 /* BMIPS5000 */ 1009 static const struct mips_perf_event bmips5000_cache_map 1010 [PERF_COUNT_HW_CACHE_MAX] 1011 [PERF_COUNT_HW_CACHE_OP_MAX] 1012 [PERF_COUNT_HW_CACHE_RESULT_MAX] = { 1013 [C(L1D)] = { 1014 /* 1015 * Like some other architectures (e.g. ARM), the performance 1016 * counters don't differentiate between read and write 1017 * accesses/misses, so this isn't strictly correct, but it's the 1018 * best we can do. Writes and reads get combined. 1019 */ 1020 [C(OP_READ)] = { 1021 [C(RESULT_ACCESS)] = { 12, CNTR_EVEN, T }, 1022 [C(RESULT_MISS)] = { 12, CNTR_ODD, T }, 1023 }, 1024 [C(OP_WRITE)] = { 1025 [C(RESULT_ACCESS)] = { 12, CNTR_EVEN, T }, 1026 [C(RESULT_MISS)] = { 12, CNTR_ODD, T }, 1027 }, 1028 }, 1029 [C(L1I)] = { 1030 [C(OP_READ)] = { 1031 [C(RESULT_ACCESS)] = { 10, CNTR_EVEN, T }, 1032 [C(RESULT_MISS)] = { 10, CNTR_ODD, T }, 1033 }, 1034 [C(OP_WRITE)] = { 1035 [C(RESULT_ACCESS)] = { 10, CNTR_EVEN, T }, 1036 [C(RESULT_MISS)] = { 10, CNTR_ODD, T }, 1037 }, 1038 [C(OP_PREFETCH)] = { 1039 [C(RESULT_ACCESS)] = { 23, CNTR_EVEN, T }, 1040 /* 1041 * Note that MIPS has only "hit" events countable for 1042 * the prefetch operation. 1043 */ 1044 }, 1045 }, 1046 [C(LL)] = { 1047 [C(OP_READ)] = { 1048 [C(RESULT_ACCESS)] = { 28, CNTR_EVEN, P }, 1049 [C(RESULT_MISS)] = { 28, CNTR_ODD, P }, 1050 }, 1051 [C(OP_WRITE)] = { 1052 [C(RESULT_ACCESS)] = { 28, CNTR_EVEN, P }, 1053 [C(RESULT_MISS)] = { 28, CNTR_ODD, P }, 1054 }, 1055 }, 1056 [C(BPU)] = { 1057 /* Using the same code for *HW_BRANCH* */ 1058 [C(OP_READ)] = { 1059 [C(RESULT_MISS)] = { 0x02, CNTR_ODD, T }, 1060 }, 1061 [C(OP_WRITE)] = { 1062 [C(RESULT_MISS)] = { 0x02, CNTR_ODD, T }, 1063 }, 1064 }, 1065 }; 1066 1067 1068 static const struct mips_perf_event octeon_cache_map 1069 [PERF_COUNT_HW_CACHE_MAX] 1070 [PERF_COUNT_HW_CACHE_OP_MAX] 1071 [PERF_COUNT_HW_CACHE_RESULT_MAX] = { 1072 [C(L1D)] = { 1073 [C(OP_READ)] = { 1074 [C(RESULT_ACCESS)] = { 0x2b, CNTR_ALL }, 1075 [C(RESULT_MISS)] = { 0x2e, CNTR_ALL }, 1076 }, 1077 [C(OP_WRITE)] = { 1078 [C(RESULT_ACCESS)] = { 0x30, CNTR_ALL }, 1079 }, 1080 }, 1081 [C(L1I)] = { 1082 [C(OP_READ)] = { 1083 [C(RESULT_ACCESS)] = { 0x18, CNTR_ALL }, 1084 }, 1085 [C(OP_PREFETCH)] = { 1086 [C(RESULT_ACCESS)] = { 0x19, CNTR_ALL }, 1087 }, 1088 }, 1089 [C(DTLB)] = { 1090 /* 1091 * Only general DTLB misses are counted use the same event for 1092 * read and write. 1093 */ 1094 [C(OP_READ)] = { 1095 [C(RESULT_MISS)] = { 0x35, CNTR_ALL }, 1096 }, 1097 [C(OP_WRITE)] = { 1098 [C(RESULT_MISS)] = { 0x35, CNTR_ALL }, 1099 }, 1100 }, 1101 [C(ITLB)] = { 1102 [C(OP_READ)] = { 1103 [C(RESULT_MISS)] = { 0x37, CNTR_ALL }, 1104 }, 1105 }, 1106 }; 1107 1108 static const struct mips_perf_event xlp_cache_map 1109 [PERF_COUNT_HW_CACHE_MAX] 1110 [PERF_COUNT_HW_CACHE_OP_MAX] 1111 [PERF_COUNT_HW_CACHE_RESULT_MAX] = { 1112 [C(L1D)] = { 1113 [C(OP_READ)] = { 1114 [C(RESULT_ACCESS)] = { 0x31, CNTR_ALL }, /* PAPI_L1_DCR */ 1115 [C(RESULT_MISS)] = { 0x30, CNTR_ALL }, /* PAPI_L1_LDM */ 1116 }, 1117 [C(OP_WRITE)] = { 1118 [C(RESULT_ACCESS)] = { 0x2f, CNTR_ALL }, /* PAPI_L1_DCW */ 1119 [C(RESULT_MISS)] = { 0x2e, CNTR_ALL }, /* PAPI_L1_STM */ 1120 }, 1121 }, 1122 [C(L1I)] = { 1123 [C(OP_READ)] = { 1124 [C(RESULT_ACCESS)] = { 0x04, CNTR_ALL }, /* PAPI_L1_ICA */ 1125 [C(RESULT_MISS)] = { 0x07, CNTR_ALL }, /* PAPI_L1_ICM */ 1126 }, 1127 }, 1128 [C(LL)] = { 1129 [C(OP_READ)] = { 1130 [C(RESULT_ACCESS)] = { 0x35, CNTR_ALL }, /* PAPI_L2_DCR */ 1131 [C(RESULT_MISS)] = { 0x37, CNTR_ALL }, /* PAPI_L2_LDM */ 1132 }, 1133 [C(OP_WRITE)] = { 1134 [C(RESULT_ACCESS)] = { 0x34, CNTR_ALL }, /* PAPI_L2_DCA */ 1135 [C(RESULT_MISS)] = { 0x36, CNTR_ALL }, /* PAPI_L2_DCM */ 1136 }, 1137 }, 1138 [C(DTLB)] = { 1139 /* 1140 * Only general DTLB misses are counted use the same event for 1141 * read and write. 1142 */ 1143 [C(OP_READ)] = { 1144 [C(RESULT_MISS)] = { 0x2d, CNTR_ALL }, /* PAPI_TLB_DM */ 1145 }, 1146 [C(OP_WRITE)] = { 1147 [C(RESULT_MISS)] = { 0x2d, CNTR_ALL }, /* PAPI_TLB_DM */ 1148 }, 1149 }, 1150 [C(ITLB)] = { 1151 [C(OP_READ)] = { 1152 [C(RESULT_MISS)] = { 0x08, CNTR_ALL }, /* PAPI_TLB_IM */ 1153 }, 1154 [C(OP_WRITE)] = { 1155 [C(RESULT_MISS)] = { 0x08, CNTR_ALL }, /* PAPI_TLB_IM */ 1156 }, 1157 }, 1158 [C(BPU)] = { 1159 [C(OP_READ)] = { 1160 [C(RESULT_MISS)] = { 0x25, CNTR_ALL }, 1161 }, 1162 }, 1163 }; 1164 1165 #ifdef CONFIG_MIPS_MT_SMP 1166 static void check_and_calc_range(struct perf_event *event, 1167 const struct mips_perf_event *pev) 1168 { 1169 struct hw_perf_event *hwc = &event->hw; 1170 1171 if (event->cpu >= 0) { 1172 if (pev->range > V) { 1173 /* 1174 * The user selected an event that is processor 1175 * wide, while expecting it to be VPE wide. 1176 */ 1177 hwc->config_base |= M_TC_EN_ALL; 1178 } else { 1179 /* 1180 * FIXME: cpu_data[event->cpu].vpe_id reports 0 1181 * for both CPUs. 1182 */ 1183 hwc->config_base |= M_PERFCTL_VPEID(event->cpu); 1184 hwc->config_base |= M_TC_EN_VPE; 1185 } 1186 } else 1187 hwc->config_base |= M_TC_EN_ALL; 1188 } 1189 #else 1190 static void check_and_calc_range(struct perf_event *event, 1191 const struct mips_perf_event *pev) 1192 { 1193 } 1194 #endif 1195 1196 static int __hw_perf_event_init(struct perf_event *event) 1197 { 1198 struct perf_event_attr *attr = &event->attr; 1199 struct hw_perf_event *hwc = &event->hw; 1200 const struct mips_perf_event *pev; 1201 int err; 1202 1203 /* Returning MIPS event descriptor for generic perf event. */ 1204 if (PERF_TYPE_HARDWARE == event->attr.type) { 1205 if (event->attr.config >= PERF_COUNT_HW_MAX) 1206 return -EINVAL; 1207 pev = mipspmu_map_general_event(event->attr.config); 1208 } else if (PERF_TYPE_HW_CACHE == event->attr.type) { 1209 pev = mipspmu_map_cache_event(event->attr.config); 1210 } else if (PERF_TYPE_RAW == event->attr.type) { 1211 /* We are working on the global raw event. */ 1212 mutex_lock(&raw_event_mutex); 1213 pev = mipspmu.map_raw_event(event->attr.config); 1214 } else { 1215 /* The event type is not (yet) supported. */ 1216 return -EOPNOTSUPP; 1217 } 1218 1219 if (IS_ERR(pev)) { 1220 if (PERF_TYPE_RAW == event->attr.type) 1221 mutex_unlock(&raw_event_mutex); 1222 return PTR_ERR(pev); 1223 } 1224 1225 /* 1226 * We allow max flexibility on how each individual counter shared 1227 * by the single CPU operates (the mode exclusion and the range). 1228 */ 1229 hwc->config_base = M_PERFCTL_INTERRUPT_ENABLE; 1230 1231 /* Calculate range bits and validate it. */ 1232 if (num_possible_cpus() > 1) 1233 check_and_calc_range(event, pev); 1234 1235 hwc->event_base = mipspmu_perf_event_encode(pev); 1236 if (PERF_TYPE_RAW == event->attr.type) 1237 mutex_unlock(&raw_event_mutex); 1238 1239 if (!attr->exclude_user) 1240 hwc->config_base |= M_PERFCTL_USER; 1241 if (!attr->exclude_kernel) { 1242 hwc->config_base |= M_PERFCTL_KERNEL; 1243 /* MIPS kernel mode: KSU == 00b || EXL == 1 || ERL == 1 */ 1244 hwc->config_base |= M_PERFCTL_EXL; 1245 } 1246 if (!attr->exclude_hv) 1247 hwc->config_base |= M_PERFCTL_SUPERVISOR; 1248 1249 hwc->config_base &= M_PERFCTL_CONFIG_MASK; 1250 /* 1251 * The event can belong to another cpu. We do not assign a local 1252 * counter for it for now. 1253 */ 1254 hwc->idx = -1; 1255 hwc->config = 0; 1256 1257 if (!hwc->sample_period) { 1258 hwc->sample_period = mipspmu.max_period; 1259 hwc->last_period = hwc->sample_period; 1260 local64_set(&hwc->period_left, hwc->sample_period); 1261 } 1262 1263 err = 0; 1264 if (event->group_leader != event) 1265 err = validate_group(event); 1266 1267 event->destroy = hw_perf_event_destroy; 1268 1269 if (err) 1270 event->destroy(event); 1271 1272 return err; 1273 } 1274 1275 static void pause_local_counters(void) 1276 { 1277 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); 1278 int ctr = mipspmu.num_counters; 1279 unsigned long flags; 1280 1281 local_irq_save(flags); 1282 do { 1283 ctr--; 1284 cpuc->saved_ctrl[ctr] = mipsxx_pmu_read_control(ctr); 1285 mipsxx_pmu_write_control(ctr, cpuc->saved_ctrl[ctr] & 1286 ~M_PERFCTL_COUNT_EVENT_WHENEVER); 1287 } while (ctr > 0); 1288 local_irq_restore(flags); 1289 } 1290 1291 static void resume_local_counters(void) 1292 { 1293 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); 1294 int ctr = mipspmu.num_counters; 1295 1296 do { 1297 ctr--; 1298 mipsxx_pmu_write_control(ctr, cpuc->saved_ctrl[ctr]); 1299 } while (ctr > 0); 1300 } 1301 1302 static int mipsxx_pmu_handle_shared_irq(void) 1303 { 1304 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); 1305 struct perf_sample_data data; 1306 unsigned int counters = mipspmu.num_counters; 1307 u64 counter; 1308 int handled = IRQ_NONE; 1309 struct pt_regs *regs; 1310 1311 if (cpu_has_perf_cntr_intr_bit && !(read_c0_cause() & CAUSEF_PCI)) 1312 return handled; 1313 /* 1314 * First we pause the local counters, so that when we are locked 1315 * here, the counters are all paused. When it gets locked due to 1316 * perf_disable(), the timer interrupt handler will be delayed. 1317 * 1318 * See also mipsxx_pmu_start(). 1319 */ 1320 pause_local_counters(); 1321 #ifdef CONFIG_MIPS_PERF_SHARED_TC_COUNTERS 1322 read_lock(&pmuint_rwlock); 1323 #endif 1324 1325 regs = get_irq_regs(); 1326 1327 perf_sample_data_init(&data, 0, 0); 1328 1329 switch (counters) { 1330 #define HANDLE_COUNTER(n) \ 1331 case n + 1: \ 1332 if (test_bit(n, cpuc->used_mask)) { \ 1333 counter = mipspmu.read_counter(n); \ 1334 if (counter & mipspmu.overflow) { \ 1335 handle_associated_event(cpuc, n, &data, regs); \ 1336 handled = IRQ_HANDLED; \ 1337 } \ 1338 } 1339 HANDLE_COUNTER(3) 1340 HANDLE_COUNTER(2) 1341 HANDLE_COUNTER(1) 1342 HANDLE_COUNTER(0) 1343 } 1344 1345 /* 1346 * Do all the work for the pending perf events. We can do this 1347 * in here because the performance counter interrupt is a regular 1348 * interrupt, not NMI. 1349 */ 1350 if (handled == IRQ_HANDLED) 1351 irq_work_run(); 1352 1353 #ifdef CONFIG_MIPS_PERF_SHARED_TC_COUNTERS 1354 read_unlock(&pmuint_rwlock); 1355 #endif 1356 resume_local_counters(); 1357 return handled; 1358 } 1359 1360 static irqreturn_t mipsxx_pmu_handle_irq(int irq, void *dev) 1361 { 1362 return mipsxx_pmu_handle_shared_irq(); 1363 } 1364 1365 /* 24K */ 1366 #define IS_BOTH_COUNTERS_24K_EVENT(b) \ 1367 ((b) == 0 || (b) == 1 || (b) == 11) 1368 1369 /* 34K */ 1370 #define IS_BOTH_COUNTERS_34K_EVENT(b) \ 1371 ((b) == 0 || (b) == 1 || (b) == 11) 1372 #ifdef CONFIG_MIPS_MT_SMP 1373 #define IS_RANGE_P_34K_EVENT(r, b) \ 1374 ((b) == 0 || (r) == 18 || (b) == 21 || (b) == 22 || \ 1375 (b) == 25 || (b) == 39 || (r) == 44 || (r) == 174 || \ 1376 (r) == 176 || ((b) >= 50 && (b) <= 55) || \ 1377 ((b) >= 64 && (b) <= 67)) 1378 #define IS_RANGE_V_34K_EVENT(r) ((r) == 47) 1379 #endif 1380 1381 /* 74K */ 1382 #define IS_BOTH_COUNTERS_74K_EVENT(b) \ 1383 ((b) == 0 || (b) == 1) 1384 1385 /* proAptiv */ 1386 #define IS_BOTH_COUNTERS_PROAPTIV_EVENT(b) \ 1387 ((b) == 0 || (b) == 1) 1388 /* P5600 */ 1389 #define IS_BOTH_COUNTERS_P5600_EVENT(b) \ 1390 ((b) == 0 || (b) == 1) 1391 1392 /* 1004K */ 1393 #define IS_BOTH_COUNTERS_1004K_EVENT(b) \ 1394 ((b) == 0 || (b) == 1 || (b) == 11) 1395 #ifdef CONFIG_MIPS_MT_SMP 1396 #define IS_RANGE_P_1004K_EVENT(r, b) \ 1397 ((b) == 0 || (r) == 18 || (b) == 21 || (b) == 22 || \ 1398 (b) == 25 || (b) == 36 || (b) == 39 || (r) == 44 || \ 1399 (r) == 174 || (r) == 176 || ((b) >= 50 && (b) <= 59) || \ 1400 (r) == 188 || (b) == 61 || (b) == 62 || \ 1401 ((b) >= 64 && (b) <= 67)) 1402 #define IS_RANGE_V_1004K_EVENT(r) ((r) == 47) 1403 #endif 1404 1405 /* interAptiv */ 1406 #define IS_BOTH_COUNTERS_INTERAPTIV_EVENT(b) \ 1407 ((b) == 0 || (b) == 1 || (b) == 11) 1408 #ifdef CONFIG_MIPS_MT_SMP 1409 /* The P/V/T info is not provided for "(b) == 38" in SUM, assume P. */ 1410 #define IS_RANGE_P_INTERAPTIV_EVENT(r, b) \ 1411 ((b) == 0 || (r) == 18 || (b) == 21 || (b) == 22 || \ 1412 (b) == 25 || (b) == 36 || (b) == 38 || (b) == 39 || \ 1413 (r) == 44 || (r) == 174 || (r) == 176 || ((b) >= 50 && \ 1414 (b) <= 59) || (r) == 188 || (b) == 61 || (b) == 62 || \ 1415 ((b) >= 64 && (b) <= 67)) 1416 #define IS_RANGE_V_INTERAPTIV_EVENT(r) ((r) == 47 || (r) == 175) 1417 #endif 1418 1419 /* BMIPS5000 */ 1420 #define IS_BOTH_COUNTERS_BMIPS5000_EVENT(b) \ 1421 ((b) == 0 || (b) == 1) 1422 1423 1424 /* 1425 * For most cores the user can use 0-255 raw events, where 0-127 for the events 1426 * of even counters, and 128-255 for odd counters. Note that bit 7 is used to 1427 * indicate the even/odd bank selector. So, for example, when user wants to take 1428 * the Event Num of 15 for odd counters (by referring to the user manual), then 1429 * 128 needs to be added to 15 as the input for the event config, i.e., 143 (0x8F) 1430 * to be used. 1431 * 1432 * Some newer cores have even more events, in which case the user can use raw 1433 * events 0-511, where 0-255 are for the events of even counters, and 256-511 1434 * are for odd counters, so bit 8 is used to indicate the even/odd bank selector. 1435 */ 1436 static const struct mips_perf_event *mipsxx_pmu_map_raw_event(u64 config) 1437 { 1438 /* currently most cores have 7-bit event numbers */ 1439 unsigned int raw_id = config & 0xff; 1440 unsigned int base_id = raw_id & 0x7f; 1441 1442 switch (current_cpu_type()) { 1443 case CPU_24K: 1444 if (IS_BOTH_COUNTERS_24K_EVENT(base_id)) 1445 raw_event.cntr_mask = CNTR_EVEN | CNTR_ODD; 1446 else 1447 raw_event.cntr_mask = 1448 raw_id > 127 ? CNTR_ODD : CNTR_EVEN; 1449 #ifdef CONFIG_MIPS_MT_SMP 1450 /* 1451 * This is actually doing nothing. Non-multithreading 1452 * CPUs will not check and calculate the range. 1453 */ 1454 raw_event.range = P; 1455 #endif 1456 break; 1457 case CPU_34K: 1458 if (IS_BOTH_COUNTERS_34K_EVENT(base_id)) 1459 raw_event.cntr_mask = CNTR_EVEN | CNTR_ODD; 1460 else 1461 raw_event.cntr_mask = 1462 raw_id > 127 ? CNTR_ODD : CNTR_EVEN; 1463 #ifdef CONFIG_MIPS_MT_SMP 1464 if (IS_RANGE_P_34K_EVENT(raw_id, base_id)) 1465 raw_event.range = P; 1466 else if (unlikely(IS_RANGE_V_34K_EVENT(raw_id))) 1467 raw_event.range = V; 1468 else 1469 raw_event.range = T; 1470 #endif 1471 break; 1472 case CPU_74K: 1473 case CPU_1074K: 1474 if (IS_BOTH_COUNTERS_74K_EVENT(base_id)) 1475 raw_event.cntr_mask = CNTR_EVEN | CNTR_ODD; 1476 else 1477 raw_event.cntr_mask = 1478 raw_id > 127 ? CNTR_ODD : CNTR_EVEN; 1479 #ifdef CONFIG_MIPS_MT_SMP 1480 raw_event.range = P; 1481 #endif 1482 break; 1483 case CPU_PROAPTIV: 1484 if (IS_BOTH_COUNTERS_PROAPTIV_EVENT(base_id)) 1485 raw_event.cntr_mask = CNTR_EVEN | CNTR_ODD; 1486 else 1487 raw_event.cntr_mask = 1488 raw_id > 127 ? CNTR_ODD : CNTR_EVEN; 1489 #ifdef CONFIG_MIPS_MT_SMP 1490 raw_event.range = P; 1491 #endif 1492 break; 1493 case CPU_P5600: 1494 /* 8-bit event numbers */ 1495 raw_id = config & 0x1ff; 1496 base_id = raw_id & 0xff; 1497 if (IS_BOTH_COUNTERS_P5600_EVENT(base_id)) 1498 raw_event.cntr_mask = CNTR_EVEN | CNTR_ODD; 1499 else 1500 raw_event.cntr_mask = 1501 raw_id > 255 ? CNTR_ODD : CNTR_EVEN; 1502 #ifdef CONFIG_MIPS_MT_SMP 1503 raw_event.range = P; 1504 #endif 1505 break; 1506 case CPU_1004K: 1507 if (IS_BOTH_COUNTERS_1004K_EVENT(base_id)) 1508 raw_event.cntr_mask = CNTR_EVEN | CNTR_ODD; 1509 else 1510 raw_event.cntr_mask = 1511 raw_id > 127 ? CNTR_ODD : CNTR_EVEN; 1512 #ifdef CONFIG_MIPS_MT_SMP 1513 if (IS_RANGE_P_1004K_EVENT(raw_id, base_id)) 1514 raw_event.range = P; 1515 else if (unlikely(IS_RANGE_V_1004K_EVENT(raw_id))) 1516 raw_event.range = V; 1517 else 1518 raw_event.range = T; 1519 #endif 1520 break; 1521 case CPU_INTERAPTIV: 1522 if (IS_BOTH_COUNTERS_INTERAPTIV_EVENT(base_id)) 1523 raw_event.cntr_mask = CNTR_EVEN | CNTR_ODD; 1524 else 1525 raw_event.cntr_mask = 1526 raw_id > 127 ? CNTR_ODD : CNTR_EVEN; 1527 #ifdef CONFIG_MIPS_MT_SMP 1528 if (IS_RANGE_P_INTERAPTIV_EVENT(raw_id, base_id)) 1529 raw_event.range = P; 1530 else if (unlikely(IS_RANGE_V_INTERAPTIV_EVENT(raw_id))) 1531 raw_event.range = V; 1532 else 1533 raw_event.range = T; 1534 #endif 1535 break; 1536 case CPU_BMIPS5000: 1537 if (IS_BOTH_COUNTERS_BMIPS5000_EVENT(base_id)) 1538 raw_event.cntr_mask = CNTR_EVEN | CNTR_ODD; 1539 else 1540 raw_event.cntr_mask = 1541 raw_id > 127 ? CNTR_ODD : CNTR_EVEN; 1542 } 1543 1544 raw_event.event_id = base_id; 1545 1546 return &raw_event; 1547 } 1548 1549 static const struct mips_perf_event *octeon_pmu_map_raw_event(u64 config) 1550 { 1551 unsigned int raw_id = config & 0xff; 1552 unsigned int base_id = raw_id & 0x7f; 1553 1554 1555 raw_event.cntr_mask = CNTR_ALL; 1556 raw_event.event_id = base_id; 1557 1558 if (current_cpu_type() == CPU_CAVIUM_OCTEON2) { 1559 if (base_id > 0x42) 1560 return ERR_PTR(-EOPNOTSUPP); 1561 } else { 1562 if (base_id > 0x3a) 1563 return ERR_PTR(-EOPNOTSUPP); 1564 } 1565 1566 switch (base_id) { 1567 case 0x00: 1568 case 0x0f: 1569 case 0x1e: 1570 case 0x1f: 1571 case 0x2f: 1572 case 0x34: 1573 case 0x3b ... 0x3f: 1574 return ERR_PTR(-EOPNOTSUPP); 1575 default: 1576 break; 1577 } 1578 1579 return &raw_event; 1580 } 1581 1582 static const struct mips_perf_event *xlp_pmu_map_raw_event(u64 config) 1583 { 1584 unsigned int raw_id = config & 0xff; 1585 1586 /* Only 1-63 are defined */ 1587 if ((raw_id < 0x01) || (raw_id > 0x3f)) 1588 return ERR_PTR(-EOPNOTSUPP); 1589 1590 raw_event.cntr_mask = CNTR_ALL; 1591 raw_event.event_id = raw_id; 1592 1593 return &raw_event; 1594 } 1595 1596 static int __init 1597 init_hw_perf_events(void) 1598 { 1599 int counters, irq; 1600 int counter_bits; 1601 1602 pr_info("Performance counters: "); 1603 1604 counters = n_counters(); 1605 if (counters == 0) { 1606 pr_cont("No available PMU.\n"); 1607 return -ENODEV; 1608 } 1609 1610 #ifdef CONFIG_MIPS_PERF_SHARED_TC_COUNTERS 1611 cpu_has_mipsmt_pertccounters = read_c0_config7() & (1<<19); 1612 if (!cpu_has_mipsmt_pertccounters) 1613 counters = counters_total_to_per_cpu(counters); 1614 #endif 1615 1616 if (get_c0_perfcount_int) 1617 irq = get_c0_perfcount_int(); 1618 else if ((cp0_perfcount_irq >= 0) && 1619 (cp0_compare_irq != cp0_perfcount_irq)) 1620 irq = MIPS_CPU_IRQ_BASE + cp0_perfcount_irq; 1621 else 1622 irq = -1; 1623 1624 mipspmu.map_raw_event = mipsxx_pmu_map_raw_event; 1625 1626 switch (current_cpu_type()) { 1627 case CPU_24K: 1628 mipspmu.name = "mips/24K"; 1629 mipspmu.general_event_map = &mipsxxcore_event_map; 1630 mipspmu.cache_event_map = &mipsxxcore_cache_map; 1631 break; 1632 case CPU_34K: 1633 mipspmu.name = "mips/34K"; 1634 mipspmu.general_event_map = &mipsxxcore_event_map; 1635 mipspmu.cache_event_map = &mipsxxcore_cache_map; 1636 break; 1637 case CPU_74K: 1638 mipspmu.name = "mips/74K"; 1639 mipspmu.general_event_map = &mipsxxcore_event_map2; 1640 mipspmu.cache_event_map = &mipsxxcore_cache_map2; 1641 break; 1642 case CPU_PROAPTIV: 1643 mipspmu.name = "mips/proAptiv"; 1644 mipspmu.general_event_map = &mipsxxcore_event_map2; 1645 mipspmu.cache_event_map = &mipsxxcore_cache_map2; 1646 break; 1647 case CPU_P5600: 1648 mipspmu.name = "mips/P5600"; 1649 mipspmu.general_event_map = &mipsxxcore_event_map2; 1650 mipspmu.cache_event_map = &mipsxxcore_cache_map2; 1651 break; 1652 case CPU_1004K: 1653 mipspmu.name = "mips/1004K"; 1654 mipspmu.general_event_map = &mipsxxcore_event_map; 1655 mipspmu.cache_event_map = &mipsxxcore_cache_map; 1656 break; 1657 case CPU_1074K: 1658 mipspmu.name = "mips/1074K"; 1659 mipspmu.general_event_map = &mipsxxcore_event_map; 1660 mipspmu.cache_event_map = &mipsxxcore_cache_map; 1661 break; 1662 case CPU_INTERAPTIV: 1663 mipspmu.name = "mips/interAptiv"; 1664 mipspmu.general_event_map = &mipsxxcore_event_map; 1665 mipspmu.cache_event_map = &mipsxxcore_cache_map; 1666 break; 1667 case CPU_LOONGSON1: 1668 mipspmu.name = "mips/loongson1"; 1669 mipspmu.general_event_map = &mipsxxcore_event_map; 1670 mipspmu.cache_event_map = &mipsxxcore_cache_map; 1671 break; 1672 case CPU_CAVIUM_OCTEON: 1673 case CPU_CAVIUM_OCTEON_PLUS: 1674 case CPU_CAVIUM_OCTEON2: 1675 mipspmu.name = "octeon"; 1676 mipspmu.general_event_map = &octeon_event_map; 1677 mipspmu.cache_event_map = &octeon_cache_map; 1678 mipspmu.map_raw_event = octeon_pmu_map_raw_event; 1679 break; 1680 case CPU_BMIPS5000: 1681 mipspmu.name = "BMIPS5000"; 1682 mipspmu.general_event_map = &bmips5000_event_map; 1683 mipspmu.cache_event_map = &bmips5000_cache_map; 1684 break; 1685 case CPU_XLP: 1686 mipspmu.name = "xlp"; 1687 mipspmu.general_event_map = &xlp_event_map; 1688 mipspmu.cache_event_map = &xlp_cache_map; 1689 mipspmu.map_raw_event = xlp_pmu_map_raw_event; 1690 break; 1691 default: 1692 pr_cont("Either hardware does not support performance " 1693 "counters, or not yet implemented.\n"); 1694 return -ENODEV; 1695 } 1696 1697 mipspmu.num_counters = counters; 1698 mipspmu.irq = irq; 1699 1700 if (read_c0_perfctrl0() & M_PERFCTL_WIDE) { 1701 mipspmu.max_period = (1ULL << 63) - 1; 1702 mipspmu.valid_count = (1ULL << 63) - 1; 1703 mipspmu.overflow = 1ULL << 63; 1704 mipspmu.read_counter = mipsxx_pmu_read_counter_64; 1705 mipspmu.write_counter = mipsxx_pmu_write_counter_64; 1706 counter_bits = 64; 1707 } else { 1708 mipspmu.max_period = (1ULL << 31) - 1; 1709 mipspmu.valid_count = (1ULL << 31) - 1; 1710 mipspmu.overflow = 1ULL << 31; 1711 mipspmu.read_counter = mipsxx_pmu_read_counter; 1712 mipspmu.write_counter = mipsxx_pmu_write_counter; 1713 counter_bits = 32; 1714 } 1715 1716 on_each_cpu(reset_counters, (void *)(long)counters, 1); 1717 1718 pr_cont("%s PMU enabled, %d %d-bit counters available to each " 1719 "CPU, irq %d%s\n", mipspmu.name, counters, counter_bits, irq, 1720 irq < 0 ? " (share with timer interrupt)" : ""); 1721 1722 perf_pmu_register(&pmu, "cpu", PERF_TYPE_RAW); 1723 1724 return 0; 1725 } 1726 early_initcall(init_hw_perf_events); 1727