1 /* 2 * This file is subject to the terms and conditions of the GNU General Public 3 * License. See the file "COPYING" in the main directory of this archive 4 * for more details. 5 * 6 * Copyright (c) 2014 Imagination Technologies Ltd. 7 * Author: Leonid Yegoshin <Leonid.Yegoshin@imgtec.com> 8 * Author: Markos Chandras <markos.chandras@imgtec.com> 9 * 10 * MIPS R2 user space instruction emulator for MIPS R6 11 * 12 */ 13 #include <linux/bug.h> 14 #include <linux/compiler.h> 15 #include <linux/debugfs.h> 16 #include <linux/init.h> 17 #include <linux/kernel.h> 18 #include <linux/module.h> 19 #include <linux/ptrace.h> 20 #include <linux/seq_file.h> 21 22 #include <asm/asm.h> 23 #include <asm/branch.h> 24 #include <asm/break.h> 25 #include <asm/fpu.h> 26 #include <asm/fpu_emulator.h> 27 #include <asm/inst.h> 28 #include <asm/mips-r2-to-r6-emul.h> 29 #include <asm/local.h> 30 #include <asm/ptrace.h> 31 #include <asm/uaccess.h> 32 33 #ifdef CONFIG_64BIT 34 #define ADDIU "daddiu " 35 #define INS "dins " 36 #define EXT "dext " 37 #else 38 #define ADDIU "addiu " 39 #define INS "ins " 40 #define EXT "ext " 41 #endif /* CONFIG_64BIT */ 42 43 #define SB "sb " 44 #define LB "lb " 45 #define LL "ll " 46 #define SC "sc " 47 48 DEFINE_PER_CPU(struct mips_r2_emulator_stats, mipsr2emustats); 49 DEFINE_PER_CPU(struct mips_r2_emulator_stats, mipsr2bdemustats); 50 DEFINE_PER_CPU(struct mips_r2br_emulator_stats, mipsr2bremustats); 51 52 extern const unsigned int fpucondbit[8]; 53 54 #define MIPS_R2_EMUL_TOTAL_PASS 10 55 56 int mipsr2_emulation = 0; 57 58 static int __init mipsr2emu_enable(char *s) 59 { 60 mipsr2_emulation = 1; 61 62 pr_info("MIPS R2-to-R6 Emulator Enabled!"); 63 64 return 1; 65 } 66 __setup("mipsr2emu", mipsr2emu_enable); 67 68 /** 69 * mipsr6_emul - Emulate some frequent R2/R5/R6 instructions in delay slot 70 * for performance instead of the traditional way of using a stack trampoline 71 * which is rather slow. 72 * @regs: Process register set 73 * @ir: Instruction 74 */ 75 static inline int mipsr6_emul(struct pt_regs *regs, u32 ir) 76 { 77 switch (MIPSInst_OPCODE(ir)) { 78 case addiu_op: 79 if (MIPSInst_RT(ir)) 80 regs->regs[MIPSInst_RT(ir)] = 81 (s32)regs->regs[MIPSInst_RS(ir)] + 82 (s32)MIPSInst_SIMM(ir); 83 return 0; 84 case daddiu_op: 85 if (config_enabled(CONFIG_32BIT)) 86 break; 87 88 if (MIPSInst_RT(ir)) 89 regs->regs[MIPSInst_RT(ir)] = 90 (s64)regs->regs[MIPSInst_RS(ir)] + 91 (s64)MIPSInst_SIMM(ir); 92 return 0; 93 case lwc1_op: 94 case swc1_op: 95 case cop1_op: 96 case cop1x_op: 97 /* FPU instructions in delay slot */ 98 return -SIGFPE; 99 case spec_op: 100 switch (MIPSInst_FUNC(ir)) { 101 case or_op: 102 if (MIPSInst_RD(ir)) 103 regs->regs[MIPSInst_RD(ir)] = 104 regs->regs[MIPSInst_RS(ir)] | 105 regs->regs[MIPSInst_RT(ir)]; 106 return 0; 107 case sll_op: 108 if (MIPSInst_RS(ir)) 109 break; 110 111 if (MIPSInst_RD(ir)) 112 regs->regs[MIPSInst_RD(ir)] = 113 (s32)(((u32)regs->regs[MIPSInst_RT(ir)]) << 114 MIPSInst_FD(ir)); 115 return 0; 116 case srl_op: 117 if (MIPSInst_RS(ir)) 118 break; 119 120 if (MIPSInst_RD(ir)) 121 regs->regs[MIPSInst_RD(ir)] = 122 (s32)(((u32)regs->regs[MIPSInst_RT(ir)]) >> 123 MIPSInst_FD(ir)); 124 return 0; 125 case addu_op: 126 if (MIPSInst_FD(ir)) 127 break; 128 129 if (MIPSInst_RD(ir)) 130 regs->regs[MIPSInst_RD(ir)] = 131 (s32)((u32)regs->regs[MIPSInst_RS(ir)] + 132 (u32)regs->regs[MIPSInst_RT(ir)]); 133 return 0; 134 case subu_op: 135 if (MIPSInst_FD(ir)) 136 break; 137 138 if (MIPSInst_RD(ir)) 139 regs->regs[MIPSInst_RD(ir)] = 140 (s32)((u32)regs->regs[MIPSInst_RS(ir)] - 141 (u32)regs->regs[MIPSInst_RT(ir)]); 142 return 0; 143 case dsll_op: 144 if (config_enabled(CONFIG_32BIT) || MIPSInst_RS(ir)) 145 break; 146 147 if (MIPSInst_RD(ir)) 148 regs->regs[MIPSInst_RD(ir)] = 149 (s64)(((u64)regs->regs[MIPSInst_RT(ir)]) << 150 MIPSInst_FD(ir)); 151 return 0; 152 case dsrl_op: 153 if (config_enabled(CONFIG_32BIT) || MIPSInst_RS(ir)) 154 break; 155 156 if (MIPSInst_RD(ir)) 157 regs->regs[MIPSInst_RD(ir)] = 158 (s64)(((u64)regs->regs[MIPSInst_RT(ir)]) >> 159 MIPSInst_FD(ir)); 160 return 0; 161 case daddu_op: 162 if (config_enabled(CONFIG_32BIT) || MIPSInst_FD(ir)) 163 break; 164 165 if (MIPSInst_RD(ir)) 166 regs->regs[MIPSInst_RD(ir)] = 167 (u64)regs->regs[MIPSInst_RS(ir)] + 168 (u64)regs->regs[MIPSInst_RT(ir)]; 169 return 0; 170 case dsubu_op: 171 if (config_enabled(CONFIG_32BIT) || MIPSInst_FD(ir)) 172 break; 173 174 if (MIPSInst_RD(ir)) 175 regs->regs[MIPSInst_RD(ir)] = 176 (s64)((u64)regs->regs[MIPSInst_RS(ir)] - 177 (u64)regs->regs[MIPSInst_RT(ir)]); 178 return 0; 179 } 180 break; 181 default: 182 pr_debug("No fastpath BD emulation for instruction 0x%08x (op: %02x)\n", 183 ir, MIPSInst_OPCODE(ir)); 184 } 185 186 return SIGILL; 187 } 188 189 /** 190 * movt_func - Emulate a MOVT instruction 191 * @regs: Process register set 192 * @ir: Instruction 193 * 194 * Returns 0 since it always succeeds. 195 */ 196 static int movf_func(struct pt_regs *regs, u32 ir) 197 { 198 u32 csr; 199 u32 cond; 200 201 csr = current->thread.fpu.fcr31; 202 cond = fpucondbit[MIPSInst_RT(ir) >> 2]; 203 if (((csr & cond) == 0) && MIPSInst_RD(ir)) 204 regs->regs[MIPSInst_RD(ir)] = regs->regs[MIPSInst_RS(ir)]; 205 MIPS_R2_STATS(movs); 206 return 0; 207 } 208 209 /** 210 * movt_func - Emulate a MOVT instruction 211 * @regs: Process register set 212 * @ir: Instruction 213 * 214 * Returns 0 since it always succeeds. 215 */ 216 static int movt_func(struct pt_regs *regs, u32 ir) 217 { 218 u32 csr; 219 u32 cond; 220 221 csr = current->thread.fpu.fcr31; 222 cond = fpucondbit[MIPSInst_RT(ir) >> 2]; 223 224 if (((csr & cond) != 0) && MIPSInst_RD(ir)) 225 regs->regs[MIPSInst_RD(ir)] = regs->regs[MIPSInst_RS(ir)]; 226 227 MIPS_R2_STATS(movs); 228 229 return 0; 230 } 231 232 /** 233 * jr_func - Emulate a JR instruction. 234 * @pt_regs: Process register set 235 * @ir: Instruction 236 * 237 * Returns SIGILL if JR was in delay slot, SIGEMT if we 238 * can't compute the EPC, SIGSEGV if we can't access the 239 * userland instruction or 0 on success. 240 */ 241 static int jr_func(struct pt_regs *regs, u32 ir) 242 { 243 int err; 244 unsigned long cepc, epc, nepc; 245 u32 nir; 246 247 if (delay_slot(regs)) 248 return SIGILL; 249 250 /* EPC after the RI/JR instruction */ 251 nepc = regs->cp0_epc; 252 /* Roll back to the reserved R2 JR instruction */ 253 regs->cp0_epc -= 4; 254 epc = regs->cp0_epc; 255 err = __compute_return_epc(regs); 256 257 if (err < 0) 258 return SIGEMT; 259 260 261 /* Computed EPC */ 262 cepc = regs->cp0_epc; 263 264 /* Get DS instruction */ 265 err = __get_user(nir, (u32 __user *)nepc); 266 if (err) 267 return SIGSEGV; 268 269 MIPS_R2BR_STATS(jrs); 270 271 /* If nir == 0(NOP), then nothing else to do */ 272 if (nir) { 273 /* 274 * Negative err means FPU instruction in BD-slot, 275 * Zero err means 'BD-slot emulation done' 276 * For anything else we go back to trampoline emulation. 277 */ 278 err = mipsr6_emul(regs, nir); 279 if (err > 0) { 280 regs->cp0_epc = nepc; 281 err = mips_dsemul(regs, nir, cepc); 282 if (err == SIGILL) 283 err = SIGEMT; 284 MIPS_R2_STATS(dsemul); 285 } 286 } 287 288 return err; 289 } 290 291 /** 292 * movz_func - Emulate a MOVZ instruction 293 * @regs: Process register set 294 * @ir: Instruction 295 * 296 * Returns 0 since it always succeeds. 297 */ 298 static int movz_func(struct pt_regs *regs, u32 ir) 299 { 300 if (((regs->regs[MIPSInst_RT(ir)]) == 0) && MIPSInst_RD(ir)) 301 regs->regs[MIPSInst_RD(ir)] = regs->regs[MIPSInst_RS(ir)]; 302 MIPS_R2_STATS(movs); 303 304 return 0; 305 } 306 307 /** 308 * movn_func - Emulate a MOVZ instruction 309 * @regs: Process register set 310 * @ir: Instruction 311 * 312 * Returns 0 since it always succeeds. 313 */ 314 static int movn_func(struct pt_regs *regs, u32 ir) 315 { 316 if (((regs->regs[MIPSInst_RT(ir)]) != 0) && MIPSInst_RD(ir)) 317 regs->regs[MIPSInst_RD(ir)] = regs->regs[MIPSInst_RS(ir)]; 318 MIPS_R2_STATS(movs); 319 320 return 0; 321 } 322 323 /** 324 * mfhi_func - Emulate a MFHI instruction 325 * @regs: Process register set 326 * @ir: Instruction 327 * 328 * Returns 0 since it always succeeds. 329 */ 330 static int mfhi_func(struct pt_regs *regs, u32 ir) 331 { 332 if (MIPSInst_RD(ir)) 333 regs->regs[MIPSInst_RD(ir)] = regs->hi; 334 335 MIPS_R2_STATS(hilo); 336 337 return 0; 338 } 339 340 /** 341 * mthi_func - Emulate a MTHI instruction 342 * @regs: Process register set 343 * @ir: Instruction 344 * 345 * Returns 0 since it always succeeds. 346 */ 347 static int mthi_func(struct pt_regs *regs, u32 ir) 348 { 349 regs->hi = regs->regs[MIPSInst_RS(ir)]; 350 351 MIPS_R2_STATS(hilo); 352 353 return 0; 354 } 355 356 /** 357 * mflo_func - Emulate a MFLO instruction 358 * @regs: Process register set 359 * @ir: Instruction 360 * 361 * Returns 0 since it always succeeds. 362 */ 363 static int mflo_func(struct pt_regs *regs, u32 ir) 364 { 365 if (MIPSInst_RD(ir)) 366 regs->regs[MIPSInst_RD(ir)] = regs->lo; 367 368 MIPS_R2_STATS(hilo); 369 370 return 0; 371 } 372 373 /** 374 * mtlo_func - Emulate a MTLO instruction 375 * @regs: Process register set 376 * @ir: Instruction 377 * 378 * Returns 0 since it always succeeds. 379 */ 380 static int mtlo_func(struct pt_regs *regs, u32 ir) 381 { 382 regs->lo = regs->regs[MIPSInst_RS(ir)]; 383 384 MIPS_R2_STATS(hilo); 385 386 return 0; 387 } 388 389 /** 390 * mult_func - Emulate a MULT instruction 391 * @regs: Process register set 392 * @ir: Instruction 393 * 394 * Returns 0 since it always succeeds. 395 */ 396 static int mult_func(struct pt_regs *regs, u32 ir) 397 { 398 s64 res; 399 s32 rt, rs; 400 401 rt = regs->regs[MIPSInst_RT(ir)]; 402 rs = regs->regs[MIPSInst_RS(ir)]; 403 res = (s64)rt * (s64)rs; 404 405 rs = res; 406 regs->lo = (s64)rs; 407 rt = res >> 32; 408 res = (s64)rt; 409 regs->hi = res; 410 411 MIPS_R2_STATS(muls); 412 413 return 0; 414 } 415 416 /** 417 * multu_func - Emulate a MULTU instruction 418 * @regs: Process register set 419 * @ir: Instruction 420 * 421 * Returns 0 since it always succeeds. 422 */ 423 static int multu_func(struct pt_regs *regs, u32 ir) 424 { 425 u64 res; 426 u32 rt, rs; 427 428 rt = regs->regs[MIPSInst_RT(ir)]; 429 rs = regs->regs[MIPSInst_RS(ir)]; 430 res = (u64)rt * (u64)rs; 431 rt = res; 432 regs->lo = (s64)rt; 433 regs->hi = (s64)(res >> 32); 434 435 MIPS_R2_STATS(muls); 436 437 return 0; 438 } 439 440 /** 441 * div_func - Emulate a DIV instruction 442 * @regs: Process register set 443 * @ir: Instruction 444 * 445 * Returns 0 since it always succeeds. 446 */ 447 static int div_func(struct pt_regs *regs, u32 ir) 448 { 449 s32 rt, rs; 450 451 rt = regs->regs[MIPSInst_RT(ir)]; 452 rs = regs->regs[MIPSInst_RS(ir)]; 453 454 regs->lo = (s64)(rs / rt); 455 regs->hi = (s64)(rs % rt); 456 457 MIPS_R2_STATS(divs); 458 459 return 0; 460 } 461 462 /** 463 * divu_func - Emulate a DIVU instruction 464 * @regs: Process register set 465 * @ir: Instruction 466 * 467 * Returns 0 since it always succeeds. 468 */ 469 static int divu_func(struct pt_regs *regs, u32 ir) 470 { 471 u32 rt, rs; 472 473 rt = regs->regs[MIPSInst_RT(ir)]; 474 rs = regs->regs[MIPSInst_RS(ir)]; 475 476 regs->lo = (s64)(rs / rt); 477 regs->hi = (s64)(rs % rt); 478 479 MIPS_R2_STATS(divs); 480 481 return 0; 482 } 483 484 /** 485 * dmult_func - Emulate a DMULT instruction 486 * @regs: Process register set 487 * @ir: Instruction 488 * 489 * Returns 0 on success or SIGILL for 32-bit kernels. 490 */ 491 static int dmult_func(struct pt_regs *regs, u32 ir) 492 { 493 s64 res; 494 s64 rt, rs; 495 496 if (config_enabled(CONFIG_32BIT)) 497 return SIGILL; 498 499 rt = regs->regs[MIPSInst_RT(ir)]; 500 rs = regs->regs[MIPSInst_RS(ir)]; 501 res = rt * rs; 502 503 regs->lo = res; 504 __asm__ __volatile__( 505 "dmuh %0, %1, %2\t\n" 506 : "=r"(res) 507 : "r"(rt), "r"(rs)); 508 509 regs->hi = res; 510 511 MIPS_R2_STATS(muls); 512 513 return 0; 514 } 515 516 /** 517 * dmultu_func - Emulate a DMULTU instruction 518 * @regs: Process register set 519 * @ir: Instruction 520 * 521 * Returns 0 on success or SIGILL for 32-bit kernels. 522 */ 523 static int dmultu_func(struct pt_regs *regs, u32 ir) 524 { 525 u64 res; 526 u64 rt, rs; 527 528 if (config_enabled(CONFIG_32BIT)) 529 return SIGILL; 530 531 rt = regs->regs[MIPSInst_RT(ir)]; 532 rs = regs->regs[MIPSInst_RS(ir)]; 533 res = rt * rs; 534 535 regs->lo = res; 536 __asm__ __volatile__( 537 "dmuhu %0, %1, %2\t\n" 538 : "=r"(res) 539 : "r"(rt), "r"(rs)); 540 541 regs->hi = res; 542 543 MIPS_R2_STATS(muls); 544 545 return 0; 546 } 547 548 /** 549 * ddiv_func - Emulate a DDIV instruction 550 * @regs: Process register set 551 * @ir: Instruction 552 * 553 * Returns 0 on success or SIGILL for 32-bit kernels. 554 */ 555 static int ddiv_func(struct pt_regs *regs, u32 ir) 556 { 557 s64 rt, rs; 558 559 if (config_enabled(CONFIG_32BIT)) 560 return SIGILL; 561 562 rt = regs->regs[MIPSInst_RT(ir)]; 563 rs = regs->regs[MIPSInst_RS(ir)]; 564 565 regs->lo = rs / rt; 566 regs->hi = rs % rt; 567 568 MIPS_R2_STATS(divs); 569 570 return 0; 571 } 572 573 /** 574 * ddivu_func - Emulate a DDIVU instruction 575 * @regs: Process register set 576 * @ir: Instruction 577 * 578 * Returns 0 on success or SIGILL for 32-bit kernels. 579 */ 580 static int ddivu_func(struct pt_regs *regs, u32 ir) 581 { 582 u64 rt, rs; 583 584 if (config_enabled(CONFIG_32BIT)) 585 return SIGILL; 586 587 rt = regs->regs[MIPSInst_RT(ir)]; 588 rs = regs->regs[MIPSInst_RS(ir)]; 589 590 regs->lo = rs / rt; 591 regs->hi = rs % rt; 592 593 MIPS_R2_STATS(divs); 594 595 return 0; 596 } 597 598 /* R6 removed instructions for the SPECIAL opcode */ 599 static struct r2_decoder_table spec_op_table[] = { 600 { 0xfc1ff83f, 0x00000008, jr_func }, 601 { 0xfc00ffff, 0x00000018, mult_func }, 602 { 0xfc00ffff, 0x00000019, multu_func }, 603 { 0xfc00ffff, 0x0000001c, dmult_func }, 604 { 0xfc00ffff, 0x0000001d, dmultu_func }, 605 { 0xffff07ff, 0x00000010, mfhi_func }, 606 { 0xfc1fffff, 0x00000011, mthi_func }, 607 { 0xffff07ff, 0x00000012, mflo_func }, 608 { 0xfc1fffff, 0x00000013, mtlo_func }, 609 { 0xfc0307ff, 0x00000001, movf_func }, 610 { 0xfc0307ff, 0x00010001, movt_func }, 611 { 0xfc0007ff, 0x0000000a, movz_func }, 612 { 0xfc0007ff, 0x0000000b, movn_func }, 613 { 0xfc00ffff, 0x0000001a, div_func }, 614 { 0xfc00ffff, 0x0000001b, divu_func }, 615 { 0xfc00ffff, 0x0000001e, ddiv_func }, 616 { 0xfc00ffff, 0x0000001f, ddivu_func }, 617 {} 618 }; 619 620 /** 621 * madd_func - Emulate a MADD instruction 622 * @regs: Process register set 623 * @ir: Instruction 624 * 625 * Returns 0 since it always succeeds. 626 */ 627 static int madd_func(struct pt_regs *regs, u32 ir) 628 { 629 s64 res; 630 s32 rt, rs; 631 632 rt = regs->regs[MIPSInst_RT(ir)]; 633 rs = regs->regs[MIPSInst_RS(ir)]; 634 res = (s64)rt * (s64)rs; 635 rt = regs->hi; 636 rs = regs->lo; 637 res += ((((s64)rt) << 32) | (u32)rs); 638 639 rt = res; 640 regs->lo = (s64)rt; 641 rs = res >> 32; 642 regs->hi = (s64)rs; 643 644 MIPS_R2_STATS(dsps); 645 646 return 0; 647 } 648 649 /** 650 * maddu_func - Emulate a MADDU instruction 651 * @regs: Process register set 652 * @ir: Instruction 653 * 654 * Returns 0 since it always succeeds. 655 */ 656 static int maddu_func(struct pt_regs *regs, u32 ir) 657 { 658 u64 res; 659 u32 rt, rs; 660 661 rt = regs->regs[MIPSInst_RT(ir)]; 662 rs = regs->regs[MIPSInst_RS(ir)]; 663 res = (u64)rt * (u64)rs; 664 rt = regs->hi; 665 rs = regs->lo; 666 res += ((((s64)rt) << 32) | (u32)rs); 667 668 rt = res; 669 regs->lo = (s64)rt; 670 rs = res >> 32; 671 regs->hi = (s64)rs; 672 673 MIPS_R2_STATS(dsps); 674 675 return 0; 676 } 677 678 /** 679 * msub_func - Emulate a MSUB instruction 680 * @regs: Process register set 681 * @ir: Instruction 682 * 683 * Returns 0 since it always succeeds. 684 */ 685 static int msub_func(struct pt_regs *regs, u32 ir) 686 { 687 s64 res; 688 s32 rt, rs; 689 690 rt = regs->regs[MIPSInst_RT(ir)]; 691 rs = regs->regs[MIPSInst_RS(ir)]; 692 res = (s64)rt * (s64)rs; 693 rt = regs->hi; 694 rs = regs->lo; 695 res = ((((s64)rt) << 32) | (u32)rs) - res; 696 697 rt = res; 698 regs->lo = (s64)rt; 699 rs = res >> 32; 700 regs->hi = (s64)rs; 701 702 MIPS_R2_STATS(dsps); 703 704 return 0; 705 } 706 707 /** 708 * msubu_func - Emulate a MSUBU instruction 709 * @regs: Process register set 710 * @ir: Instruction 711 * 712 * Returns 0 since it always succeeds. 713 */ 714 static int msubu_func(struct pt_regs *regs, u32 ir) 715 { 716 u64 res; 717 u32 rt, rs; 718 719 rt = regs->regs[MIPSInst_RT(ir)]; 720 rs = regs->regs[MIPSInst_RS(ir)]; 721 res = (u64)rt * (u64)rs; 722 rt = regs->hi; 723 rs = regs->lo; 724 res = ((((s64)rt) << 32) | (u32)rs) - res; 725 726 rt = res; 727 regs->lo = (s64)rt; 728 rs = res >> 32; 729 regs->hi = (s64)rs; 730 731 MIPS_R2_STATS(dsps); 732 733 return 0; 734 } 735 736 /** 737 * mul_func - Emulate a MUL instruction 738 * @regs: Process register set 739 * @ir: Instruction 740 * 741 * Returns 0 since it always succeeds. 742 */ 743 static int mul_func(struct pt_regs *regs, u32 ir) 744 { 745 s64 res; 746 s32 rt, rs; 747 748 if (!MIPSInst_RD(ir)) 749 return 0; 750 rt = regs->regs[MIPSInst_RT(ir)]; 751 rs = regs->regs[MIPSInst_RS(ir)]; 752 res = (s64)rt * (s64)rs; 753 754 rs = res; 755 regs->regs[MIPSInst_RD(ir)] = (s64)rs; 756 757 MIPS_R2_STATS(muls); 758 759 return 0; 760 } 761 762 /** 763 * clz_func - Emulate a CLZ instruction 764 * @regs: Process register set 765 * @ir: Instruction 766 * 767 * Returns 0 since it always succeeds. 768 */ 769 static int clz_func(struct pt_regs *regs, u32 ir) 770 { 771 u32 res; 772 u32 rs; 773 774 if (!MIPSInst_RD(ir)) 775 return 0; 776 777 rs = regs->regs[MIPSInst_RS(ir)]; 778 __asm__ __volatile__("clz %0, %1" : "=r"(res) : "r"(rs)); 779 regs->regs[MIPSInst_RD(ir)] = res; 780 781 MIPS_R2_STATS(bops); 782 783 return 0; 784 } 785 786 /** 787 * clo_func - Emulate a CLO instruction 788 * @regs: Process register set 789 * @ir: Instruction 790 * 791 * Returns 0 since it always succeeds. 792 */ 793 794 static int clo_func(struct pt_regs *regs, u32 ir) 795 { 796 u32 res; 797 u32 rs; 798 799 if (!MIPSInst_RD(ir)) 800 return 0; 801 802 rs = regs->regs[MIPSInst_RS(ir)]; 803 __asm__ __volatile__("clo %0, %1" : "=r"(res) : "r"(rs)); 804 regs->regs[MIPSInst_RD(ir)] = res; 805 806 MIPS_R2_STATS(bops); 807 808 return 0; 809 } 810 811 /** 812 * dclz_func - Emulate a DCLZ instruction 813 * @regs: Process register set 814 * @ir: Instruction 815 * 816 * Returns 0 since it always succeeds. 817 */ 818 static int dclz_func(struct pt_regs *regs, u32 ir) 819 { 820 u64 res; 821 u64 rs; 822 823 if (config_enabled(CONFIG_32BIT)) 824 return SIGILL; 825 826 if (!MIPSInst_RD(ir)) 827 return 0; 828 829 rs = regs->regs[MIPSInst_RS(ir)]; 830 __asm__ __volatile__("dclz %0, %1" : "=r"(res) : "r"(rs)); 831 regs->regs[MIPSInst_RD(ir)] = res; 832 833 MIPS_R2_STATS(bops); 834 835 return 0; 836 } 837 838 /** 839 * dclo_func - Emulate a DCLO instruction 840 * @regs: Process register set 841 * @ir: Instruction 842 * 843 * Returns 0 since it always succeeds. 844 */ 845 static int dclo_func(struct pt_regs *regs, u32 ir) 846 { 847 u64 res; 848 u64 rs; 849 850 if (config_enabled(CONFIG_32BIT)) 851 return SIGILL; 852 853 if (!MIPSInst_RD(ir)) 854 return 0; 855 856 rs = regs->regs[MIPSInst_RS(ir)]; 857 __asm__ __volatile__("dclo %0, %1" : "=r"(res) : "r"(rs)); 858 regs->regs[MIPSInst_RD(ir)] = res; 859 860 MIPS_R2_STATS(bops); 861 862 return 0; 863 } 864 865 /* R6 removed instructions for the SPECIAL2 opcode */ 866 static struct r2_decoder_table spec2_op_table[] = { 867 { 0xfc00ffff, 0x70000000, madd_func }, 868 { 0xfc00ffff, 0x70000001, maddu_func }, 869 { 0xfc0007ff, 0x70000002, mul_func }, 870 { 0xfc00ffff, 0x70000004, msub_func }, 871 { 0xfc00ffff, 0x70000005, msubu_func }, 872 { 0xfc0007ff, 0x70000020, clz_func }, 873 { 0xfc0007ff, 0x70000021, clo_func }, 874 { 0xfc0007ff, 0x70000024, dclz_func }, 875 { 0xfc0007ff, 0x70000025, dclo_func }, 876 { } 877 }; 878 879 static inline int mipsr2_find_op_func(struct pt_regs *regs, u32 inst, 880 struct r2_decoder_table *table) 881 { 882 struct r2_decoder_table *p; 883 int err; 884 885 for (p = table; p->func; p++) { 886 if ((inst & p->mask) == p->code) { 887 err = (p->func)(regs, inst); 888 return err; 889 } 890 } 891 return SIGILL; 892 } 893 894 /** 895 * mipsr2_decoder: Decode and emulate a MIPS R2 instruction 896 * @regs: Process register set 897 * @inst: Instruction to decode and emulate 898 */ 899 int mipsr2_decoder(struct pt_regs *regs, u32 inst) 900 { 901 int err = 0; 902 unsigned long vaddr; 903 u32 nir; 904 unsigned long cpc, epc, nepc, r31, res, rs, rt; 905 906 void __user *fault_addr = NULL; 907 int pass = 0; 908 909 repeat: 910 r31 = regs->regs[31]; 911 epc = regs->cp0_epc; 912 err = compute_return_epc(regs); 913 if (err < 0) { 914 BUG(); 915 return SIGEMT; 916 } 917 pr_debug("Emulating the 0x%08x R2 instruction @ 0x%08lx (pass=%d))\n", 918 inst, epc, pass); 919 920 switch (MIPSInst_OPCODE(inst)) { 921 case spec_op: 922 err = mipsr2_find_op_func(regs, inst, spec_op_table); 923 if (err < 0) { 924 /* FPU instruction under JR */ 925 regs->cp0_cause |= CAUSEF_BD; 926 goto fpu_emul; 927 } 928 break; 929 case spec2_op: 930 err = mipsr2_find_op_func(regs, inst, spec2_op_table); 931 break; 932 case bcond_op: 933 rt = MIPSInst_RT(inst); 934 rs = MIPSInst_RS(inst); 935 switch (rt) { 936 case tgei_op: 937 if ((long)regs->regs[rs] >= MIPSInst_SIMM(inst)) 938 do_trap_or_bp(regs, 0, "TGEI"); 939 940 MIPS_R2_STATS(traps); 941 942 break; 943 case tgeiu_op: 944 if (regs->regs[rs] >= MIPSInst_UIMM(inst)) 945 do_trap_or_bp(regs, 0, "TGEIU"); 946 947 MIPS_R2_STATS(traps); 948 949 break; 950 case tlti_op: 951 if ((long)regs->regs[rs] < MIPSInst_SIMM(inst)) 952 do_trap_or_bp(regs, 0, "TLTI"); 953 954 MIPS_R2_STATS(traps); 955 956 break; 957 case tltiu_op: 958 if (regs->regs[rs] < MIPSInst_UIMM(inst)) 959 do_trap_or_bp(regs, 0, "TLTIU"); 960 961 MIPS_R2_STATS(traps); 962 963 break; 964 case teqi_op: 965 if (regs->regs[rs] == MIPSInst_SIMM(inst)) 966 do_trap_or_bp(regs, 0, "TEQI"); 967 968 MIPS_R2_STATS(traps); 969 970 break; 971 case tnei_op: 972 if (regs->regs[rs] != MIPSInst_SIMM(inst)) 973 do_trap_or_bp(regs, 0, "TNEI"); 974 975 MIPS_R2_STATS(traps); 976 977 break; 978 case bltzl_op: 979 case bgezl_op: 980 case bltzall_op: 981 case bgezall_op: 982 if (delay_slot(regs)) { 983 err = SIGILL; 984 break; 985 } 986 regs->regs[31] = r31; 987 regs->cp0_epc = epc; 988 err = __compute_return_epc(regs); 989 if (err < 0) 990 return SIGEMT; 991 if (err != BRANCH_LIKELY_TAKEN) 992 break; 993 cpc = regs->cp0_epc; 994 nepc = epc + 4; 995 err = __get_user(nir, (u32 __user *)nepc); 996 if (err) { 997 err = SIGSEGV; 998 break; 999 } 1000 /* 1001 * This will probably be optimized away when 1002 * CONFIG_DEBUG_FS is not enabled 1003 */ 1004 switch (rt) { 1005 case bltzl_op: 1006 MIPS_R2BR_STATS(bltzl); 1007 break; 1008 case bgezl_op: 1009 MIPS_R2BR_STATS(bgezl); 1010 break; 1011 case bltzall_op: 1012 MIPS_R2BR_STATS(bltzall); 1013 break; 1014 case bgezall_op: 1015 MIPS_R2BR_STATS(bgezall); 1016 break; 1017 } 1018 1019 switch (MIPSInst_OPCODE(nir)) { 1020 case cop1_op: 1021 case cop1x_op: 1022 case lwc1_op: 1023 case swc1_op: 1024 regs->cp0_cause |= CAUSEF_BD; 1025 goto fpu_emul; 1026 } 1027 if (nir) { 1028 err = mipsr6_emul(regs, nir); 1029 if (err > 0) { 1030 err = mips_dsemul(regs, nir, cpc); 1031 if (err == SIGILL) 1032 err = SIGEMT; 1033 MIPS_R2_STATS(dsemul); 1034 } 1035 } 1036 break; 1037 case bltzal_op: 1038 case bgezal_op: 1039 if (delay_slot(regs)) { 1040 err = SIGILL; 1041 break; 1042 } 1043 regs->regs[31] = r31; 1044 regs->cp0_epc = epc; 1045 err = __compute_return_epc(regs); 1046 if (err < 0) 1047 return SIGEMT; 1048 cpc = regs->cp0_epc; 1049 nepc = epc + 4; 1050 err = __get_user(nir, (u32 __user *)nepc); 1051 if (err) { 1052 err = SIGSEGV; 1053 break; 1054 } 1055 /* 1056 * This will probably be optimized away when 1057 * CONFIG_DEBUG_FS is not enabled 1058 */ 1059 switch (rt) { 1060 case bltzal_op: 1061 MIPS_R2BR_STATS(bltzal); 1062 break; 1063 case bgezal_op: 1064 MIPS_R2BR_STATS(bgezal); 1065 break; 1066 } 1067 1068 switch (MIPSInst_OPCODE(nir)) { 1069 case cop1_op: 1070 case cop1x_op: 1071 case lwc1_op: 1072 case swc1_op: 1073 regs->cp0_cause |= CAUSEF_BD; 1074 goto fpu_emul; 1075 } 1076 if (nir) { 1077 err = mipsr6_emul(regs, nir); 1078 if (err > 0) { 1079 err = mips_dsemul(regs, nir, cpc); 1080 if (err == SIGILL) 1081 err = SIGEMT; 1082 MIPS_R2_STATS(dsemul); 1083 } 1084 } 1085 break; 1086 default: 1087 regs->regs[31] = r31; 1088 regs->cp0_epc = epc; 1089 err = SIGILL; 1090 break; 1091 } 1092 break; 1093 1094 case beql_op: 1095 case bnel_op: 1096 case blezl_op: 1097 case bgtzl_op: 1098 if (delay_slot(regs)) { 1099 err = SIGILL; 1100 break; 1101 } 1102 regs->regs[31] = r31; 1103 regs->cp0_epc = epc; 1104 err = __compute_return_epc(regs); 1105 if (err < 0) 1106 return SIGEMT; 1107 if (err != BRANCH_LIKELY_TAKEN) 1108 break; 1109 cpc = regs->cp0_epc; 1110 nepc = epc + 4; 1111 err = __get_user(nir, (u32 __user *)nepc); 1112 if (err) { 1113 err = SIGSEGV; 1114 break; 1115 } 1116 /* 1117 * This will probably be optimized away when 1118 * CONFIG_DEBUG_FS is not enabled 1119 */ 1120 switch (MIPSInst_OPCODE(inst)) { 1121 case beql_op: 1122 MIPS_R2BR_STATS(beql); 1123 break; 1124 case bnel_op: 1125 MIPS_R2BR_STATS(bnel); 1126 break; 1127 case blezl_op: 1128 MIPS_R2BR_STATS(blezl); 1129 break; 1130 case bgtzl_op: 1131 MIPS_R2BR_STATS(bgtzl); 1132 break; 1133 } 1134 1135 switch (MIPSInst_OPCODE(nir)) { 1136 case cop1_op: 1137 case cop1x_op: 1138 case lwc1_op: 1139 case swc1_op: 1140 regs->cp0_cause |= CAUSEF_BD; 1141 goto fpu_emul; 1142 } 1143 if (nir) { 1144 err = mipsr6_emul(regs, nir); 1145 if (err > 0) { 1146 err = mips_dsemul(regs, nir, cpc); 1147 if (err == SIGILL) 1148 err = SIGEMT; 1149 MIPS_R2_STATS(dsemul); 1150 } 1151 } 1152 break; 1153 case lwc1_op: 1154 case swc1_op: 1155 case cop1_op: 1156 case cop1x_op: 1157 fpu_emul: 1158 regs->regs[31] = r31; 1159 regs->cp0_epc = epc; 1160 if (!used_math()) { /* First time FPU user. */ 1161 err = init_fpu(); 1162 set_used_math(); 1163 } 1164 lose_fpu(1); /* Save FPU state for the emulator. */ 1165 1166 err = fpu_emulator_cop1Handler(regs, ¤t->thread.fpu, 0, 1167 &fault_addr); 1168 1169 /* 1170 * this is a tricky issue - lose_fpu() uses LL/SC atomics 1171 * if FPU is owned and effectively cancels user level LL/SC. 1172 * So, it could be logical to don't restore FPU ownership here. 1173 * But the sequence of multiple FPU instructions is much much 1174 * more often than LL-FPU-SC and I prefer loop here until 1175 * next scheduler cycle cancels FPU ownership 1176 */ 1177 own_fpu(1); /* Restore FPU state. */ 1178 1179 if (err) 1180 current->thread.cp0_baduaddr = (unsigned long)fault_addr; 1181 1182 MIPS_R2_STATS(fpus); 1183 1184 break; 1185 1186 case lwl_op: 1187 rt = regs->regs[MIPSInst_RT(inst)]; 1188 vaddr = regs->regs[MIPSInst_RS(inst)] + MIPSInst_SIMM(inst); 1189 if (!access_ok(VERIFY_READ, vaddr, 4)) { 1190 current->thread.cp0_baduaddr = vaddr; 1191 err = SIGSEGV; 1192 break; 1193 } 1194 __asm__ __volatile__( 1195 " .set push\n" 1196 " .set reorder\n" 1197 #ifdef CONFIG_CPU_LITTLE_ENDIAN 1198 "1:" LB "%1, 0(%2)\n" 1199 INS "%0, %1, 24, 8\n" 1200 " andi %1, %2, 0x3\n" 1201 " beq $0, %1, 9f\n" 1202 ADDIU "%2, %2, -1\n" 1203 "2:" LB "%1, 0(%2)\n" 1204 INS "%0, %1, 16, 8\n" 1205 " andi %1, %2, 0x3\n" 1206 " beq $0, %1, 9f\n" 1207 ADDIU "%2, %2, -1\n" 1208 "3:" LB "%1, 0(%2)\n" 1209 INS "%0, %1, 8, 8\n" 1210 " andi %1, %2, 0x3\n" 1211 " beq $0, %1, 9f\n" 1212 ADDIU "%2, %2, -1\n" 1213 "4:" LB "%1, 0(%2)\n" 1214 INS "%0, %1, 0, 8\n" 1215 #else /* !CONFIG_CPU_LITTLE_ENDIAN */ 1216 "1:" LB "%1, 0(%2)\n" 1217 INS "%0, %1, 24, 8\n" 1218 ADDIU "%2, %2, 1\n" 1219 " andi %1, %2, 0x3\n" 1220 " beq $0, %1, 9f\n" 1221 "2:" LB "%1, 0(%2)\n" 1222 INS "%0, %1, 16, 8\n" 1223 ADDIU "%2, %2, 1\n" 1224 " andi %1, %2, 0x3\n" 1225 " beq $0, %1, 9f\n" 1226 "3:" LB "%1, 0(%2)\n" 1227 INS "%0, %1, 8, 8\n" 1228 ADDIU "%2, %2, 1\n" 1229 " andi %1, %2, 0x3\n" 1230 " beq $0, %1, 9f\n" 1231 "4:" LB "%1, 0(%2)\n" 1232 INS "%0, %1, 0, 8\n" 1233 #endif /* CONFIG_CPU_LITTLE_ENDIAN */ 1234 "9: sll %0, %0, 0\n" 1235 "10:\n" 1236 " .insn\n" 1237 " .section .fixup,\"ax\"\n" 1238 "8: li %3,%4\n" 1239 " j 10b\n" 1240 " .previous\n" 1241 " .section __ex_table,\"a\"\n" 1242 " .word 1b,8b\n" 1243 " .word 2b,8b\n" 1244 " .word 3b,8b\n" 1245 " .word 4b,8b\n" 1246 " .previous\n" 1247 " .set pop\n" 1248 : "+&r"(rt), "=&r"(rs), 1249 "+&r"(vaddr), "+&r"(err) 1250 : "i"(SIGSEGV)); 1251 1252 if (MIPSInst_RT(inst) && !err) 1253 regs->regs[MIPSInst_RT(inst)] = rt; 1254 1255 MIPS_R2_STATS(loads); 1256 1257 break; 1258 1259 case lwr_op: 1260 rt = regs->regs[MIPSInst_RT(inst)]; 1261 vaddr = regs->regs[MIPSInst_RS(inst)] + MIPSInst_SIMM(inst); 1262 if (!access_ok(VERIFY_READ, vaddr, 4)) { 1263 current->thread.cp0_baduaddr = vaddr; 1264 err = SIGSEGV; 1265 break; 1266 } 1267 __asm__ __volatile__( 1268 " .set push\n" 1269 " .set reorder\n" 1270 #ifdef CONFIG_CPU_LITTLE_ENDIAN 1271 "1:" LB "%1, 0(%2)\n" 1272 INS "%0, %1, 0, 8\n" 1273 ADDIU "%2, %2, 1\n" 1274 " andi %1, %2, 0x3\n" 1275 " beq $0, %1, 9f\n" 1276 "2:" LB "%1, 0(%2)\n" 1277 INS "%0, %1, 8, 8\n" 1278 ADDIU "%2, %2, 1\n" 1279 " andi %1, %2, 0x3\n" 1280 " beq $0, %1, 9f\n" 1281 "3:" LB "%1, 0(%2)\n" 1282 INS "%0, %1, 16, 8\n" 1283 ADDIU "%2, %2, 1\n" 1284 " andi %1, %2, 0x3\n" 1285 " beq $0, %1, 9f\n" 1286 "4:" LB "%1, 0(%2)\n" 1287 INS "%0, %1, 24, 8\n" 1288 " sll %0, %0, 0\n" 1289 #else /* !CONFIG_CPU_LITTLE_ENDIAN */ 1290 "1:" LB "%1, 0(%2)\n" 1291 INS "%0, %1, 0, 8\n" 1292 " andi %1, %2, 0x3\n" 1293 " beq $0, %1, 9f\n" 1294 ADDIU "%2, %2, -1\n" 1295 "2:" LB "%1, 0(%2)\n" 1296 INS "%0, %1, 8, 8\n" 1297 " andi %1, %2, 0x3\n" 1298 " beq $0, %1, 9f\n" 1299 ADDIU "%2, %2, -1\n" 1300 "3:" LB "%1, 0(%2)\n" 1301 INS "%0, %1, 16, 8\n" 1302 " andi %1, %2, 0x3\n" 1303 " beq $0, %1, 9f\n" 1304 ADDIU "%2, %2, -1\n" 1305 "4:" LB "%1, 0(%2)\n" 1306 INS "%0, %1, 24, 8\n" 1307 " sll %0, %0, 0\n" 1308 #endif /* CONFIG_CPU_LITTLE_ENDIAN */ 1309 "9:\n" 1310 "10:\n" 1311 " .insn\n" 1312 " .section .fixup,\"ax\"\n" 1313 "8: li %3,%4\n" 1314 " j 10b\n" 1315 " .previous\n" 1316 " .section __ex_table,\"a\"\n" 1317 " .word 1b,8b\n" 1318 " .word 2b,8b\n" 1319 " .word 3b,8b\n" 1320 " .word 4b,8b\n" 1321 " .previous\n" 1322 " .set pop\n" 1323 : "+&r"(rt), "=&r"(rs), 1324 "+&r"(vaddr), "+&r"(err) 1325 : "i"(SIGSEGV)); 1326 if (MIPSInst_RT(inst) && !err) 1327 regs->regs[MIPSInst_RT(inst)] = rt; 1328 1329 MIPS_R2_STATS(loads); 1330 1331 break; 1332 1333 case swl_op: 1334 rt = regs->regs[MIPSInst_RT(inst)]; 1335 vaddr = regs->regs[MIPSInst_RS(inst)] + MIPSInst_SIMM(inst); 1336 if (!access_ok(VERIFY_WRITE, vaddr, 4)) { 1337 current->thread.cp0_baduaddr = vaddr; 1338 err = SIGSEGV; 1339 break; 1340 } 1341 __asm__ __volatile__( 1342 " .set push\n" 1343 " .set reorder\n" 1344 #ifdef CONFIG_CPU_LITTLE_ENDIAN 1345 EXT "%1, %0, 24, 8\n" 1346 "1:" SB "%1, 0(%2)\n" 1347 " andi %1, %2, 0x3\n" 1348 " beq $0, %1, 9f\n" 1349 ADDIU "%2, %2, -1\n" 1350 EXT "%1, %0, 16, 8\n" 1351 "2:" SB "%1, 0(%2)\n" 1352 " andi %1, %2, 0x3\n" 1353 " beq $0, %1, 9f\n" 1354 ADDIU "%2, %2, -1\n" 1355 EXT "%1, %0, 8, 8\n" 1356 "3:" SB "%1, 0(%2)\n" 1357 " andi %1, %2, 0x3\n" 1358 " beq $0, %1, 9f\n" 1359 ADDIU "%2, %2, -1\n" 1360 EXT "%1, %0, 0, 8\n" 1361 "4:" SB "%1, 0(%2)\n" 1362 #else /* !CONFIG_CPU_LITTLE_ENDIAN */ 1363 EXT "%1, %0, 24, 8\n" 1364 "1:" SB "%1, 0(%2)\n" 1365 ADDIU "%2, %2, 1\n" 1366 " andi %1, %2, 0x3\n" 1367 " beq $0, %1, 9f\n" 1368 EXT "%1, %0, 16, 8\n" 1369 "2:" SB "%1, 0(%2)\n" 1370 ADDIU "%2, %2, 1\n" 1371 " andi %1, %2, 0x3\n" 1372 " beq $0, %1, 9f\n" 1373 EXT "%1, %0, 8, 8\n" 1374 "3:" SB "%1, 0(%2)\n" 1375 ADDIU "%2, %2, 1\n" 1376 " andi %1, %2, 0x3\n" 1377 " beq $0, %1, 9f\n" 1378 EXT "%1, %0, 0, 8\n" 1379 "4:" SB "%1, 0(%2)\n" 1380 #endif /* CONFIG_CPU_LITTLE_ENDIAN */ 1381 "9:\n" 1382 " .insn\n" 1383 " .section .fixup,\"ax\"\n" 1384 "8: li %3,%4\n" 1385 " j 9b\n" 1386 " .previous\n" 1387 " .section __ex_table,\"a\"\n" 1388 " .word 1b,8b\n" 1389 " .word 2b,8b\n" 1390 " .word 3b,8b\n" 1391 " .word 4b,8b\n" 1392 " .previous\n" 1393 " .set pop\n" 1394 : "+&r"(rt), "=&r"(rs), 1395 "+&r"(vaddr), "+&r"(err) 1396 : "i"(SIGSEGV) 1397 : "memory"); 1398 1399 MIPS_R2_STATS(stores); 1400 1401 break; 1402 1403 case swr_op: 1404 rt = regs->regs[MIPSInst_RT(inst)]; 1405 vaddr = regs->regs[MIPSInst_RS(inst)] + MIPSInst_SIMM(inst); 1406 if (!access_ok(VERIFY_WRITE, vaddr, 4)) { 1407 current->thread.cp0_baduaddr = vaddr; 1408 err = SIGSEGV; 1409 break; 1410 } 1411 __asm__ __volatile__( 1412 " .set push\n" 1413 " .set reorder\n" 1414 #ifdef CONFIG_CPU_LITTLE_ENDIAN 1415 EXT "%1, %0, 0, 8\n" 1416 "1:" SB "%1, 0(%2)\n" 1417 ADDIU "%2, %2, 1\n" 1418 " andi %1, %2, 0x3\n" 1419 " beq $0, %1, 9f\n" 1420 EXT "%1, %0, 8, 8\n" 1421 "2:" SB "%1, 0(%2)\n" 1422 ADDIU "%2, %2, 1\n" 1423 " andi %1, %2, 0x3\n" 1424 " beq $0, %1, 9f\n" 1425 EXT "%1, %0, 16, 8\n" 1426 "3:" SB "%1, 0(%2)\n" 1427 ADDIU "%2, %2, 1\n" 1428 " andi %1, %2, 0x3\n" 1429 " beq $0, %1, 9f\n" 1430 EXT "%1, %0, 24, 8\n" 1431 "4:" SB "%1, 0(%2)\n" 1432 #else /* !CONFIG_CPU_LITTLE_ENDIAN */ 1433 EXT "%1, %0, 0, 8\n" 1434 "1:" SB "%1, 0(%2)\n" 1435 " andi %1, %2, 0x3\n" 1436 " beq $0, %1, 9f\n" 1437 ADDIU "%2, %2, -1\n" 1438 EXT "%1, %0, 8, 8\n" 1439 "2:" SB "%1, 0(%2)\n" 1440 " andi %1, %2, 0x3\n" 1441 " beq $0, %1, 9f\n" 1442 ADDIU "%2, %2, -1\n" 1443 EXT "%1, %0, 16, 8\n" 1444 "3:" SB "%1, 0(%2)\n" 1445 " andi %1, %2, 0x3\n" 1446 " beq $0, %1, 9f\n" 1447 ADDIU "%2, %2, -1\n" 1448 EXT "%1, %0, 24, 8\n" 1449 "4:" SB "%1, 0(%2)\n" 1450 #endif /* CONFIG_CPU_LITTLE_ENDIAN */ 1451 "9:\n" 1452 " .insn\n" 1453 " .section .fixup,\"ax\"\n" 1454 "8: li %3,%4\n" 1455 " j 9b\n" 1456 " .previous\n" 1457 " .section __ex_table,\"a\"\n" 1458 " .word 1b,8b\n" 1459 " .word 2b,8b\n" 1460 " .word 3b,8b\n" 1461 " .word 4b,8b\n" 1462 " .previous\n" 1463 " .set pop\n" 1464 : "+&r"(rt), "=&r"(rs), 1465 "+&r"(vaddr), "+&r"(err) 1466 : "i"(SIGSEGV) 1467 : "memory"); 1468 1469 MIPS_R2_STATS(stores); 1470 1471 break; 1472 1473 case ldl_op: 1474 if (config_enabled(CONFIG_32BIT)) { 1475 err = SIGILL; 1476 break; 1477 } 1478 1479 rt = regs->regs[MIPSInst_RT(inst)]; 1480 vaddr = regs->regs[MIPSInst_RS(inst)] + MIPSInst_SIMM(inst); 1481 if (!access_ok(VERIFY_READ, vaddr, 8)) { 1482 current->thread.cp0_baduaddr = vaddr; 1483 err = SIGSEGV; 1484 break; 1485 } 1486 __asm__ __volatile__( 1487 " .set push\n" 1488 " .set reorder\n" 1489 #ifdef CONFIG_CPU_LITTLE_ENDIAN 1490 "1: lb %1, 0(%2)\n" 1491 " dinsu %0, %1, 56, 8\n" 1492 " andi %1, %2, 0x7\n" 1493 " beq $0, %1, 9f\n" 1494 " daddiu %2, %2, -1\n" 1495 "2: lb %1, 0(%2)\n" 1496 " dinsu %0, %1, 48, 8\n" 1497 " andi %1, %2, 0x7\n" 1498 " beq $0, %1, 9f\n" 1499 " daddiu %2, %2, -1\n" 1500 "3: lb %1, 0(%2)\n" 1501 " dinsu %0, %1, 40, 8\n" 1502 " andi %1, %2, 0x7\n" 1503 " beq $0, %1, 9f\n" 1504 " daddiu %2, %2, -1\n" 1505 "4: lb %1, 0(%2)\n" 1506 " dinsu %0, %1, 32, 8\n" 1507 " andi %1, %2, 0x7\n" 1508 " beq $0, %1, 9f\n" 1509 " daddiu %2, %2, -1\n" 1510 "5: lb %1, 0(%2)\n" 1511 " dins %0, %1, 24, 8\n" 1512 " andi %1, %2, 0x7\n" 1513 " beq $0, %1, 9f\n" 1514 " daddiu %2, %2, -1\n" 1515 "6: lb %1, 0(%2)\n" 1516 " dins %0, %1, 16, 8\n" 1517 " andi %1, %2, 0x7\n" 1518 " beq $0, %1, 9f\n" 1519 " daddiu %2, %2, -1\n" 1520 "7: lb %1, 0(%2)\n" 1521 " dins %0, %1, 8, 8\n" 1522 " andi %1, %2, 0x7\n" 1523 " beq $0, %1, 9f\n" 1524 " daddiu %2, %2, -1\n" 1525 "0: lb %1, 0(%2)\n" 1526 " dins %0, %1, 0, 8\n" 1527 #else /* !CONFIG_CPU_LITTLE_ENDIAN */ 1528 "1: lb %1, 0(%2)\n" 1529 " dinsu %0, %1, 56, 8\n" 1530 " daddiu %2, %2, 1\n" 1531 " andi %1, %2, 0x7\n" 1532 " beq $0, %1, 9f\n" 1533 "2: lb %1, 0(%2)\n" 1534 " dinsu %0, %1, 48, 8\n" 1535 " daddiu %2, %2, 1\n" 1536 " andi %1, %2, 0x7\n" 1537 " beq $0, %1, 9f\n" 1538 "3: lb %1, 0(%2)\n" 1539 " dinsu %0, %1, 40, 8\n" 1540 " daddiu %2, %2, 1\n" 1541 " andi %1, %2, 0x7\n" 1542 " beq $0, %1, 9f\n" 1543 "4: lb %1, 0(%2)\n" 1544 " dinsu %0, %1, 32, 8\n" 1545 " daddiu %2, %2, 1\n" 1546 " andi %1, %2, 0x7\n" 1547 " beq $0, %1, 9f\n" 1548 "5: lb %1, 0(%2)\n" 1549 " dins %0, %1, 24, 8\n" 1550 " daddiu %2, %2, 1\n" 1551 " andi %1, %2, 0x7\n" 1552 " beq $0, %1, 9f\n" 1553 "6: lb %1, 0(%2)\n" 1554 " dins %0, %1, 16, 8\n" 1555 " daddiu %2, %2, 1\n" 1556 " andi %1, %2, 0x7\n" 1557 " beq $0, %1, 9f\n" 1558 "7: lb %1, 0(%2)\n" 1559 " dins %0, %1, 8, 8\n" 1560 " daddiu %2, %2, 1\n" 1561 " andi %1, %2, 0x7\n" 1562 " beq $0, %1, 9f\n" 1563 "0: lb %1, 0(%2)\n" 1564 " dins %0, %1, 0, 8\n" 1565 #endif /* CONFIG_CPU_LITTLE_ENDIAN */ 1566 "9:\n" 1567 " .insn\n" 1568 " .section .fixup,\"ax\"\n" 1569 "8: li %3,%4\n" 1570 " j 9b\n" 1571 " .previous\n" 1572 " .section __ex_table,\"a\"\n" 1573 " .word 1b,8b\n" 1574 " .word 2b,8b\n" 1575 " .word 3b,8b\n" 1576 " .word 4b,8b\n" 1577 " .word 5b,8b\n" 1578 " .word 6b,8b\n" 1579 " .word 7b,8b\n" 1580 " .word 0b,8b\n" 1581 " .previous\n" 1582 " .set pop\n" 1583 : "+&r"(rt), "=&r"(rs), 1584 "+&r"(vaddr), "+&r"(err) 1585 : "i"(SIGSEGV)); 1586 if (MIPSInst_RT(inst) && !err) 1587 regs->regs[MIPSInst_RT(inst)] = rt; 1588 1589 MIPS_R2_STATS(loads); 1590 break; 1591 1592 case ldr_op: 1593 if (config_enabled(CONFIG_32BIT)) { 1594 err = SIGILL; 1595 break; 1596 } 1597 1598 rt = regs->regs[MIPSInst_RT(inst)]; 1599 vaddr = regs->regs[MIPSInst_RS(inst)] + MIPSInst_SIMM(inst); 1600 if (!access_ok(VERIFY_READ, vaddr, 8)) { 1601 current->thread.cp0_baduaddr = vaddr; 1602 err = SIGSEGV; 1603 break; 1604 } 1605 __asm__ __volatile__( 1606 " .set push\n" 1607 " .set reorder\n" 1608 #ifdef CONFIG_CPU_LITTLE_ENDIAN 1609 "1: lb %1, 0(%2)\n" 1610 " dins %0, %1, 0, 8\n" 1611 " daddiu %2, %2, 1\n" 1612 " andi %1, %2, 0x7\n" 1613 " beq $0, %1, 9f\n" 1614 "2: lb %1, 0(%2)\n" 1615 " dins %0, %1, 8, 8\n" 1616 " daddiu %2, %2, 1\n" 1617 " andi %1, %2, 0x7\n" 1618 " beq $0, %1, 9f\n" 1619 "3: lb %1, 0(%2)\n" 1620 " dins %0, %1, 16, 8\n" 1621 " daddiu %2, %2, 1\n" 1622 " andi %1, %2, 0x7\n" 1623 " beq $0, %1, 9f\n" 1624 "4: lb %1, 0(%2)\n" 1625 " dins %0, %1, 24, 8\n" 1626 " daddiu %2, %2, 1\n" 1627 " andi %1, %2, 0x7\n" 1628 " beq $0, %1, 9f\n" 1629 "5: lb %1, 0(%2)\n" 1630 " dinsu %0, %1, 32, 8\n" 1631 " daddiu %2, %2, 1\n" 1632 " andi %1, %2, 0x7\n" 1633 " beq $0, %1, 9f\n" 1634 "6: lb %1, 0(%2)\n" 1635 " dinsu %0, %1, 40, 8\n" 1636 " daddiu %2, %2, 1\n" 1637 " andi %1, %2, 0x7\n" 1638 " beq $0, %1, 9f\n" 1639 "7: lb %1, 0(%2)\n" 1640 " dinsu %0, %1, 48, 8\n" 1641 " daddiu %2, %2, 1\n" 1642 " andi %1, %2, 0x7\n" 1643 " beq $0, %1, 9f\n" 1644 "0: lb %1, 0(%2)\n" 1645 " dinsu %0, %1, 56, 8\n" 1646 #else /* !CONFIG_CPU_LITTLE_ENDIAN */ 1647 "1: lb %1, 0(%2)\n" 1648 " dins %0, %1, 0, 8\n" 1649 " andi %1, %2, 0x7\n" 1650 " beq $0, %1, 9f\n" 1651 " daddiu %2, %2, -1\n" 1652 "2: lb %1, 0(%2)\n" 1653 " dins %0, %1, 8, 8\n" 1654 " andi %1, %2, 0x7\n" 1655 " beq $0, %1, 9f\n" 1656 " daddiu %2, %2, -1\n" 1657 "3: lb %1, 0(%2)\n" 1658 " dins %0, %1, 16, 8\n" 1659 " andi %1, %2, 0x7\n" 1660 " beq $0, %1, 9f\n" 1661 " daddiu %2, %2, -1\n" 1662 "4: lb %1, 0(%2)\n" 1663 " dins %0, %1, 24, 8\n" 1664 " andi %1, %2, 0x7\n" 1665 " beq $0, %1, 9f\n" 1666 " daddiu %2, %2, -1\n" 1667 "5: lb %1, 0(%2)\n" 1668 " dinsu %0, %1, 32, 8\n" 1669 " andi %1, %2, 0x7\n" 1670 " beq $0, %1, 9f\n" 1671 " daddiu %2, %2, -1\n" 1672 "6: lb %1, 0(%2)\n" 1673 " dinsu %0, %1, 40, 8\n" 1674 " andi %1, %2, 0x7\n" 1675 " beq $0, %1, 9f\n" 1676 " daddiu %2, %2, -1\n" 1677 "7: lb %1, 0(%2)\n" 1678 " dinsu %0, %1, 48, 8\n" 1679 " andi %1, %2, 0x7\n" 1680 " beq $0, %1, 9f\n" 1681 " daddiu %2, %2, -1\n" 1682 "0: lb %1, 0(%2)\n" 1683 " dinsu %0, %1, 56, 8\n" 1684 #endif /* CONFIG_CPU_LITTLE_ENDIAN */ 1685 "9:\n" 1686 " .insn\n" 1687 " .section .fixup,\"ax\"\n" 1688 "8: li %3,%4\n" 1689 " j 9b\n" 1690 " .previous\n" 1691 " .section __ex_table,\"a\"\n" 1692 " .word 1b,8b\n" 1693 " .word 2b,8b\n" 1694 " .word 3b,8b\n" 1695 " .word 4b,8b\n" 1696 " .word 5b,8b\n" 1697 " .word 6b,8b\n" 1698 " .word 7b,8b\n" 1699 " .word 0b,8b\n" 1700 " .previous\n" 1701 " .set pop\n" 1702 : "+&r"(rt), "=&r"(rs), 1703 "+&r"(vaddr), "+&r"(err) 1704 : "i"(SIGSEGV)); 1705 if (MIPSInst_RT(inst) && !err) 1706 regs->regs[MIPSInst_RT(inst)] = rt; 1707 1708 MIPS_R2_STATS(loads); 1709 break; 1710 1711 case sdl_op: 1712 if (config_enabled(CONFIG_32BIT)) { 1713 err = SIGILL; 1714 break; 1715 } 1716 1717 rt = regs->regs[MIPSInst_RT(inst)]; 1718 vaddr = regs->regs[MIPSInst_RS(inst)] + MIPSInst_SIMM(inst); 1719 if (!access_ok(VERIFY_WRITE, vaddr, 8)) { 1720 current->thread.cp0_baduaddr = vaddr; 1721 err = SIGSEGV; 1722 break; 1723 } 1724 __asm__ __volatile__( 1725 " .set push\n" 1726 " .set reorder\n" 1727 #ifdef CONFIG_CPU_LITTLE_ENDIAN 1728 " dextu %1, %0, 56, 8\n" 1729 "1: sb %1, 0(%2)\n" 1730 " andi %1, %2, 0x7\n" 1731 " beq $0, %1, 9f\n" 1732 " daddiu %2, %2, -1\n" 1733 " dextu %1, %0, 48, 8\n" 1734 "2: sb %1, 0(%2)\n" 1735 " andi %1, %2, 0x7\n" 1736 " beq $0, %1, 9f\n" 1737 " daddiu %2, %2, -1\n" 1738 " dextu %1, %0, 40, 8\n" 1739 "3: sb %1, 0(%2)\n" 1740 " andi %1, %2, 0x7\n" 1741 " beq $0, %1, 9f\n" 1742 " daddiu %2, %2, -1\n" 1743 " dextu %1, %0, 32, 8\n" 1744 "4: sb %1, 0(%2)\n" 1745 " andi %1, %2, 0x7\n" 1746 " beq $0, %1, 9f\n" 1747 " daddiu %2, %2, -1\n" 1748 " dext %1, %0, 24, 8\n" 1749 "5: sb %1, 0(%2)\n" 1750 " andi %1, %2, 0x7\n" 1751 " beq $0, %1, 9f\n" 1752 " daddiu %2, %2, -1\n" 1753 " dext %1, %0, 16, 8\n" 1754 "6: sb %1, 0(%2)\n" 1755 " andi %1, %2, 0x7\n" 1756 " beq $0, %1, 9f\n" 1757 " daddiu %2, %2, -1\n" 1758 " dext %1, %0, 8, 8\n" 1759 "7: sb %1, 0(%2)\n" 1760 " andi %1, %2, 0x7\n" 1761 " beq $0, %1, 9f\n" 1762 " daddiu %2, %2, -1\n" 1763 " dext %1, %0, 0, 8\n" 1764 "0: sb %1, 0(%2)\n" 1765 #else /* !CONFIG_CPU_LITTLE_ENDIAN */ 1766 " dextu %1, %0, 56, 8\n" 1767 "1: sb %1, 0(%2)\n" 1768 " daddiu %2, %2, 1\n" 1769 " andi %1, %2, 0x7\n" 1770 " beq $0, %1, 9f\n" 1771 " dextu %1, %0, 48, 8\n" 1772 "2: sb %1, 0(%2)\n" 1773 " daddiu %2, %2, 1\n" 1774 " andi %1, %2, 0x7\n" 1775 " beq $0, %1, 9f\n" 1776 " dextu %1, %0, 40, 8\n" 1777 "3: sb %1, 0(%2)\n" 1778 " daddiu %2, %2, 1\n" 1779 " andi %1, %2, 0x7\n" 1780 " beq $0, %1, 9f\n" 1781 " dextu %1, %0, 32, 8\n" 1782 "4: sb %1, 0(%2)\n" 1783 " daddiu %2, %2, 1\n" 1784 " andi %1, %2, 0x7\n" 1785 " beq $0, %1, 9f\n" 1786 " dext %1, %0, 24, 8\n" 1787 "5: sb %1, 0(%2)\n" 1788 " daddiu %2, %2, 1\n" 1789 " andi %1, %2, 0x7\n" 1790 " beq $0, %1, 9f\n" 1791 " dext %1, %0, 16, 8\n" 1792 "6: sb %1, 0(%2)\n" 1793 " daddiu %2, %2, 1\n" 1794 " andi %1, %2, 0x7\n" 1795 " beq $0, %1, 9f\n" 1796 " dext %1, %0, 8, 8\n" 1797 "7: sb %1, 0(%2)\n" 1798 " daddiu %2, %2, 1\n" 1799 " andi %1, %2, 0x7\n" 1800 " beq $0, %1, 9f\n" 1801 " dext %1, %0, 0, 8\n" 1802 "0: sb %1, 0(%2)\n" 1803 #endif /* CONFIG_CPU_LITTLE_ENDIAN */ 1804 "9:\n" 1805 " .insn\n" 1806 " .section .fixup,\"ax\"\n" 1807 "8: li %3,%4\n" 1808 " j 9b\n" 1809 " .previous\n" 1810 " .section __ex_table,\"a\"\n" 1811 " .word 1b,8b\n" 1812 " .word 2b,8b\n" 1813 " .word 3b,8b\n" 1814 " .word 4b,8b\n" 1815 " .word 5b,8b\n" 1816 " .word 6b,8b\n" 1817 " .word 7b,8b\n" 1818 " .word 0b,8b\n" 1819 " .previous\n" 1820 " .set pop\n" 1821 : "+&r"(rt), "=&r"(rs), 1822 "+&r"(vaddr), "+&r"(err) 1823 : "i"(SIGSEGV) 1824 : "memory"); 1825 1826 MIPS_R2_STATS(stores); 1827 break; 1828 1829 case sdr_op: 1830 if (config_enabled(CONFIG_32BIT)) { 1831 err = SIGILL; 1832 break; 1833 } 1834 1835 rt = regs->regs[MIPSInst_RT(inst)]; 1836 vaddr = regs->regs[MIPSInst_RS(inst)] + MIPSInst_SIMM(inst); 1837 if (!access_ok(VERIFY_WRITE, vaddr, 8)) { 1838 current->thread.cp0_baduaddr = vaddr; 1839 err = SIGSEGV; 1840 break; 1841 } 1842 __asm__ __volatile__( 1843 " .set push\n" 1844 " .set reorder\n" 1845 #ifdef CONFIG_CPU_LITTLE_ENDIAN 1846 " dext %1, %0, 0, 8\n" 1847 "1: sb %1, 0(%2)\n" 1848 " daddiu %2, %2, 1\n" 1849 " andi %1, %2, 0x7\n" 1850 " beq $0, %1, 9f\n" 1851 " dext %1, %0, 8, 8\n" 1852 "2: sb %1, 0(%2)\n" 1853 " daddiu %2, %2, 1\n" 1854 " andi %1, %2, 0x7\n" 1855 " beq $0, %1, 9f\n" 1856 " dext %1, %0, 16, 8\n" 1857 "3: sb %1, 0(%2)\n" 1858 " daddiu %2, %2, 1\n" 1859 " andi %1, %2, 0x7\n" 1860 " beq $0, %1, 9f\n" 1861 " dext %1, %0, 24, 8\n" 1862 "4: sb %1, 0(%2)\n" 1863 " daddiu %2, %2, 1\n" 1864 " andi %1, %2, 0x7\n" 1865 " beq $0, %1, 9f\n" 1866 " dextu %1, %0, 32, 8\n" 1867 "5: sb %1, 0(%2)\n" 1868 " daddiu %2, %2, 1\n" 1869 " andi %1, %2, 0x7\n" 1870 " beq $0, %1, 9f\n" 1871 " dextu %1, %0, 40, 8\n" 1872 "6: sb %1, 0(%2)\n" 1873 " daddiu %2, %2, 1\n" 1874 " andi %1, %2, 0x7\n" 1875 " beq $0, %1, 9f\n" 1876 " dextu %1, %0, 48, 8\n" 1877 "7: sb %1, 0(%2)\n" 1878 " daddiu %2, %2, 1\n" 1879 " andi %1, %2, 0x7\n" 1880 " beq $0, %1, 9f\n" 1881 " dextu %1, %0, 56, 8\n" 1882 "0: sb %1, 0(%2)\n" 1883 #else /* !CONFIG_CPU_LITTLE_ENDIAN */ 1884 " dext %1, %0, 0, 8\n" 1885 "1: sb %1, 0(%2)\n" 1886 " andi %1, %2, 0x7\n" 1887 " beq $0, %1, 9f\n" 1888 " daddiu %2, %2, -1\n" 1889 " dext %1, %0, 8, 8\n" 1890 "2: sb %1, 0(%2)\n" 1891 " andi %1, %2, 0x7\n" 1892 " beq $0, %1, 9f\n" 1893 " daddiu %2, %2, -1\n" 1894 " dext %1, %0, 16, 8\n" 1895 "3: sb %1, 0(%2)\n" 1896 " andi %1, %2, 0x7\n" 1897 " beq $0, %1, 9f\n" 1898 " daddiu %2, %2, -1\n" 1899 " dext %1, %0, 24, 8\n" 1900 "4: sb %1, 0(%2)\n" 1901 " andi %1, %2, 0x7\n" 1902 " beq $0, %1, 9f\n" 1903 " daddiu %2, %2, -1\n" 1904 " dextu %1, %0, 32, 8\n" 1905 "5: sb %1, 0(%2)\n" 1906 " andi %1, %2, 0x7\n" 1907 " beq $0, %1, 9f\n" 1908 " daddiu %2, %2, -1\n" 1909 " dextu %1, %0, 40, 8\n" 1910 "6: sb %1, 0(%2)\n" 1911 " andi %1, %2, 0x7\n" 1912 " beq $0, %1, 9f\n" 1913 " daddiu %2, %2, -1\n" 1914 " dextu %1, %0, 48, 8\n" 1915 "7: sb %1, 0(%2)\n" 1916 " andi %1, %2, 0x7\n" 1917 " beq $0, %1, 9f\n" 1918 " daddiu %2, %2, -1\n" 1919 " dextu %1, %0, 56, 8\n" 1920 "0: sb %1, 0(%2)\n" 1921 #endif /* CONFIG_CPU_LITTLE_ENDIAN */ 1922 "9:\n" 1923 " .insn\n" 1924 " .section .fixup,\"ax\"\n" 1925 "8: li %3,%4\n" 1926 " j 9b\n" 1927 " .previous\n" 1928 " .section __ex_table,\"a\"\n" 1929 " .word 1b,8b\n" 1930 " .word 2b,8b\n" 1931 " .word 3b,8b\n" 1932 " .word 4b,8b\n" 1933 " .word 5b,8b\n" 1934 " .word 6b,8b\n" 1935 " .word 7b,8b\n" 1936 " .word 0b,8b\n" 1937 " .previous\n" 1938 " .set pop\n" 1939 : "+&r"(rt), "=&r"(rs), 1940 "+&r"(vaddr), "+&r"(err) 1941 : "i"(SIGSEGV) 1942 : "memory"); 1943 1944 MIPS_R2_STATS(stores); 1945 1946 break; 1947 case ll_op: 1948 vaddr = regs->regs[MIPSInst_RS(inst)] + MIPSInst_SIMM(inst); 1949 if (vaddr & 0x3) { 1950 current->thread.cp0_baduaddr = vaddr; 1951 err = SIGBUS; 1952 break; 1953 } 1954 if (!access_ok(VERIFY_READ, vaddr, 4)) { 1955 current->thread.cp0_baduaddr = vaddr; 1956 err = SIGBUS; 1957 break; 1958 } 1959 1960 if (!cpu_has_rw_llb) { 1961 /* 1962 * An LL/SC block can't be safely emulated without 1963 * a Config5/LLB availability. So it's probably time to 1964 * kill our process before things get any worse. This is 1965 * because Config5/LLB allows us to use ERETNC so that 1966 * the LLAddr/LLB bit is not cleared when we return from 1967 * an exception. MIPS R2 LL/SC instructions trap with an 1968 * RI exception so once we emulate them here, we return 1969 * back to userland with ERETNC. That preserves the 1970 * LLAddr/LLB so the subsequent SC instruction will 1971 * succeed preserving the atomic semantics of the LL/SC 1972 * block. Without that, there is no safe way to emulate 1973 * an LL/SC block in MIPSR2 userland. 1974 */ 1975 pr_err("Can't emulate MIPSR2 LL/SC without Config5/LLB\n"); 1976 err = SIGKILL; 1977 break; 1978 } 1979 1980 __asm__ __volatile__( 1981 "1:\n" 1982 "ll %0, 0(%2)\n" 1983 "2:\n" 1984 ".insn\n" 1985 ".section .fixup,\"ax\"\n" 1986 "3:\n" 1987 "li %1, %3\n" 1988 "j 2b\n" 1989 ".previous\n" 1990 ".section __ex_table,\"a\"\n" 1991 ".word 1b, 3b\n" 1992 ".previous\n" 1993 : "=&r"(res), "+&r"(err) 1994 : "r"(vaddr), "i"(SIGSEGV) 1995 : "memory"); 1996 1997 if (MIPSInst_RT(inst) && !err) 1998 regs->regs[MIPSInst_RT(inst)] = res; 1999 MIPS_R2_STATS(llsc); 2000 2001 break; 2002 2003 case sc_op: 2004 vaddr = regs->regs[MIPSInst_RS(inst)] + MIPSInst_SIMM(inst); 2005 if (vaddr & 0x3) { 2006 current->thread.cp0_baduaddr = vaddr; 2007 err = SIGBUS; 2008 break; 2009 } 2010 if (!access_ok(VERIFY_WRITE, vaddr, 4)) { 2011 current->thread.cp0_baduaddr = vaddr; 2012 err = SIGBUS; 2013 break; 2014 } 2015 2016 if (!cpu_has_rw_llb) { 2017 /* 2018 * An LL/SC block can't be safely emulated without 2019 * a Config5/LLB availability. So it's probably time to 2020 * kill our process before things get any worse. This is 2021 * because Config5/LLB allows us to use ERETNC so that 2022 * the LLAddr/LLB bit is not cleared when we return from 2023 * an exception. MIPS R2 LL/SC instructions trap with an 2024 * RI exception so once we emulate them here, we return 2025 * back to userland with ERETNC. That preserves the 2026 * LLAddr/LLB so the subsequent SC instruction will 2027 * succeed preserving the atomic semantics of the LL/SC 2028 * block. Without that, there is no safe way to emulate 2029 * an LL/SC block in MIPSR2 userland. 2030 */ 2031 pr_err("Can't emulate MIPSR2 LL/SC without Config5/LLB\n"); 2032 err = SIGKILL; 2033 break; 2034 } 2035 2036 res = regs->regs[MIPSInst_RT(inst)]; 2037 2038 __asm__ __volatile__( 2039 "1:\n" 2040 "sc %0, 0(%2)\n" 2041 "2:\n" 2042 ".insn\n" 2043 ".section .fixup,\"ax\"\n" 2044 "3:\n" 2045 "li %1, %3\n" 2046 "j 2b\n" 2047 ".previous\n" 2048 ".section __ex_table,\"a\"\n" 2049 ".word 1b, 3b\n" 2050 ".previous\n" 2051 : "+&r"(res), "+&r"(err) 2052 : "r"(vaddr), "i"(SIGSEGV)); 2053 2054 if (MIPSInst_RT(inst) && !err) 2055 regs->regs[MIPSInst_RT(inst)] = res; 2056 2057 MIPS_R2_STATS(llsc); 2058 2059 break; 2060 2061 case lld_op: 2062 if (config_enabled(CONFIG_32BIT)) { 2063 err = SIGILL; 2064 break; 2065 } 2066 2067 vaddr = regs->regs[MIPSInst_RS(inst)] + MIPSInst_SIMM(inst); 2068 if (vaddr & 0x7) { 2069 current->thread.cp0_baduaddr = vaddr; 2070 err = SIGBUS; 2071 break; 2072 } 2073 if (!access_ok(VERIFY_READ, vaddr, 8)) { 2074 current->thread.cp0_baduaddr = vaddr; 2075 err = SIGBUS; 2076 break; 2077 } 2078 2079 if (!cpu_has_rw_llb) { 2080 /* 2081 * An LL/SC block can't be safely emulated without 2082 * a Config5/LLB availability. So it's probably time to 2083 * kill our process before things get any worse. This is 2084 * because Config5/LLB allows us to use ERETNC so that 2085 * the LLAddr/LLB bit is not cleared when we return from 2086 * an exception. MIPS R2 LL/SC instructions trap with an 2087 * RI exception so once we emulate them here, we return 2088 * back to userland with ERETNC. That preserves the 2089 * LLAddr/LLB so the subsequent SC instruction will 2090 * succeed preserving the atomic semantics of the LL/SC 2091 * block. Without that, there is no safe way to emulate 2092 * an LL/SC block in MIPSR2 userland. 2093 */ 2094 pr_err("Can't emulate MIPSR2 LL/SC without Config5/LLB\n"); 2095 err = SIGKILL; 2096 break; 2097 } 2098 2099 __asm__ __volatile__( 2100 "1:\n" 2101 "lld %0, 0(%2)\n" 2102 "2:\n" 2103 ".insn\n" 2104 ".section .fixup,\"ax\"\n" 2105 "3:\n" 2106 "li %1, %3\n" 2107 "j 2b\n" 2108 ".previous\n" 2109 ".section __ex_table,\"a\"\n" 2110 ".word 1b, 3b\n" 2111 ".previous\n" 2112 : "=&r"(res), "+&r"(err) 2113 : "r"(vaddr), "i"(SIGSEGV) 2114 : "memory"); 2115 if (MIPSInst_RT(inst) && !err) 2116 regs->regs[MIPSInst_RT(inst)] = res; 2117 2118 MIPS_R2_STATS(llsc); 2119 2120 break; 2121 2122 case scd_op: 2123 if (config_enabled(CONFIG_32BIT)) { 2124 err = SIGILL; 2125 break; 2126 } 2127 2128 vaddr = regs->regs[MIPSInst_RS(inst)] + MIPSInst_SIMM(inst); 2129 if (vaddr & 0x7) { 2130 current->thread.cp0_baduaddr = vaddr; 2131 err = SIGBUS; 2132 break; 2133 } 2134 if (!access_ok(VERIFY_WRITE, vaddr, 8)) { 2135 current->thread.cp0_baduaddr = vaddr; 2136 err = SIGBUS; 2137 break; 2138 } 2139 2140 if (!cpu_has_rw_llb) { 2141 /* 2142 * An LL/SC block can't be safely emulated without 2143 * a Config5/LLB availability. So it's probably time to 2144 * kill our process before things get any worse. This is 2145 * because Config5/LLB allows us to use ERETNC so that 2146 * the LLAddr/LLB bit is not cleared when we return from 2147 * an exception. MIPS R2 LL/SC instructions trap with an 2148 * RI exception so once we emulate them here, we return 2149 * back to userland with ERETNC. That preserves the 2150 * LLAddr/LLB so the subsequent SC instruction will 2151 * succeed preserving the atomic semantics of the LL/SC 2152 * block. Without that, there is no safe way to emulate 2153 * an LL/SC block in MIPSR2 userland. 2154 */ 2155 pr_err("Can't emulate MIPSR2 LL/SC without Config5/LLB\n"); 2156 err = SIGKILL; 2157 break; 2158 } 2159 2160 res = regs->regs[MIPSInst_RT(inst)]; 2161 2162 __asm__ __volatile__( 2163 "1:\n" 2164 "scd %0, 0(%2)\n" 2165 "2:\n" 2166 ".insn\n" 2167 ".section .fixup,\"ax\"\n" 2168 "3:\n" 2169 "li %1, %3\n" 2170 "j 2b\n" 2171 ".previous\n" 2172 ".section __ex_table,\"a\"\n" 2173 ".word 1b, 3b\n" 2174 ".previous\n" 2175 : "+&r"(res), "+&r"(err) 2176 : "r"(vaddr), "i"(SIGSEGV)); 2177 2178 if (MIPSInst_RT(inst) && !err) 2179 regs->regs[MIPSInst_RT(inst)] = res; 2180 2181 MIPS_R2_STATS(llsc); 2182 2183 break; 2184 case pref_op: 2185 /* skip it */ 2186 break; 2187 default: 2188 err = SIGILL; 2189 } 2190 2191 /* 2192 * Lets not return to userland just yet. It's constly and 2193 * it's likely we have more R2 instructions to emulate 2194 */ 2195 if (!err && (pass++ < MIPS_R2_EMUL_TOTAL_PASS)) { 2196 regs->cp0_cause &= ~CAUSEF_BD; 2197 err = get_user(inst, (u32 __user *)regs->cp0_epc); 2198 if (!err) 2199 goto repeat; 2200 2201 if (err < 0) 2202 err = SIGSEGV; 2203 } 2204 2205 if (err && (err != SIGEMT)) { 2206 regs->regs[31] = r31; 2207 regs->cp0_epc = epc; 2208 } 2209 2210 /* Likely a MIPS R6 compatible instruction */ 2211 if (pass && (err == SIGILL)) 2212 err = 0; 2213 2214 return err; 2215 } 2216 2217 #ifdef CONFIG_DEBUG_FS 2218 2219 static int mipsr2_stats_show(struct seq_file *s, void *unused) 2220 { 2221 2222 seq_printf(s, "Instruction\tTotal\tBDslot\n------------------------------\n"); 2223 seq_printf(s, "movs\t\t%ld\t%ld\n", 2224 (unsigned long)__this_cpu_read(mipsr2emustats.movs), 2225 (unsigned long)__this_cpu_read(mipsr2bdemustats.movs)); 2226 seq_printf(s, "hilo\t\t%ld\t%ld\n", 2227 (unsigned long)__this_cpu_read(mipsr2emustats.hilo), 2228 (unsigned long)__this_cpu_read(mipsr2bdemustats.hilo)); 2229 seq_printf(s, "muls\t\t%ld\t%ld\n", 2230 (unsigned long)__this_cpu_read(mipsr2emustats.muls), 2231 (unsigned long)__this_cpu_read(mipsr2bdemustats.muls)); 2232 seq_printf(s, "divs\t\t%ld\t%ld\n", 2233 (unsigned long)__this_cpu_read(mipsr2emustats.divs), 2234 (unsigned long)__this_cpu_read(mipsr2bdemustats.divs)); 2235 seq_printf(s, "dsps\t\t%ld\t%ld\n", 2236 (unsigned long)__this_cpu_read(mipsr2emustats.dsps), 2237 (unsigned long)__this_cpu_read(mipsr2bdemustats.dsps)); 2238 seq_printf(s, "bops\t\t%ld\t%ld\n", 2239 (unsigned long)__this_cpu_read(mipsr2emustats.bops), 2240 (unsigned long)__this_cpu_read(mipsr2bdemustats.bops)); 2241 seq_printf(s, "traps\t\t%ld\t%ld\n", 2242 (unsigned long)__this_cpu_read(mipsr2emustats.traps), 2243 (unsigned long)__this_cpu_read(mipsr2bdemustats.traps)); 2244 seq_printf(s, "fpus\t\t%ld\t%ld\n", 2245 (unsigned long)__this_cpu_read(mipsr2emustats.fpus), 2246 (unsigned long)__this_cpu_read(mipsr2bdemustats.fpus)); 2247 seq_printf(s, "loads\t\t%ld\t%ld\n", 2248 (unsigned long)__this_cpu_read(mipsr2emustats.loads), 2249 (unsigned long)__this_cpu_read(mipsr2bdemustats.loads)); 2250 seq_printf(s, "stores\t\t%ld\t%ld\n", 2251 (unsigned long)__this_cpu_read(mipsr2emustats.stores), 2252 (unsigned long)__this_cpu_read(mipsr2bdemustats.stores)); 2253 seq_printf(s, "llsc\t\t%ld\t%ld\n", 2254 (unsigned long)__this_cpu_read(mipsr2emustats.llsc), 2255 (unsigned long)__this_cpu_read(mipsr2bdemustats.llsc)); 2256 seq_printf(s, "dsemul\t\t%ld\t%ld\n", 2257 (unsigned long)__this_cpu_read(mipsr2emustats.dsemul), 2258 (unsigned long)__this_cpu_read(mipsr2bdemustats.dsemul)); 2259 seq_printf(s, "jr\t\t%ld\n", 2260 (unsigned long)__this_cpu_read(mipsr2bremustats.jrs)); 2261 seq_printf(s, "bltzl\t\t%ld\n", 2262 (unsigned long)__this_cpu_read(mipsr2bremustats.bltzl)); 2263 seq_printf(s, "bgezl\t\t%ld\n", 2264 (unsigned long)__this_cpu_read(mipsr2bremustats.bgezl)); 2265 seq_printf(s, "bltzll\t\t%ld\n", 2266 (unsigned long)__this_cpu_read(mipsr2bremustats.bltzll)); 2267 seq_printf(s, "bgezll\t\t%ld\n", 2268 (unsigned long)__this_cpu_read(mipsr2bremustats.bgezll)); 2269 seq_printf(s, "bltzal\t\t%ld\n", 2270 (unsigned long)__this_cpu_read(mipsr2bremustats.bltzal)); 2271 seq_printf(s, "bgezal\t\t%ld\n", 2272 (unsigned long)__this_cpu_read(mipsr2bremustats.bgezal)); 2273 seq_printf(s, "beql\t\t%ld\n", 2274 (unsigned long)__this_cpu_read(mipsr2bremustats.beql)); 2275 seq_printf(s, "bnel\t\t%ld\n", 2276 (unsigned long)__this_cpu_read(mipsr2bremustats.bnel)); 2277 seq_printf(s, "blezl\t\t%ld\n", 2278 (unsigned long)__this_cpu_read(mipsr2bremustats.blezl)); 2279 seq_printf(s, "bgtzl\t\t%ld\n", 2280 (unsigned long)__this_cpu_read(mipsr2bremustats.bgtzl)); 2281 2282 return 0; 2283 } 2284 2285 static int mipsr2_stats_clear_show(struct seq_file *s, void *unused) 2286 { 2287 mipsr2_stats_show(s, unused); 2288 2289 __this_cpu_write((mipsr2emustats).movs, 0); 2290 __this_cpu_write((mipsr2bdemustats).movs, 0); 2291 __this_cpu_write((mipsr2emustats).hilo, 0); 2292 __this_cpu_write((mipsr2bdemustats).hilo, 0); 2293 __this_cpu_write((mipsr2emustats).muls, 0); 2294 __this_cpu_write((mipsr2bdemustats).muls, 0); 2295 __this_cpu_write((mipsr2emustats).divs, 0); 2296 __this_cpu_write((mipsr2bdemustats).divs, 0); 2297 __this_cpu_write((mipsr2emustats).dsps, 0); 2298 __this_cpu_write((mipsr2bdemustats).dsps, 0); 2299 __this_cpu_write((mipsr2emustats).bops, 0); 2300 __this_cpu_write((mipsr2bdemustats).bops, 0); 2301 __this_cpu_write((mipsr2emustats).traps, 0); 2302 __this_cpu_write((mipsr2bdemustats).traps, 0); 2303 __this_cpu_write((mipsr2emustats).fpus, 0); 2304 __this_cpu_write((mipsr2bdemustats).fpus, 0); 2305 __this_cpu_write((mipsr2emustats).loads, 0); 2306 __this_cpu_write((mipsr2bdemustats).loads, 0); 2307 __this_cpu_write((mipsr2emustats).stores, 0); 2308 __this_cpu_write((mipsr2bdemustats).stores, 0); 2309 __this_cpu_write((mipsr2emustats).llsc, 0); 2310 __this_cpu_write((mipsr2bdemustats).llsc, 0); 2311 __this_cpu_write((mipsr2emustats).dsemul, 0); 2312 __this_cpu_write((mipsr2bdemustats).dsemul, 0); 2313 __this_cpu_write((mipsr2bremustats).jrs, 0); 2314 __this_cpu_write((mipsr2bremustats).bltzl, 0); 2315 __this_cpu_write((mipsr2bremustats).bgezl, 0); 2316 __this_cpu_write((mipsr2bremustats).bltzll, 0); 2317 __this_cpu_write((mipsr2bremustats).bgezll, 0); 2318 __this_cpu_write((mipsr2bremustats).bltzal, 0); 2319 __this_cpu_write((mipsr2bremustats).bgezal, 0); 2320 __this_cpu_write((mipsr2bremustats).beql, 0); 2321 __this_cpu_write((mipsr2bremustats).bnel, 0); 2322 __this_cpu_write((mipsr2bremustats).blezl, 0); 2323 __this_cpu_write((mipsr2bremustats).bgtzl, 0); 2324 2325 return 0; 2326 } 2327 2328 static int mipsr2_stats_open(struct inode *inode, struct file *file) 2329 { 2330 return single_open(file, mipsr2_stats_show, inode->i_private); 2331 } 2332 2333 static int mipsr2_stats_clear_open(struct inode *inode, struct file *file) 2334 { 2335 return single_open(file, mipsr2_stats_clear_show, inode->i_private); 2336 } 2337 2338 static const struct file_operations mipsr2_emul_fops = { 2339 .open = mipsr2_stats_open, 2340 .read = seq_read, 2341 .llseek = seq_lseek, 2342 .release = single_release, 2343 }; 2344 2345 static const struct file_operations mipsr2_clear_fops = { 2346 .open = mipsr2_stats_clear_open, 2347 .read = seq_read, 2348 .llseek = seq_lseek, 2349 .release = single_release, 2350 }; 2351 2352 2353 static int __init mipsr2_init_debugfs(void) 2354 { 2355 extern struct dentry *mips_debugfs_dir; 2356 struct dentry *mipsr2_emul; 2357 2358 if (!mips_debugfs_dir) 2359 return -ENODEV; 2360 2361 mipsr2_emul = debugfs_create_file("r2_emul_stats", S_IRUGO, 2362 mips_debugfs_dir, NULL, 2363 &mipsr2_emul_fops); 2364 if (!mipsr2_emul) 2365 return -ENOMEM; 2366 2367 mipsr2_emul = debugfs_create_file("r2_emul_stats_clear", S_IRUGO, 2368 mips_debugfs_dir, NULL, 2369 &mipsr2_clear_fops); 2370 if (!mipsr2_emul) 2371 return -ENOMEM; 2372 2373 return 0; 2374 } 2375 2376 device_initcall(mipsr2_init_debugfs); 2377 2378 #endif /* CONFIG_DEBUG_FS */ 2379