1 /* 2 * General MIPS MT support routines, usable in AP/SP, SMVP, or SMTC kernels 3 * Copyright (C) 2005 Mips Technologies, Inc 4 */ 5 6 #include <linux/kernel.h> 7 #include <linux/sched.h> 8 #include <linux/cpumask.h> 9 #include <linux/interrupt.h> 10 #include <linux/security.h> 11 12 #include <asm/cpu.h> 13 #include <asm/processor.h> 14 #include <asm/atomic.h> 15 #include <asm/system.h> 16 #include <asm/hardirq.h> 17 #include <asm/mmu_context.h> 18 #include <asm/smp.h> 19 #include <asm/mipsmtregs.h> 20 #include <asm/r4kcache.h> 21 #include <asm/cacheflush.h> 22 23 /* 24 * CPU mask used to set process affinity for MT VPEs/TCs with FPUs 25 */ 26 27 cpumask_t mt_fpu_cpumask; 28 29 #ifdef CONFIG_MIPS_MT_FPAFF 30 31 #include <linux/cpu.h> 32 #include <linux/delay.h> 33 #include <asm/uaccess.h> 34 35 unsigned long mt_fpemul_threshold = 0; 36 37 /* 38 * Replacement functions for the sys_sched_setaffinity() and 39 * sys_sched_getaffinity() system calls, so that we can integrate 40 * FPU affinity with the user's requested processor affinity. 41 * This code is 98% identical with the sys_sched_setaffinity() 42 * and sys_sched_getaffinity() system calls, and should be 43 * updated when kernel/sched.c changes. 44 */ 45 46 /* 47 * find_process_by_pid - find a process with a matching PID value. 48 * used in sys_sched_set/getaffinity() in kernel/sched.c, so 49 * cloned here. 50 */ 51 static inline struct task_struct *find_process_by_pid(pid_t pid) 52 { 53 return pid ? find_task_by_pid(pid) : current; 54 } 55 56 57 /* 58 * mipsmt_sys_sched_setaffinity - set the cpu affinity of a process 59 */ 60 asmlinkage long mipsmt_sys_sched_setaffinity(pid_t pid, unsigned int len, 61 unsigned long __user *user_mask_ptr) 62 { 63 cpumask_t new_mask; 64 cpumask_t effective_mask; 65 int retval; 66 struct task_struct *p; 67 68 if (len < sizeof(new_mask)) 69 return -EINVAL; 70 71 if (copy_from_user(&new_mask, user_mask_ptr, sizeof(new_mask))) 72 return -EFAULT; 73 74 lock_cpu_hotplug(); 75 read_lock(&tasklist_lock); 76 77 p = find_process_by_pid(pid); 78 if (!p) { 79 read_unlock(&tasklist_lock); 80 unlock_cpu_hotplug(); 81 return -ESRCH; 82 } 83 84 /* 85 * It is not safe to call set_cpus_allowed with the 86 * tasklist_lock held. We will bump the task_struct's 87 * usage count and drop tasklist_lock before invoking 88 * set_cpus_allowed. 89 */ 90 get_task_struct(p); 91 92 retval = -EPERM; 93 if ((current->euid != p->euid) && (current->euid != p->uid) && 94 !capable(CAP_SYS_NICE)) { 95 read_unlock(&tasklist_lock); 96 goto out_unlock; 97 } 98 99 retval = security_task_setscheduler(p, 0, NULL); 100 if (retval) 101 goto out_unlock; 102 103 /* Record new user-specified CPU set for future reference */ 104 p->thread.user_cpus_allowed = new_mask; 105 106 /* Unlock the task list */ 107 read_unlock(&tasklist_lock); 108 109 /* Compute new global allowed CPU set if necessary */ 110 if( (p->thread.mflags & MF_FPUBOUND) 111 && cpus_intersects(new_mask, mt_fpu_cpumask)) { 112 cpus_and(effective_mask, new_mask, mt_fpu_cpumask); 113 retval = set_cpus_allowed(p, effective_mask); 114 } else { 115 p->thread.mflags &= ~MF_FPUBOUND; 116 retval = set_cpus_allowed(p, new_mask); 117 } 118 119 120 out_unlock: 121 put_task_struct(p); 122 unlock_cpu_hotplug(); 123 return retval; 124 } 125 126 /* 127 * mipsmt_sys_sched_getaffinity - get the cpu affinity of a process 128 */ 129 asmlinkage long mipsmt_sys_sched_getaffinity(pid_t pid, unsigned int len, 130 unsigned long __user *user_mask_ptr) 131 { 132 unsigned int real_len; 133 cpumask_t mask; 134 int retval; 135 struct task_struct *p; 136 137 real_len = sizeof(mask); 138 if (len < real_len) 139 return -EINVAL; 140 141 lock_cpu_hotplug(); 142 read_lock(&tasklist_lock); 143 144 retval = -ESRCH; 145 p = find_process_by_pid(pid); 146 if (!p) 147 goto out_unlock; 148 retval = security_task_getscheduler(p); 149 if (retval) 150 goto out_unlock; 151 152 cpus_and(mask, p->thread.user_cpus_allowed, cpu_possible_map); 153 154 out_unlock: 155 read_unlock(&tasklist_lock); 156 unlock_cpu_hotplug(); 157 if (retval) 158 return retval; 159 if (copy_to_user(user_mask_ptr, &mask, real_len)) 160 return -EFAULT; 161 return real_len; 162 } 163 164 #endif /* CONFIG_MIPS_MT_FPAFF */ 165 166 /* 167 * Dump new MIPS MT state for the core. Does not leave TCs halted. 168 * Takes an argument which taken to be a pre-call MVPControl value. 169 */ 170 171 void mips_mt_regdump(unsigned long mvpctl) 172 { 173 unsigned long flags; 174 unsigned long vpflags; 175 unsigned long mvpconf0; 176 int nvpe; 177 int ntc; 178 int i; 179 int tc; 180 unsigned long haltval; 181 unsigned long tcstatval; 182 #ifdef CONFIG_MIPS_MT_SMTC 183 void smtc_soft_dump(void); 184 #endif /* CONFIG_MIPT_MT_SMTC */ 185 186 local_irq_save(flags); 187 vpflags = dvpe(); 188 printk("=== MIPS MT State Dump ===\n"); 189 printk("-- Global State --\n"); 190 printk(" MVPControl Passed: %08lx\n", mvpctl); 191 printk(" MVPControl Read: %08lx\n", vpflags); 192 printk(" MVPConf0 : %08lx\n", (mvpconf0 = read_c0_mvpconf0())); 193 nvpe = ((mvpconf0 & MVPCONF0_PVPE) >> MVPCONF0_PVPE_SHIFT) + 1; 194 ntc = ((mvpconf0 & MVPCONF0_PTC) >> MVPCONF0_PTC_SHIFT) + 1; 195 printk("-- per-VPE State --\n"); 196 for(i = 0; i < nvpe; i++) { 197 for(tc = 0; tc < ntc; tc++) { 198 settc(tc); 199 if((read_tc_c0_tcbind() & TCBIND_CURVPE) == i) { 200 printk(" VPE %d\n", i); 201 printk(" VPEControl : %08lx\n", read_vpe_c0_vpecontrol()); 202 printk(" VPEConf0 : %08lx\n", read_vpe_c0_vpeconf0()); 203 printk(" VPE%d.Status : %08lx\n", 204 i, read_vpe_c0_status()); 205 printk(" VPE%d.EPC : %08lx\n", i, read_vpe_c0_epc()); 206 printk(" VPE%d.Cause : %08lx\n", i, read_vpe_c0_cause()); 207 printk(" VPE%d.Config7 : %08lx\n", 208 i, read_vpe_c0_config7()); 209 break; /* Next VPE */ 210 } 211 } 212 } 213 printk("-- per-TC State --\n"); 214 for(tc = 0; tc < ntc; tc++) { 215 settc(tc); 216 if(read_tc_c0_tcbind() == read_c0_tcbind()) { 217 /* Are we dumping ourself? */ 218 haltval = 0; /* Then we're not halted, and mustn't be */ 219 tcstatval = flags; /* And pre-dump TCStatus is flags */ 220 printk(" TC %d (current TC with VPE EPC above)\n", tc); 221 } else { 222 haltval = read_tc_c0_tchalt(); 223 write_tc_c0_tchalt(1); 224 tcstatval = read_tc_c0_tcstatus(); 225 printk(" TC %d\n", tc); 226 } 227 printk(" TCStatus : %08lx\n", tcstatval); 228 printk(" TCBind : %08lx\n", read_tc_c0_tcbind()); 229 printk(" TCRestart : %08lx\n", read_tc_c0_tcrestart()); 230 printk(" TCHalt : %08lx\n", haltval); 231 printk(" TCContext : %08lx\n", read_tc_c0_tccontext()); 232 if (!haltval) 233 write_tc_c0_tchalt(0); 234 } 235 #ifdef CONFIG_MIPS_MT_SMTC 236 smtc_soft_dump(); 237 #endif /* CONFIG_MIPT_MT_SMTC */ 238 printk("===========================\n"); 239 evpe(vpflags); 240 local_irq_restore(flags); 241 } 242 243 static int mt_opt_norps = 0; 244 static int mt_opt_rpsctl = -1; 245 static int mt_opt_nblsu = -1; 246 static int mt_opt_forceconfig7 = 0; 247 static int mt_opt_config7 = -1; 248 249 static int __init rps_disable(char *s) 250 { 251 mt_opt_norps = 1; 252 return 1; 253 } 254 __setup("norps", rps_disable); 255 256 static int __init rpsctl_set(char *str) 257 { 258 get_option(&str, &mt_opt_rpsctl); 259 return 1; 260 } 261 __setup("rpsctl=", rpsctl_set); 262 263 static int __init nblsu_set(char *str) 264 { 265 get_option(&str, &mt_opt_nblsu); 266 return 1; 267 } 268 __setup("nblsu=", nblsu_set); 269 270 static int __init config7_set(char *str) 271 { 272 get_option(&str, &mt_opt_config7); 273 mt_opt_forceconfig7 = 1; 274 return 1; 275 } 276 __setup("config7=", config7_set); 277 278 /* Experimental cache flush control parameters that should go away some day */ 279 int mt_protiflush = 0; 280 int mt_protdflush = 0; 281 int mt_n_iflushes = 1; 282 int mt_n_dflushes = 1; 283 284 static int __init set_protiflush(char *s) 285 { 286 mt_protiflush = 1; 287 return 1; 288 } 289 __setup("protiflush", set_protiflush); 290 291 static int __init set_protdflush(char *s) 292 { 293 mt_protdflush = 1; 294 return 1; 295 } 296 __setup("protdflush", set_protdflush); 297 298 static int __init niflush(char *s) 299 { 300 get_option(&s, &mt_n_iflushes); 301 return 1; 302 } 303 __setup("niflush=", niflush); 304 305 static int __init ndflush(char *s) 306 { 307 get_option(&s, &mt_n_dflushes); 308 return 1; 309 } 310 __setup("ndflush=", ndflush); 311 #ifdef CONFIG_MIPS_MT_FPAFF 312 static int fpaff_threshold = -1; 313 314 static int __init fpaff_thresh(char *str) 315 { 316 get_option(&str, &fpaff_threshold); 317 return 1; 318 } 319 320 __setup("fpaff=", fpaff_thresh); 321 #endif /* CONFIG_MIPS_MT_FPAFF */ 322 323 static unsigned int itc_base = 0; 324 325 static int __init set_itc_base(char *str) 326 { 327 get_option(&str, &itc_base); 328 return 1; 329 } 330 331 __setup("itcbase=", set_itc_base); 332 333 void mips_mt_set_cpuoptions(void) 334 { 335 unsigned int oconfig7 = read_c0_config7(); 336 unsigned int nconfig7 = oconfig7; 337 338 if (mt_opt_norps) { 339 printk("\"norps\" option deprectated: use \"rpsctl=\"\n"); 340 } 341 if (mt_opt_rpsctl >= 0) { 342 printk("34K return prediction stack override set to %d.\n", 343 mt_opt_rpsctl); 344 if (mt_opt_rpsctl) 345 nconfig7 |= (1 << 2); 346 else 347 nconfig7 &= ~(1 << 2); 348 } 349 if (mt_opt_nblsu >= 0) { 350 printk("34K ALU/LSU sync override set to %d.\n", mt_opt_nblsu); 351 if (mt_opt_nblsu) 352 nconfig7 |= (1 << 5); 353 else 354 nconfig7 &= ~(1 << 5); 355 } 356 if (mt_opt_forceconfig7) { 357 printk("CP0.Config7 forced to 0x%08x.\n", mt_opt_config7); 358 nconfig7 = mt_opt_config7; 359 } 360 if (oconfig7 != nconfig7) { 361 __asm__ __volatile("sync"); 362 write_c0_config7(nconfig7); 363 ehb (); 364 printk("Config7: 0x%08x\n", read_c0_config7()); 365 } 366 367 /* Report Cache management debug options */ 368 if (mt_protiflush) 369 printk("I-cache flushes single-threaded\n"); 370 if (mt_protdflush) 371 printk("D-cache flushes single-threaded\n"); 372 if (mt_n_iflushes != 1) 373 printk("I-Cache Flushes Repeated %d times\n", mt_n_iflushes); 374 if (mt_n_dflushes != 1) 375 printk("D-Cache Flushes Repeated %d times\n", mt_n_dflushes); 376 377 #ifdef CONFIG_MIPS_MT_FPAFF 378 /* FPU Use Factor empirically derived from experiments on 34K */ 379 #define FPUSEFACTOR 333 380 381 if (fpaff_threshold >= 0) { 382 mt_fpemul_threshold = fpaff_threshold; 383 } else { 384 mt_fpemul_threshold = 385 (FPUSEFACTOR * (loops_per_jiffy/(500000/HZ))) / HZ; 386 } 387 printk("FPU Affinity set after %ld emulations\n", 388 mt_fpemul_threshold); 389 #endif /* CONFIG_MIPS_MT_FPAFF */ 390 391 if (itc_base != 0) { 392 /* 393 * Configure ITC mapping. This code is very 394 * specific to the 34K core family, which uses 395 * a special mode bit ("ITC") in the ErrCtl 396 * register to enable access to ITC control 397 * registers via cache "tag" operations. 398 */ 399 unsigned long ectlval; 400 unsigned long itcblkgrn; 401 402 /* ErrCtl register is known as "ecc" to Linux */ 403 ectlval = read_c0_ecc(); 404 write_c0_ecc(ectlval | (0x1 << 26)); 405 ehb(); 406 #define INDEX_0 (0x80000000) 407 #define INDEX_8 (0x80000008) 408 /* Read "cache tag" for Dcache pseudo-index 8 */ 409 cache_op(Index_Load_Tag_D, INDEX_8); 410 ehb(); 411 itcblkgrn = read_c0_dtaglo(); 412 itcblkgrn &= 0xfffe0000; 413 /* Set for 128 byte pitch of ITC cells */ 414 itcblkgrn |= 0x00000c00; 415 /* Stage in Tag register */ 416 write_c0_dtaglo(itcblkgrn); 417 ehb(); 418 /* Write out to ITU with CACHE op */ 419 cache_op(Index_Store_Tag_D, INDEX_8); 420 /* Now set base address, and turn ITC on with 0x1 bit */ 421 write_c0_dtaglo((itc_base & 0xfffffc00) | 0x1 ); 422 ehb(); 423 /* Write out to ITU with CACHE op */ 424 cache_op(Index_Store_Tag_D, INDEX_0); 425 write_c0_ecc(ectlval); 426 ehb(); 427 printk("Mapped %ld ITC cells starting at 0x%08x\n", 428 ((itcblkgrn & 0x7fe00000) >> 20), itc_base); 429 } 430 } 431 432 /* 433 * Function to protect cache flushes from concurrent execution 434 * depends on MP software model chosen. 435 */ 436 437 void mt_cflush_lockdown(void) 438 { 439 #ifdef CONFIG_MIPS_MT_SMTC 440 void smtc_cflush_lockdown(void); 441 442 smtc_cflush_lockdown(); 443 #endif /* CONFIG_MIPS_MT_SMTC */ 444 /* FILL IN VSMP and AP/SP VERSIONS HERE */ 445 } 446 447 void mt_cflush_release(void) 448 { 449 #ifdef CONFIG_MIPS_MT_SMTC 450 void smtc_cflush_release(void); 451 452 smtc_cflush_release(); 453 #endif /* CONFIG_MIPS_MT_SMTC */ 454 /* FILL IN VSMP and AP/SP VERSIONS HERE */ 455 } 456