xref: /linux/arch/mips/kernel/jump_label.c (revision 18f90d372cf35b387663f1567de701e5393f6eb5)
1 /*
2  * This file is subject to the terms and conditions of the GNU General Public
3  * License.  See the file "COPYING" in the main directory of this archive
4  * for more details.
5  *
6  * Copyright (c) 2010 Cavium Networks, Inc.
7  */
8 
9 #include <linux/jump_label.h>
10 #include <linux/kernel.h>
11 #include <linux/memory.h>
12 #include <linux/mutex.h>
13 #include <linux/types.h>
14 #include <linux/cpu.h>
15 
16 #include <asm/cacheflush.h>
17 #include <asm/inst.h>
18 
19 /*
20  * Define parameters for the standard MIPS and the microMIPS jump
21  * instruction encoding respectively:
22  *
23  * - the ISA bit of the target, either 0 or 1 respectively,
24  *
25  * - the amount the jump target address is shifted right to fit in the
26  *   immediate field of the machine instruction, either 2 or 1,
27  *
28  * - the mask determining the size of the jump region relative to the
29  *   delay-slot instruction, either 256MB or 128MB,
30  *
31  * - the jump target alignment, either 4 or 2 bytes.
32  */
33 #define J_ISA_BIT	IS_ENABLED(CONFIG_CPU_MICROMIPS)
34 #define J_RANGE_SHIFT	(2 - J_ISA_BIT)
35 #define J_RANGE_MASK	((1ul << (26 + J_RANGE_SHIFT)) - 1)
36 #define J_ALIGN_MASK	((1ul << J_RANGE_SHIFT) - 1)
37 
38 void arch_jump_label_transform(struct jump_entry *e,
39 			       enum jump_label_type type)
40 {
41 	union mips_instruction *insn_p;
42 	union mips_instruction insn;
43 
44 	insn_p = (union mips_instruction *)msk_isa16_mode(e->code);
45 
46 	/* Jump only works within an aligned region its delay slot is in. */
47 	BUG_ON((e->target & ~J_RANGE_MASK) != ((e->code + 4) & ~J_RANGE_MASK));
48 
49 	/* Target must have the right alignment and ISA must be preserved. */
50 	BUG_ON((e->target & J_ALIGN_MASK) != J_ISA_BIT);
51 
52 	if (type == JUMP_LABEL_JMP) {
53 		insn.j_format.opcode = J_ISA_BIT ? mm_j32_op : j_op;
54 		insn.j_format.target = e->target >> J_RANGE_SHIFT;
55 	} else {
56 		insn.word = 0; /* nop */
57 	}
58 
59 	mutex_lock(&text_mutex);
60 	if (IS_ENABLED(CONFIG_CPU_MICROMIPS)) {
61 		insn_p->halfword[0] = insn.word >> 16;
62 		insn_p->halfword[1] = insn.word;
63 	} else
64 		*insn_p = insn;
65 
66 	flush_icache_range((unsigned long)insn_p,
67 			   (unsigned long)insn_p + sizeof(*insn_p));
68 
69 	mutex_unlock(&text_mutex);
70 }
71