1 /* 2 * MIPS idle loop and WAIT instruction support. 3 * 4 * Copyright (C) xxxx the Anonymous 5 * Copyright (C) 1994 - 2006 Ralf Baechle 6 * Copyright (C) 2003, 2004 Maciej W. Rozycki 7 * Copyright (C) 2001, 2004, 2011, 2012 MIPS Technologies, Inc. 8 * 9 * This program is free software; you can redistribute it and/or 10 * modify it under the terms of the GNU General Public License 11 * as published by the Free Software Foundation; either version 12 * 2 of the License, or (at your option) any later version. 13 */ 14 #include <linux/export.h> 15 #include <linux/init.h> 16 #include <linux/irqflags.h> 17 #include <linux/printk.h> 18 #include <linux/sched.h> 19 #include <asm/cpu.h> 20 #include <asm/cpu-info.h> 21 #include <asm/cpu-type.h> 22 #include <asm/idle.h> 23 #include <asm/mipsregs.h> 24 25 /* 26 * Not all of the MIPS CPUs have the "wait" instruction available. Moreover, 27 * the implementation of the "wait" feature differs between CPU families. This 28 * points to the function that implements CPU specific wait. 29 * The wait instruction stops the pipeline and reduces the power consumption of 30 * the CPU very much. 31 */ 32 void (*cpu_wait)(void); 33 EXPORT_SYMBOL(cpu_wait); 34 35 static void r3081_wait(void) 36 { 37 unsigned long cfg = read_c0_conf(); 38 write_c0_conf(cfg | R30XX_CONF_HALT); 39 local_irq_enable(); 40 } 41 42 static void r39xx_wait(void) 43 { 44 if (!need_resched()) 45 write_c0_conf(read_c0_conf() | TX39_CONF_HALT); 46 local_irq_enable(); 47 } 48 49 void r4k_wait(void) 50 { 51 local_irq_enable(); 52 __r4k_wait(); 53 } 54 55 /* 56 * This variant is preferable as it allows testing need_resched and going to 57 * sleep depending on the outcome atomically. Unfortunately the "It is 58 * implementation-dependent whether the pipeline restarts when a non-enabled 59 * interrupt is requested" restriction in the MIPS32/MIPS64 architecture makes 60 * using this version a gamble. 61 */ 62 void r4k_wait_irqoff(void) 63 { 64 if (!need_resched()) 65 __asm__( 66 " .set push \n" 67 " .set arch=r4000 \n" 68 " wait \n" 69 " .set pop \n"); 70 local_irq_enable(); 71 } 72 73 /* 74 * The RM7000 variant has to handle erratum 38. The workaround is to not 75 * have any pending stores when the WAIT instruction is executed. 76 */ 77 static void rm7k_wait_irqoff(void) 78 { 79 if (!need_resched()) 80 __asm__( 81 " .set push \n" 82 " .set arch=r4000 \n" 83 " .set noat \n" 84 " mfc0 $1, $12 \n" 85 " sync \n" 86 " mtc0 $1, $12 # stalls until W stage \n" 87 " wait \n" 88 " mtc0 $1, $12 # stalls until W stage \n" 89 " .set pop \n"); 90 local_irq_enable(); 91 } 92 93 /* 94 * Au1 'wait' is only useful when the 32kHz counter is used as timer, 95 * since coreclock (and the cp0 counter) stops upon executing it. Only an 96 * interrupt can wake it, so they must be enabled before entering idle modes. 97 */ 98 static void au1k_wait(void) 99 { 100 unsigned long c0status = read_c0_status() | 1; /* irqs on */ 101 102 __asm__( 103 " .set arch=r4000 \n" 104 " cache 0x14, 0(%0) \n" 105 " cache 0x14, 32(%0) \n" 106 " sync \n" 107 " mtc0 %1, $12 \n" /* wr c0status */ 108 " wait \n" 109 " nop \n" 110 " nop \n" 111 " nop \n" 112 " nop \n" 113 " .set mips0 \n" 114 : : "r" (au1k_wait), "r" (c0status)); 115 } 116 117 static int __initdata nowait; 118 119 static int __init wait_disable(char *s) 120 { 121 nowait = 1; 122 123 return 1; 124 } 125 126 __setup("nowait", wait_disable); 127 128 void __init check_wait(void) 129 { 130 struct cpuinfo_mips *c = ¤t_cpu_data; 131 132 if (nowait) { 133 printk("Wait instruction disabled.\n"); 134 return; 135 } 136 137 switch (current_cpu_type()) { 138 case CPU_R3081: 139 case CPU_R3081E: 140 cpu_wait = r3081_wait; 141 break; 142 case CPU_TX3927: 143 cpu_wait = r39xx_wait; 144 break; 145 case CPU_R4200: 146 /* case CPU_R4300: */ 147 case CPU_R4600: 148 case CPU_R4640: 149 case CPU_R4650: 150 case CPU_R4700: 151 case CPU_R5000: 152 case CPU_R5500: 153 case CPU_NEVADA: 154 case CPU_4KC: 155 case CPU_4KEC: 156 case CPU_4KSC: 157 case CPU_5KC: 158 case CPU_25KF: 159 case CPU_PR4450: 160 case CPU_BMIPS3300: 161 case CPU_BMIPS4350: 162 case CPU_BMIPS4380: 163 case CPU_BMIPS5000: 164 case CPU_CAVIUM_OCTEON: 165 case CPU_CAVIUM_OCTEON_PLUS: 166 case CPU_CAVIUM_OCTEON2: 167 case CPU_CAVIUM_OCTEON3: 168 case CPU_JZRISC: 169 case CPU_LOONGSON1: 170 case CPU_XLR: 171 case CPU_XLP: 172 cpu_wait = r4k_wait; 173 break; 174 175 case CPU_RM7000: 176 cpu_wait = rm7k_wait_irqoff; 177 break; 178 179 case CPU_M14KC: 180 case CPU_M14KEC: 181 case CPU_24K: 182 case CPU_34K: 183 case CPU_1004K: 184 case CPU_1074K: 185 case CPU_INTERAPTIV: 186 case CPU_PROAPTIV: 187 case CPU_P5600: 188 case CPU_M5150: 189 cpu_wait = r4k_wait; 190 if (read_c0_config7() & MIPS_CONF7_WII) 191 cpu_wait = r4k_wait_irqoff; 192 break; 193 194 case CPU_74K: 195 cpu_wait = r4k_wait; 196 if ((c->processor_id & 0xff) >= PRID_REV_ENCODE_332(2, 1, 0)) 197 cpu_wait = r4k_wait_irqoff; 198 break; 199 200 case CPU_TX49XX: 201 cpu_wait = r4k_wait_irqoff; 202 break; 203 case CPU_ALCHEMY: 204 cpu_wait = au1k_wait; 205 break; 206 case CPU_20KC: 207 /* 208 * WAIT on Rev1.0 has E1, E2, E3 and E16. 209 * WAIT on Rev2.0 and Rev3.0 has E16. 210 * Rev3.1 WAIT is nop, why bother 211 */ 212 if ((c->processor_id & 0xff) <= 0x64) 213 break; 214 215 /* 216 * Another rev is incremeting c0_count at a reduced clock 217 * rate while in WAIT mode. So we basically have the choice 218 * between using the cp0 timer as clocksource or avoiding 219 * the WAIT instruction. Until more details are known, 220 * disable the use of WAIT for 20Kc entirely. 221 cpu_wait = r4k_wait; 222 */ 223 break; 224 default: 225 break; 226 } 227 } 228 229 void arch_cpu_idle(void) 230 { 231 if (cpu_wait) 232 cpu_wait(); 233 else 234 local_irq_enable(); 235 } 236 237 #ifdef CONFIG_CPU_IDLE 238 239 int mips_cpuidle_wait_enter(struct cpuidle_device *dev, 240 struct cpuidle_driver *drv, int index) 241 { 242 arch_cpu_idle(); 243 return index; 244 } 245 246 #endif 247