xref: /linux/arch/mips/kernel/head.S (revision 14b42963f64b98ab61fa9723c03d71aa5ef4f862) 
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License.  See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 1994, 1995 Waldorf Electronics
7 * Written by Ralf Baechle and Andreas Busse
8 * Copyright (C) 1994, 95, 96, 97, 98, 99, 2003 Ralf Baechle
9 * Copyright (C) 1996 Paul M. Antoine
10 * Modified for DECStation and hence R3000 support by Paul M. Antoine
11 * Further modifications by David S. Miller and Harald Koerfgen
12 * Copyright (C) 1999 Silicon Graphics, Inc.
13 * Kevin Kissell, kevink@mips.com and Carsten Langgaard, carstenl@mips.com
14 * Copyright (C) 2000 MIPS Technologies, Inc.  All rights reserved.
15 */
16#include <linux/init.h>
17#include <linux/threads.h>
18
19#include <asm/asm.h>
20#include <asm/asmmacro.h>
21#include <asm/regdef.h>
22#include <asm/page.h>
23#include <asm/mipsregs.h>
24#include <asm/stackframe.h>
25
26#include <kernel-entry-init.h>
27
28	.macro	ARC64_TWIDDLE_PC
29#if defined(CONFIG_ARC64) || defined(CONFIG_MAPPED_KERNEL)
30	/* We get launched at a XKPHYS address but the kernel is linked to
31	   run at a KSEG0 address, so jump there.  */
32	PTR_LA	t0, \@f
33	jr	t0
34\@:
35#endif
36	.endm
37
38	/*
39	 * inputs are the text nasid in t1, data nasid in t2.
40	 */
41	.macro MAPPED_KERNEL_SETUP_TLB
42#ifdef CONFIG_MAPPED_KERNEL
43	/*
44	 * This needs to read the nasid - assume 0 for now.
45	 * Drop in 0xffffffffc0000000 in tlbhi, 0+VG in tlblo_0,
46	 * 0+DVG in tlblo_1.
47	 */
48	dli	t0, 0xffffffffc0000000
49	dmtc0	t0, CP0_ENTRYHI
50	li	t0, 0x1c000		# Offset of text into node memory
51	dsll	t1, NASID_SHFT		# Shift text nasid into place
52	dsll	t2, NASID_SHFT		# Same for data nasid
53	or	t1, t1, t0		# Physical load address of kernel text
54	or	t2, t2, t0		# Physical load address of kernel data
55	dsrl	t1, 12			# 4K pfn
56	dsrl	t2, 12			# 4K pfn
57	dsll	t1, 6			# Get pfn into place
58	dsll	t2, 6			# Get pfn into place
59	li	t0, ((_PAGE_GLOBAL|_PAGE_VALID| _CACHE_CACHABLE_COW) >> 6)
60	or	t0, t0, t1
61	mtc0	t0, CP0_ENTRYLO0	# physaddr, VG, cach exlwr
62	li	t0, ((_PAGE_GLOBAL|_PAGE_VALID| _PAGE_DIRTY|_CACHE_CACHABLE_COW) >> 6)
63	or	t0, t0, t2
64	mtc0	t0, CP0_ENTRYLO1	# physaddr, DVG, cach exlwr
65	li	t0, 0x1ffe000		# MAPPED_KERN_TLBMASK, TLBPGMASK_16M
66	mtc0	t0, CP0_PAGEMASK
67	li	t0, 0			# KMAP_INX
68	mtc0	t0, CP0_INDEX
69	li	t0, 1
70	mtc0	t0, CP0_WIRED
71	tlbwi
72#else
73	mtc0	zero, CP0_WIRED
74#endif
75	.endm
76
77	/*
78	 * For the moment disable interrupts, mark the kernel mode and
79	 * set ST0_KX so that the CPU does not spit fire when using
80	 * 64-bit addresses.  A full initialization of the CPU's status
81	 * register is done later in per_cpu_trap_init().
82	 */
83	.macro	setup_c0_status set clr
84	.set	push
85#ifdef CONFIG_MIPS_MT_SMTC
86	/*
87	 * For SMTC, we need to set privilege and disable interrupts only for
88	 * the current TC, using the TCStatus register.
89	 */
90	mfc0	t0, CP0_TCSTATUS
91	/* Fortunately CU 0 is in the same place in both registers */
92	/* Set TCU0, TMX, TKSU (for later inversion) and IXMT */
93	li	t1, ST0_CU0 | 0x08001c00
94	or	t0, t1
95	/* Clear TKSU, leave IXMT */
96	xori	t0, 0x00001800
97	mtc0	t0, CP0_TCSTATUS
98	_ehb
99	/* We need to leave the global IE bit set, but clear EXL...*/
100	mfc0	t0, CP0_STATUS
101	or	t0, ST0_CU0 | ST0_EXL | ST0_ERL | \set | \clr
102	xor	t0, ST0_EXL | ST0_ERL | \clr
103	mtc0	t0, CP0_STATUS
104#else
105	mfc0	t0, CP0_STATUS
106	or	t0, ST0_CU0|\set|0x1f|\clr
107	xor	t0, 0x1f|\clr
108	mtc0	t0, CP0_STATUS
109	.set	noreorder
110	sll	zero,3				# ehb
111#endif
112	.set	pop
113	.endm
114
115	.macro	setup_c0_status_pri
116#ifdef CONFIG_64BIT
117	setup_c0_status ST0_KX 0
118#else
119	setup_c0_status 0 0
120#endif
121	.endm
122
123	.macro	setup_c0_status_sec
124#ifdef CONFIG_64BIT
125	setup_c0_status ST0_KX ST0_BEV
126#else
127	setup_c0_status 0 ST0_BEV
128#endif
129	.endm
130
131	/*
132	 * Reserved space for exception handlers.
133	 * Necessary for machines which link their kernels at KSEG0.
134	 */
135	.fill	0x400
136
137EXPORT(stext)					# used for profiling
138EXPORT(_stext)
139
140#if defined(CONFIG_QEMU) || defined(CONFIG_MIPS_SIM)
141	/*
142	 * Give us a fighting chance of running if execution beings at the
143	 * kernel load address.  This is needed because this platform does
144	 * not have a ELF loader yet.
145	 */
146	j	kernel_entry
147#endif
148	__INIT
149
150NESTED(kernel_entry, 16, sp)			# kernel entry point
151
152	kernel_entry_setup			# cpu specific setup
153
154	setup_c0_status_pri
155
156	ARC64_TWIDDLE_PC
157
158#ifdef CONFIG_MIPS_MT_SMTC
159	/*
160	 * In SMTC kernel, "CLI" is thread-specific, in TCStatus.
161	 * We still need to enable interrupts globally in Status,
162	 * and clear EXL/ERL.
163	 *
164	 * TCContext is used to track interrupt levels under
165	 * service in SMTC kernel. Clear for boot TC before
166	 * allowing any interrupts.
167	 */
168	mtc0	zero, CP0_TCCONTEXT
169
170	mfc0	t0, CP0_STATUS
171	ori	t0, t0, 0xff1f
172	xori	t0, t0, 0x001e
173	mtc0	t0, CP0_STATUS
174#endif /* CONFIG_MIPS_MT_SMTC */
175
176	PTR_LA		t0, __bss_start		# clear .bss
177	LONG_S		zero, (t0)
178	PTR_LA		t1, __bss_stop - LONGSIZE
1791:
180	PTR_ADDIU	t0, LONGSIZE
181	LONG_S		zero, (t0)
182	bne		t0, t1, 1b
183
184	LONG_S		a0, fw_arg0		# firmware arguments
185	LONG_S		a1, fw_arg1
186	LONG_S		a2, fw_arg2
187	LONG_S		a3, fw_arg3
188
189	MTC0		zero, CP0_CONTEXT	# clear context register
190	PTR_LA		$28, init_thread_union
191	PTR_ADDIU	sp, $28, _THREAD_SIZE - 32
192	set_saved_sp	sp, t0, t1
193	PTR_SUBU	sp, 4 * SZREG		# init stack pointer
194
195	j		start_kernel
196	END(kernel_entry)
197
198#ifdef CONFIG_QEMU
199	__INIT
200#endif
201
202#ifdef CONFIG_SMP
203/*
204 * SMP slave cpus entry point.  Board specific code for bootstrap calls this
205 * function after setting up the stack and gp registers.
206 */
207NESTED(smp_bootstrap, 16, sp)
208#ifdef CONFIG_MIPS_MT_SMTC
209	/*
210	 * Read-modify-writes of Status must be atomic, and this
211	 * is one case where CLI is invoked without EXL being
212	 * necessarily set. The CLI and setup_c0_status will
213	 * in fact be redundant for all but the first TC of
214	 * each VPE being booted.
215	 */
216	DMT	10	# dmt t2 /* t0, t1 are used by CLI and setup_c0_status() */
217	jal	mips_ihb
218#endif /* CONFIG_MIPS_MT_SMTC */
219	setup_c0_status_sec
220	smp_slave_setup
221#ifdef CONFIG_MIPS_MT_SMTC
222	andi	t2, t2, VPECONTROL_TE
223	beqz	t2, 2f
224	EMT		# emt
2252:
226#endif /* CONFIG_MIPS_MT_SMTC */
227	j	start_secondary
228	END(smp_bootstrap)
229#endif /* CONFIG_SMP */
230
231	__FINIT
232
233	.comm	kernelsp,    NR_CPUS * 8, 8
234	.comm	pgd_current, NR_CPUS * 8, 8
235
236	.comm	fw_arg0, SZREG, SZREG		# firmware arguments
237	.comm	fw_arg1, SZREG, SZREG
238	.comm	fw_arg2, SZREG, SZREG
239	.comm	fw_arg3, SZREG, SZREG
240
241	.macro page name, order
242	.comm	\name, (_PAGE_SIZE << \order), (_PAGE_SIZE << \order)
243	.endm
244
245	/*
246	 * On 64-bit we've got three-level pagetables with a slightly
247	 * different layout ...
248	 */
249	page	swapper_pg_dir, _PGD_ORDER
250#ifdef CONFIG_64BIT
251	page	invalid_pmd_table, _PMD_ORDER
252#endif
253	page	invalid_pte_table, _PTE_ORDER
254