1 /* 2 * Processor capabilities determination functions. 3 * 4 * Copyright (C) xxxx the Anonymous 5 * Copyright (C) 1994 - 2006 Ralf Baechle 6 * Copyright (C) 2003, 2004 Maciej W. Rozycki 7 * Copyright (C) 2001, 2004, 2011, 2012 MIPS Technologies, Inc. 8 * 9 * This program is free software; you can redistribute it and/or 10 * modify it under the terms of the GNU General Public License 11 * as published by the Free Software Foundation; either version 12 * 2 of the License, or (at your option) any later version. 13 */ 14 #include <linux/init.h> 15 #include <linux/kernel.h> 16 #include <linux/ptrace.h> 17 #include <linux/smp.h> 18 #include <linux/stddef.h> 19 #include <linux/export.h> 20 21 #include <asm/bugs.h> 22 #include <asm/cpu.h> 23 #include <asm/cpu-features.h> 24 #include <asm/cpu-type.h> 25 #include <asm/fpu.h> 26 #include <asm/mipsregs.h> 27 #include <asm/mipsmtregs.h> 28 #include <asm/msa.h> 29 #include <asm/watch.h> 30 #include <asm/elf.h> 31 #include <asm/pgtable-bits.h> 32 #include <asm/spram.h> 33 #include <linux/uaccess.h> 34 35 /* Hardware capabilities */ 36 unsigned int elf_hwcap __read_mostly; 37 EXPORT_SYMBOL_GPL(elf_hwcap); 38 39 /* 40 * Get the FPU Implementation/Revision. 41 */ 42 static inline unsigned long cpu_get_fpu_id(void) 43 { 44 unsigned long tmp, fpu_id; 45 46 tmp = read_c0_status(); 47 __enable_fpu(FPU_AS_IS); 48 fpu_id = read_32bit_cp1_register(CP1_REVISION); 49 write_c0_status(tmp); 50 return fpu_id; 51 } 52 53 /* 54 * Check if the CPU has an external FPU. 55 */ 56 static inline int __cpu_has_fpu(void) 57 { 58 return (cpu_get_fpu_id() & FPIR_IMP_MASK) != FPIR_IMP_NONE; 59 } 60 61 static inline unsigned long cpu_get_msa_id(void) 62 { 63 unsigned long status, msa_id; 64 65 status = read_c0_status(); 66 __enable_fpu(FPU_64BIT); 67 enable_msa(); 68 msa_id = read_msa_ir(); 69 disable_msa(); 70 write_c0_status(status); 71 return msa_id; 72 } 73 74 /* 75 * Determine the FCSR mask for FPU hardware. 76 */ 77 static inline void cpu_set_fpu_fcsr_mask(struct cpuinfo_mips *c) 78 { 79 unsigned long sr, mask, fcsr, fcsr0, fcsr1; 80 81 fcsr = c->fpu_csr31; 82 mask = FPU_CSR_ALL_X | FPU_CSR_ALL_E | FPU_CSR_ALL_S | FPU_CSR_RM; 83 84 sr = read_c0_status(); 85 __enable_fpu(FPU_AS_IS); 86 87 fcsr0 = fcsr & mask; 88 write_32bit_cp1_register(CP1_STATUS, fcsr0); 89 fcsr0 = read_32bit_cp1_register(CP1_STATUS); 90 91 fcsr1 = fcsr | ~mask; 92 write_32bit_cp1_register(CP1_STATUS, fcsr1); 93 fcsr1 = read_32bit_cp1_register(CP1_STATUS); 94 95 write_32bit_cp1_register(CP1_STATUS, fcsr); 96 97 write_c0_status(sr); 98 99 c->fpu_msk31 = ~(fcsr0 ^ fcsr1) & ~mask; 100 } 101 102 /* 103 * Determine the IEEE 754 NaN encodings and ABS.fmt/NEG.fmt execution modes 104 * supported by FPU hardware. 105 */ 106 static void cpu_set_fpu_2008(struct cpuinfo_mips *c) 107 { 108 if (c->isa_level & (MIPS_CPU_ISA_M32R1 | MIPS_CPU_ISA_M64R1 | 109 MIPS_CPU_ISA_M32R2 | MIPS_CPU_ISA_M64R2 | 110 MIPS_CPU_ISA_M32R6 | MIPS_CPU_ISA_M64R6)) { 111 unsigned long sr, fir, fcsr, fcsr0, fcsr1; 112 113 sr = read_c0_status(); 114 __enable_fpu(FPU_AS_IS); 115 116 fir = read_32bit_cp1_register(CP1_REVISION); 117 if (fir & MIPS_FPIR_HAS2008) { 118 fcsr = read_32bit_cp1_register(CP1_STATUS); 119 120 fcsr0 = fcsr & ~(FPU_CSR_ABS2008 | FPU_CSR_NAN2008); 121 write_32bit_cp1_register(CP1_STATUS, fcsr0); 122 fcsr0 = read_32bit_cp1_register(CP1_STATUS); 123 124 fcsr1 = fcsr | FPU_CSR_ABS2008 | FPU_CSR_NAN2008; 125 write_32bit_cp1_register(CP1_STATUS, fcsr1); 126 fcsr1 = read_32bit_cp1_register(CP1_STATUS); 127 128 write_32bit_cp1_register(CP1_STATUS, fcsr); 129 130 if (!(fcsr0 & FPU_CSR_NAN2008)) 131 c->options |= MIPS_CPU_NAN_LEGACY; 132 if (fcsr1 & FPU_CSR_NAN2008) 133 c->options |= MIPS_CPU_NAN_2008; 134 135 if ((fcsr0 ^ fcsr1) & FPU_CSR_ABS2008) 136 c->fpu_msk31 &= ~FPU_CSR_ABS2008; 137 else 138 c->fpu_csr31 |= fcsr & FPU_CSR_ABS2008; 139 140 if ((fcsr0 ^ fcsr1) & FPU_CSR_NAN2008) 141 c->fpu_msk31 &= ~FPU_CSR_NAN2008; 142 else 143 c->fpu_csr31 |= fcsr & FPU_CSR_NAN2008; 144 } else { 145 c->options |= MIPS_CPU_NAN_LEGACY; 146 } 147 148 write_c0_status(sr); 149 } else { 150 c->options |= MIPS_CPU_NAN_LEGACY; 151 } 152 } 153 154 /* 155 * IEEE 754 conformance mode to use. Affects the NaN encoding and the 156 * ABS.fmt/NEG.fmt execution mode. 157 */ 158 static enum { STRICT, LEGACY, STD2008, RELAXED } ieee754 = STRICT; 159 160 /* 161 * Set the IEEE 754 NaN encodings and the ABS.fmt/NEG.fmt execution modes 162 * to support by the FPU emulator according to the IEEE 754 conformance 163 * mode selected. Note that "relaxed" straps the emulator so that it 164 * allows 2008-NaN binaries even for legacy processors. 165 */ 166 static void cpu_set_nofpu_2008(struct cpuinfo_mips *c) 167 { 168 c->options &= ~(MIPS_CPU_NAN_2008 | MIPS_CPU_NAN_LEGACY); 169 c->fpu_csr31 &= ~(FPU_CSR_ABS2008 | FPU_CSR_NAN2008); 170 c->fpu_msk31 &= ~(FPU_CSR_ABS2008 | FPU_CSR_NAN2008); 171 172 switch (ieee754) { 173 case STRICT: 174 if (c->isa_level & (MIPS_CPU_ISA_M32R1 | MIPS_CPU_ISA_M64R1 | 175 MIPS_CPU_ISA_M32R2 | MIPS_CPU_ISA_M64R2 | 176 MIPS_CPU_ISA_M32R6 | MIPS_CPU_ISA_M64R6)) { 177 c->options |= MIPS_CPU_NAN_2008 | MIPS_CPU_NAN_LEGACY; 178 } else { 179 c->options |= MIPS_CPU_NAN_LEGACY; 180 c->fpu_msk31 |= FPU_CSR_ABS2008 | FPU_CSR_NAN2008; 181 } 182 break; 183 case LEGACY: 184 c->options |= MIPS_CPU_NAN_LEGACY; 185 c->fpu_msk31 |= FPU_CSR_ABS2008 | FPU_CSR_NAN2008; 186 break; 187 case STD2008: 188 c->options |= MIPS_CPU_NAN_2008; 189 c->fpu_csr31 |= FPU_CSR_ABS2008 | FPU_CSR_NAN2008; 190 c->fpu_msk31 |= FPU_CSR_ABS2008 | FPU_CSR_NAN2008; 191 break; 192 case RELAXED: 193 c->options |= MIPS_CPU_NAN_2008 | MIPS_CPU_NAN_LEGACY; 194 break; 195 } 196 } 197 198 /* 199 * Override the IEEE 754 NaN encoding and ABS.fmt/NEG.fmt execution mode 200 * according to the "ieee754=" parameter. 201 */ 202 static void cpu_set_nan_2008(struct cpuinfo_mips *c) 203 { 204 switch (ieee754) { 205 case STRICT: 206 mips_use_nan_legacy = !!cpu_has_nan_legacy; 207 mips_use_nan_2008 = !!cpu_has_nan_2008; 208 break; 209 case LEGACY: 210 mips_use_nan_legacy = !!cpu_has_nan_legacy; 211 mips_use_nan_2008 = !cpu_has_nan_legacy; 212 break; 213 case STD2008: 214 mips_use_nan_legacy = !cpu_has_nan_2008; 215 mips_use_nan_2008 = !!cpu_has_nan_2008; 216 break; 217 case RELAXED: 218 mips_use_nan_legacy = true; 219 mips_use_nan_2008 = true; 220 break; 221 } 222 } 223 224 /* 225 * IEEE 754 NaN encoding and ABS.fmt/NEG.fmt execution mode override 226 * settings: 227 * 228 * strict: accept binaries that request a NaN encoding supported by the FPU 229 * legacy: only accept legacy-NaN binaries 230 * 2008: only accept 2008-NaN binaries 231 * relaxed: accept any binaries regardless of whether supported by the FPU 232 */ 233 static int __init ieee754_setup(char *s) 234 { 235 if (!s) 236 return -1; 237 else if (!strcmp(s, "strict")) 238 ieee754 = STRICT; 239 else if (!strcmp(s, "legacy")) 240 ieee754 = LEGACY; 241 else if (!strcmp(s, "2008")) 242 ieee754 = STD2008; 243 else if (!strcmp(s, "relaxed")) 244 ieee754 = RELAXED; 245 else 246 return -1; 247 248 if (!(boot_cpu_data.options & MIPS_CPU_FPU)) 249 cpu_set_nofpu_2008(&boot_cpu_data); 250 cpu_set_nan_2008(&boot_cpu_data); 251 252 return 0; 253 } 254 255 early_param("ieee754", ieee754_setup); 256 257 /* 258 * Set the FIR feature flags for the FPU emulator. 259 */ 260 static void cpu_set_nofpu_id(struct cpuinfo_mips *c) 261 { 262 u32 value; 263 264 value = 0; 265 if (c->isa_level & (MIPS_CPU_ISA_M32R1 | MIPS_CPU_ISA_M64R1 | 266 MIPS_CPU_ISA_M32R2 | MIPS_CPU_ISA_M64R2 | 267 MIPS_CPU_ISA_M32R6 | MIPS_CPU_ISA_M64R6)) 268 value |= MIPS_FPIR_D | MIPS_FPIR_S; 269 if (c->isa_level & (MIPS_CPU_ISA_M32R2 | MIPS_CPU_ISA_M64R2 | 270 MIPS_CPU_ISA_M32R6 | MIPS_CPU_ISA_M64R6)) 271 value |= MIPS_FPIR_F64 | MIPS_FPIR_L | MIPS_FPIR_W; 272 if (c->options & MIPS_CPU_NAN_2008) 273 value |= MIPS_FPIR_HAS2008; 274 c->fpu_id = value; 275 } 276 277 /* Determined FPU emulator mask to use for the boot CPU with "nofpu". */ 278 static unsigned int mips_nofpu_msk31; 279 280 /* 281 * Set options for FPU hardware. 282 */ 283 static void cpu_set_fpu_opts(struct cpuinfo_mips *c) 284 { 285 c->fpu_id = cpu_get_fpu_id(); 286 mips_nofpu_msk31 = c->fpu_msk31; 287 288 if (c->isa_level & (MIPS_CPU_ISA_M32R1 | MIPS_CPU_ISA_M64R1 | 289 MIPS_CPU_ISA_M32R2 | MIPS_CPU_ISA_M64R2 | 290 MIPS_CPU_ISA_M32R6 | MIPS_CPU_ISA_M64R6)) { 291 if (c->fpu_id & MIPS_FPIR_3D) 292 c->ases |= MIPS_ASE_MIPS3D; 293 if (c->fpu_id & MIPS_FPIR_UFRP) 294 c->options |= MIPS_CPU_UFR; 295 if (c->fpu_id & MIPS_FPIR_FREP) 296 c->options |= MIPS_CPU_FRE; 297 } 298 299 cpu_set_fpu_fcsr_mask(c); 300 cpu_set_fpu_2008(c); 301 cpu_set_nan_2008(c); 302 } 303 304 /* 305 * Set options for the FPU emulator. 306 */ 307 static void cpu_set_nofpu_opts(struct cpuinfo_mips *c) 308 { 309 c->options &= ~MIPS_CPU_FPU; 310 c->fpu_msk31 = mips_nofpu_msk31; 311 312 cpu_set_nofpu_2008(c); 313 cpu_set_nan_2008(c); 314 cpu_set_nofpu_id(c); 315 } 316 317 static int mips_fpu_disabled; 318 319 static int __init fpu_disable(char *s) 320 { 321 cpu_set_nofpu_opts(&boot_cpu_data); 322 mips_fpu_disabled = 1; 323 324 return 1; 325 } 326 327 __setup("nofpu", fpu_disable); 328 329 int mips_dsp_disabled; 330 331 static int __init dsp_disable(char *s) 332 { 333 cpu_data[0].ases &= ~(MIPS_ASE_DSP | MIPS_ASE_DSP2P); 334 mips_dsp_disabled = 1; 335 336 return 1; 337 } 338 339 __setup("nodsp", dsp_disable); 340 341 static int mips_htw_disabled; 342 343 static int __init htw_disable(char *s) 344 { 345 mips_htw_disabled = 1; 346 cpu_data[0].options &= ~MIPS_CPU_HTW; 347 write_c0_pwctl(read_c0_pwctl() & 348 ~(1 << MIPS_PWCTL_PWEN_SHIFT)); 349 350 return 1; 351 } 352 353 __setup("nohtw", htw_disable); 354 355 static int mips_ftlb_disabled; 356 static int mips_has_ftlb_configured; 357 358 enum ftlb_flags { 359 FTLB_EN = 1 << 0, 360 FTLB_SET_PROB = 1 << 1, 361 }; 362 363 static int set_ftlb_enable(struct cpuinfo_mips *c, enum ftlb_flags flags); 364 365 static int __init ftlb_disable(char *s) 366 { 367 unsigned int config4, mmuextdef; 368 369 /* 370 * If the core hasn't done any FTLB configuration, there is nothing 371 * for us to do here. 372 */ 373 if (!mips_has_ftlb_configured) 374 return 1; 375 376 /* Disable it in the boot cpu */ 377 if (set_ftlb_enable(&cpu_data[0], 0)) { 378 pr_warn("Can't turn FTLB off\n"); 379 return 1; 380 } 381 382 config4 = read_c0_config4(); 383 384 /* Check that FTLB has been disabled */ 385 mmuextdef = config4 & MIPS_CONF4_MMUEXTDEF; 386 /* MMUSIZEEXT == VTLB ON, FTLB OFF */ 387 if (mmuextdef == MIPS_CONF4_MMUEXTDEF_FTLBSIZEEXT) { 388 /* This should never happen */ 389 pr_warn("FTLB could not be disabled!\n"); 390 return 1; 391 } 392 393 mips_ftlb_disabled = 1; 394 mips_has_ftlb_configured = 0; 395 396 /* 397 * noftlb is mainly used for debug purposes so print 398 * an informative message instead of using pr_debug() 399 */ 400 pr_info("FTLB has been disabled\n"); 401 402 /* 403 * Some of these bits are duplicated in the decode_config4. 404 * MIPS_CONF4_MMUEXTDEF_MMUSIZEEXT is the only possible case 405 * once FTLB has been disabled so undo what decode_config4 did. 406 */ 407 cpu_data[0].tlbsize -= cpu_data[0].tlbsizeftlbways * 408 cpu_data[0].tlbsizeftlbsets; 409 cpu_data[0].tlbsizeftlbsets = 0; 410 cpu_data[0].tlbsizeftlbways = 0; 411 412 return 1; 413 } 414 415 __setup("noftlb", ftlb_disable); 416 417 418 static inline void check_errata(void) 419 { 420 struct cpuinfo_mips *c = ¤t_cpu_data; 421 422 switch (current_cpu_type()) { 423 case CPU_34K: 424 /* 425 * Erratum "RPS May Cause Incorrect Instruction Execution" 426 * This code only handles VPE0, any SMP/RTOS code 427 * making use of VPE1 will be responsable for that VPE. 428 */ 429 if ((c->processor_id & PRID_REV_MASK) <= PRID_REV_34K_V1_0_2) 430 write_c0_config7(read_c0_config7() | MIPS_CONF7_RPS); 431 break; 432 default: 433 break; 434 } 435 } 436 437 void __init check_bugs32(void) 438 { 439 check_errata(); 440 } 441 442 /* 443 * Probe whether cpu has config register by trying to play with 444 * alternate cache bit and see whether it matters. 445 * It's used by cpu_probe to distinguish between R3000A and R3081. 446 */ 447 static inline int cpu_has_confreg(void) 448 { 449 #ifdef CONFIG_CPU_R3000 450 extern unsigned long r3k_cache_size(unsigned long); 451 unsigned long size1, size2; 452 unsigned long cfg = read_c0_conf(); 453 454 size1 = r3k_cache_size(ST0_ISC); 455 write_c0_conf(cfg ^ R30XX_CONF_AC); 456 size2 = r3k_cache_size(ST0_ISC); 457 write_c0_conf(cfg); 458 return size1 != size2; 459 #else 460 return 0; 461 #endif 462 } 463 464 static inline void set_elf_platform(int cpu, const char *plat) 465 { 466 if (cpu == 0) 467 __elf_platform = plat; 468 } 469 470 static inline void cpu_probe_vmbits(struct cpuinfo_mips *c) 471 { 472 #ifdef __NEED_VMBITS_PROBE 473 write_c0_entryhi(0x3fffffffffffe000ULL); 474 back_to_back_c0_hazard(); 475 c->vmbits = fls64(read_c0_entryhi() & 0x3fffffffffffe000ULL); 476 #endif 477 } 478 479 static void set_isa(struct cpuinfo_mips *c, unsigned int isa) 480 { 481 switch (isa) { 482 case MIPS_CPU_ISA_M64R2: 483 c->isa_level |= MIPS_CPU_ISA_M32R2 | MIPS_CPU_ISA_M64R2; 484 case MIPS_CPU_ISA_M64R1: 485 c->isa_level |= MIPS_CPU_ISA_M32R1 | MIPS_CPU_ISA_M64R1; 486 case MIPS_CPU_ISA_V: 487 c->isa_level |= MIPS_CPU_ISA_V; 488 case MIPS_CPU_ISA_IV: 489 c->isa_level |= MIPS_CPU_ISA_IV; 490 case MIPS_CPU_ISA_III: 491 c->isa_level |= MIPS_CPU_ISA_II | MIPS_CPU_ISA_III; 492 break; 493 494 /* R6 incompatible with everything else */ 495 case MIPS_CPU_ISA_M64R6: 496 c->isa_level |= MIPS_CPU_ISA_M32R6 | MIPS_CPU_ISA_M64R6; 497 case MIPS_CPU_ISA_M32R6: 498 c->isa_level |= MIPS_CPU_ISA_M32R6; 499 /* Break here so we don't add incompatible ISAs */ 500 break; 501 case MIPS_CPU_ISA_M32R2: 502 c->isa_level |= MIPS_CPU_ISA_M32R2; 503 case MIPS_CPU_ISA_M32R1: 504 c->isa_level |= MIPS_CPU_ISA_M32R1; 505 case MIPS_CPU_ISA_II: 506 c->isa_level |= MIPS_CPU_ISA_II; 507 break; 508 } 509 } 510 511 static char unknown_isa[] = KERN_ERR \ 512 "Unsupported ISA type, c0.config0: %d."; 513 514 static unsigned int calculate_ftlb_probability(struct cpuinfo_mips *c) 515 { 516 517 unsigned int probability = c->tlbsize / c->tlbsizevtlb; 518 519 /* 520 * 0 = All TLBWR instructions go to FTLB 521 * 1 = 15:1: For every 16 TBLWR instructions, 15 go to the 522 * FTLB and 1 goes to the VTLB. 523 * 2 = 7:1: As above with 7:1 ratio. 524 * 3 = 3:1: As above with 3:1 ratio. 525 * 526 * Use the linear midpoint as the probability threshold. 527 */ 528 if (probability >= 12) 529 return 1; 530 else if (probability >= 6) 531 return 2; 532 else 533 /* 534 * So FTLB is less than 4 times bigger than VTLB. 535 * A 3:1 ratio can still be useful though. 536 */ 537 return 3; 538 } 539 540 static int set_ftlb_enable(struct cpuinfo_mips *c, enum ftlb_flags flags) 541 { 542 unsigned int config; 543 544 /* It's implementation dependent how the FTLB can be enabled */ 545 switch (c->cputype) { 546 case CPU_PROAPTIV: 547 case CPU_P5600: 548 case CPU_P6600: 549 /* proAptiv & related cores use Config6 to enable the FTLB */ 550 config = read_c0_config6(); 551 552 if (flags & FTLB_EN) 553 config |= MIPS_CONF6_FTLBEN; 554 else 555 config &= ~MIPS_CONF6_FTLBEN; 556 557 if (flags & FTLB_SET_PROB) { 558 config &= ~(3 << MIPS_CONF6_FTLBP_SHIFT); 559 config |= calculate_ftlb_probability(c) 560 << MIPS_CONF6_FTLBP_SHIFT; 561 } 562 563 write_c0_config6(config); 564 back_to_back_c0_hazard(); 565 break; 566 case CPU_I6400: 567 /* There's no way to disable the FTLB */ 568 if (!(flags & FTLB_EN)) 569 return 1; 570 return 0; 571 case CPU_LOONGSON3: 572 /* Flush ITLB, DTLB, VTLB and FTLB */ 573 write_c0_diag(LOONGSON_DIAG_ITLB | LOONGSON_DIAG_DTLB | 574 LOONGSON_DIAG_VTLB | LOONGSON_DIAG_FTLB); 575 /* Loongson-3 cores use Config6 to enable the FTLB */ 576 config = read_c0_config6(); 577 if (flags & FTLB_EN) 578 /* Enable FTLB */ 579 write_c0_config6(config & ~MIPS_CONF6_FTLBDIS); 580 else 581 /* Disable FTLB */ 582 write_c0_config6(config | MIPS_CONF6_FTLBDIS); 583 break; 584 default: 585 return 1; 586 } 587 588 return 0; 589 } 590 591 static inline unsigned int decode_config0(struct cpuinfo_mips *c) 592 { 593 unsigned int config0; 594 int isa, mt; 595 596 config0 = read_c0_config(); 597 598 /* 599 * Look for Standard TLB or Dual VTLB and FTLB 600 */ 601 mt = config0 & MIPS_CONF_MT; 602 if (mt == MIPS_CONF_MT_TLB) 603 c->options |= MIPS_CPU_TLB; 604 else if (mt == MIPS_CONF_MT_FTLB) 605 c->options |= MIPS_CPU_TLB | MIPS_CPU_FTLB; 606 607 isa = (config0 & MIPS_CONF_AT) >> 13; 608 switch (isa) { 609 case 0: 610 switch ((config0 & MIPS_CONF_AR) >> 10) { 611 case 0: 612 set_isa(c, MIPS_CPU_ISA_M32R1); 613 break; 614 case 1: 615 set_isa(c, MIPS_CPU_ISA_M32R2); 616 break; 617 case 2: 618 set_isa(c, MIPS_CPU_ISA_M32R6); 619 break; 620 default: 621 goto unknown; 622 } 623 break; 624 case 2: 625 switch ((config0 & MIPS_CONF_AR) >> 10) { 626 case 0: 627 set_isa(c, MIPS_CPU_ISA_M64R1); 628 break; 629 case 1: 630 set_isa(c, MIPS_CPU_ISA_M64R2); 631 break; 632 case 2: 633 set_isa(c, MIPS_CPU_ISA_M64R6); 634 break; 635 default: 636 goto unknown; 637 } 638 break; 639 default: 640 goto unknown; 641 } 642 643 return config0 & MIPS_CONF_M; 644 645 unknown: 646 panic(unknown_isa, config0); 647 } 648 649 static inline unsigned int decode_config1(struct cpuinfo_mips *c) 650 { 651 unsigned int config1; 652 653 config1 = read_c0_config1(); 654 655 if (config1 & MIPS_CONF1_MD) 656 c->ases |= MIPS_ASE_MDMX; 657 if (config1 & MIPS_CONF1_PC) 658 c->options |= MIPS_CPU_PERF; 659 if (config1 & MIPS_CONF1_WR) 660 c->options |= MIPS_CPU_WATCH; 661 if (config1 & MIPS_CONF1_CA) 662 c->ases |= MIPS_ASE_MIPS16; 663 if (config1 & MIPS_CONF1_EP) 664 c->options |= MIPS_CPU_EJTAG; 665 if (config1 & MIPS_CONF1_FP) { 666 c->options |= MIPS_CPU_FPU; 667 c->options |= MIPS_CPU_32FPR; 668 } 669 if (cpu_has_tlb) { 670 c->tlbsize = ((config1 & MIPS_CONF1_TLBS) >> 25) + 1; 671 c->tlbsizevtlb = c->tlbsize; 672 c->tlbsizeftlbsets = 0; 673 } 674 675 return config1 & MIPS_CONF_M; 676 } 677 678 static inline unsigned int decode_config2(struct cpuinfo_mips *c) 679 { 680 unsigned int config2; 681 682 config2 = read_c0_config2(); 683 684 if (config2 & MIPS_CONF2_SL) 685 c->scache.flags &= ~MIPS_CACHE_NOT_PRESENT; 686 687 return config2 & MIPS_CONF_M; 688 } 689 690 static inline unsigned int decode_config3(struct cpuinfo_mips *c) 691 { 692 unsigned int config3; 693 694 config3 = read_c0_config3(); 695 696 if (config3 & MIPS_CONF3_SM) { 697 c->ases |= MIPS_ASE_SMARTMIPS; 698 c->options |= MIPS_CPU_RIXI | MIPS_CPU_CTXTC; 699 } 700 if (config3 & MIPS_CONF3_RXI) 701 c->options |= MIPS_CPU_RIXI; 702 if (config3 & MIPS_CONF3_CTXTC) 703 c->options |= MIPS_CPU_CTXTC; 704 if (config3 & MIPS_CONF3_DSP) 705 c->ases |= MIPS_ASE_DSP; 706 if (config3 & MIPS_CONF3_DSP2P) { 707 c->ases |= MIPS_ASE_DSP2P; 708 if (cpu_has_mips_r6) 709 c->ases |= MIPS_ASE_DSP3; 710 } 711 if (config3 & MIPS_CONF3_VINT) 712 c->options |= MIPS_CPU_VINT; 713 if (config3 & MIPS_CONF3_VEIC) 714 c->options |= MIPS_CPU_VEIC; 715 if (config3 & MIPS_CONF3_LPA) 716 c->options |= MIPS_CPU_LPA; 717 if (config3 & MIPS_CONF3_MT) 718 c->ases |= MIPS_ASE_MIPSMT; 719 if (config3 & MIPS_CONF3_ULRI) 720 c->options |= MIPS_CPU_ULRI; 721 if (config3 & MIPS_CONF3_ISA) 722 c->options |= MIPS_CPU_MICROMIPS; 723 if (config3 & MIPS_CONF3_VZ) 724 c->ases |= MIPS_ASE_VZ; 725 if (config3 & MIPS_CONF3_SC) 726 c->options |= MIPS_CPU_SEGMENTS; 727 if (config3 & MIPS_CONF3_BI) 728 c->options |= MIPS_CPU_BADINSTR; 729 if (config3 & MIPS_CONF3_BP) 730 c->options |= MIPS_CPU_BADINSTRP; 731 if (config3 & MIPS_CONF3_MSA) 732 c->ases |= MIPS_ASE_MSA; 733 if (config3 & MIPS_CONF3_PW) { 734 c->htw_seq = 0; 735 c->options |= MIPS_CPU_HTW; 736 } 737 if (config3 & MIPS_CONF3_CDMM) 738 c->options |= MIPS_CPU_CDMM; 739 if (config3 & MIPS_CONF3_SP) 740 c->options |= MIPS_CPU_SP; 741 742 return config3 & MIPS_CONF_M; 743 } 744 745 static inline unsigned int decode_config4(struct cpuinfo_mips *c) 746 { 747 unsigned int config4; 748 unsigned int newcf4; 749 unsigned int mmuextdef; 750 unsigned int ftlb_page = MIPS_CONF4_FTLBPAGESIZE; 751 unsigned long asid_mask; 752 753 config4 = read_c0_config4(); 754 755 if (cpu_has_tlb) { 756 if (((config4 & MIPS_CONF4_IE) >> 29) == 2) 757 c->options |= MIPS_CPU_TLBINV; 758 759 /* 760 * R6 has dropped the MMUExtDef field from config4. 761 * On R6 the fields always describe the FTLB, and only if it is 762 * present according to Config.MT. 763 */ 764 if (!cpu_has_mips_r6) 765 mmuextdef = config4 & MIPS_CONF4_MMUEXTDEF; 766 else if (cpu_has_ftlb) 767 mmuextdef = MIPS_CONF4_MMUEXTDEF_VTLBSIZEEXT; 768 else 769 mmuextdef = 0; 770 771 switch (mmuextdef) { 772 case MIPS_CONF4_MMUEXTDEF_MMUSIZEEXT: 773 c->tlbsize += (config4 & MIPS_CONF4_MMUSIZEEXT) * 0x40; 774 c->tlbsizevtlb = c->tlbsize; 775 break; 776 case MIPS_CONF4_MMUEXTDEF_VTLBSIZEEXT: 777 c->tlbsizevtlb += 778 ((config4 & MIPS_CONF4_VTLBSIZEEXT) >> 779 MIPS_CONF4_VTLBSIZEEXT_SHIFT) * 0x40; 780 c->tlbsize = c->tlbsizevtlb; 781 ftlb_page = MIPS_CONF4_VFTLBPAGESIZE; 782 /* fall through */ 783 case MIPS_CONF4_MMUEXTDEF_FTLBSIZEEXT: 784 if (mips_ftlb_disabled) 785 break; 786 newcf4 = (config4 & ~ftlb_page) | 787 (page_size_ftlb(mmuextdef) << 788 MIPS_CONF4_FTLBPAGESIZE_SHIFT); 789 write_c0_config4(newcf4); 790 back_to_back_c0_hazard(); 791 config4 = read_c0_config4(); 792 if (config4 != newcf4) { 793 pr_err("PAGE_SIZE 0x%lx is not supported by FTLB (config4=0x%x)\n", 794 PAGE_SIZE, config4); 795 /* Switch FTLB off */ 796 set_ftlb_enable(c, 0); 797 mips_ftlb_disabled = 1; 798 break; 799 } 800 c->tlbsizeftlbsets = 1 << 801 ((config4 & MIPS_CONF4_FTLBSETS) >> 802 MIPS_CONF4_FTLBSETS_SHIFT); 803 c->tlbsizeftlbways = ((config4 & MIPS_CONF4_FTLBWAYS) >> 804 MIPS_CONF4_FTLBWAYS_SHIFT) + 2; 805 c->tlbsize += c->tlbsizeftlbways * c->tlbsizeftlbsets; 806 mips_has_ftlb_configured = 1; 807 break; 808 } 809 } 810 811 c->kscratch_mask = (config4 & MIPS_CONF4_KSCREXIST) 812 >> MIPS_CONF4_KSCREXIST_SHIFT; 813 814 asid_mask = MIPS_ENTRYHI_ASID; 815 if (config4 & MIPS_CONF4_AE) 816 asid_mask |= MIPS_ENTRYHI_ASIDX; 817 set_cpu_asid_mask(c, asid_mask); 818 819 /* 820 * Warn if the computed ASID mask doesn't match the mask the kernel 821 * is built for. This may indicate either a serious problem or an 822 * easy optimisation opportunity, but either way should be addressed. 823 */ 824 WARN_ON(asid_mask != cpu_asid_mask(c)); 825 826 return config4 & MIPS_CONF_M; 827 } 828 829 static inline unsigned int decode_config5(struct cpuinfo_mips *c) 830 { 831 unsigned int config5; 832 833 config5 = read_c0_config5(); 834 config5 &= ~(MIPS_CONF5_UFR | MIPS_CONF5_UFE); 835 write_c0_config5(config5); 836 837 if (config5 & MIPS_CONF5_EVA) 838 c->options |= MIPS_CPU_EVA; 839 if (config5 & MIPS_CONF5_MRP) 840 c->options |= MIPS_CPU_MAAR; 841 if (config5 & MIPS_CONF5_LLB) 842 c->options |= MIPS_CPU_RW_LLB; 843 if (config5 & MIPS_CONF5_MVH) 844 c->options |= MIPS_CPU_MVH; 845 if (cpu_has_mips_r6 && (config5 & MIPS_CONF5_VP)) 846 c->options |= MIPS_CPU_VP; 847 848 return config5 & MIPS_CONF_M; 849 } 850 851 static void decode_configs(struct cpuinfo_mips *c) 852 { 853 int ok; 854 855 /* MIPS32 or MIPS64 compliant CPU. */ 856 c->options = MIPS_CPU_4KEX | MIPS_CPU_4K_CACHE | MIPS_CPU_COUNTER | 857 MIPS_CPU_DIVEC | MIPS_CPU_LLSC | MIPS_CPU_MCHECK; 858 859 c->scache.flags = MIPS_CACHE_NOT_PRESENT; 860 861 /* Enable FTLB if present and not disabled */ 862 set_ftlb_enable(c, mips_ftlb_disabled ? 0 : FTLB_EN); 863 864 ok = decode_config0(c); /* Read Config registers. */ 865 BUG_ON(!ok); /* Arch spec violation! */ 866 if (ok) 867 ok = decode_config1(c); 868 if (ok) 869 ok = decode_config2(c); 870 if (ok) 871 ok = decode_config3(c); 872 if (ok) 873 ok = decode_config4(c); 874 if (ok) 875 ok = decode_config5(c); 876 877 /* Probe the EBase.WG bit */ 878 if (cpu_has_mips_r2_r6) { 879 u64 ebase; 880 unsigned int status; 881 882 /* {read,write}_c0_ebase_64() may be UNDEFINED prior to r6 */ 883 ebase = cpu_has_mips64r6 ? read_c0_ebase_64() 884 : (s32)read_c0_ebase(); 885 if (ebase & MIPS_EBASE_WG) { 886 /* WG bit already set, we can avoid the clumsy probe */ 887 c->options |= MIPS_CPU_EBASE_WG; 888 } else { 889 /* Its UNDEFINED to change EBase while BEV=0 */ 890 status = read_c0_status(); 891 write_c0_status(status | ST0_BEV); 892 irq_enable_hazard(); 893 /* 894 * On pre-r6 cores, this may well clobber the upper bits 895 * of EBase. This is hard to avoid without potentially 896 * hitting UNDEFINED dm*c0 behaviour if EBase is 32-bit. 897 */ 898 if (cpu_has_mips64r6) 899 write_c0_ebase_64(ebase | MIPS_EBASE_WG); 900 else 901 write_c0_ebase(ebase | MIPS_EBASE_WG); 902 back_to_back_c0_hazard(); 903 /* Restore BEV */ 904 write_c0_status(status); 905 if (read_c0_ebase() & MIPS_EBASE_WG) { 906 c->options |= MIPS_CPU_EBASE_WG; 907 write_c0_ebase(ebase); 908 } 909 } 910 } 911 912 /* configure the FTLB write probability */ 913 set_ftlb_enable(c, (mips_ftlb_disabled ? 0 : FTLB_EN) | FTLB_SET_PROB); 914 915 mips_probe_watch_registers(c); 916 917 #ifndef CONFIG_MIPS_CPS 918 if (cpu_has_mips_r2_r6) { 919 c->core = get_ebase_cpunum(); 920 if (cpu_has_mipsmt) 921 c->core >>= fls(core_nvpes()) - 1; 922 } 923 #endif 924 } 925 926 /* 927 * Probe for certain guest capabilities by writing config bits and reading back. 928 * Finally write back the original value. 929 */ 930 #define probe_gc0_config(name, maxconf, bits) \ 931 do { \ 932 unsigned int tmp; \ 933 tmp = read_gc0_##name(); \ 934 write_gc0_##name(tmp | (bits)); \ 935 back_to_back_c0_hazard(); \ 936 maxconf = read_gc0_##name(); \ 937 write_gc0_##name(tmp); \ 938 } while (0) 939 940 /* 941 * Probe for dynamic guest capabilities by changing certain config bits and 942 * reading back to see if they change. Finally write back the original value. 943 */ 944 #define probe_gc0_config_dyn(name, maxconf, dynconf, bits) \ 945 do { \ 946 maxconf = read_gc0_##name(); \ 947 write_gc0_##name(maxconf ^ (bits)); \ 948 back_to_back_c0_hazard(); \ 949 dynconf = maxconf ^ read_gc0_##name(); \ 950 write_gc0_##name(maxconf); \ 951 maxconf |= dynconf; \ 952 } while (0) 953 954 static inline unsigned int decode_guest_config0(struct cpuinfo_mips *c) 955 { 956 unsigned int config0; 957 958 probe_gc0_config(config, config0, MIPS_CONF_M); 959 960 if (config0 & MIPS_CONF_M) 961 c->guest.conf |= BIT(1); 962 return config0 & MIPS_CONF_M; 963 } 964 965 static inline unsigned int decode_guest_config1(struct cpuinfo_mips *c) 966 { 967 unsigned int config1, config1_dyn; 968 969 probe_gc0_config_dyn(config1, config1, config1_dyn, 970 MIPS_CONF_M | MIPS_CONF1_PC | MIPS_CONF1_WR | 971 MIPS_CONF1_FP); 972 973 if (config1 & MIPS_CONF1_FP) 974 c->guest.options |= MIPS_CPU_FPU; 975 if (config1_dyn & MIPS_CONF1_FP) 976 c->guest.options_dyn |= MIPS_CPU_FPU; 977 978 if (config1 & MIPS_CONF1_WR) 979 c->guest.options |= MIPS_CPU_WATCH; 980 if (config1_dyn & MIPS_CONF1_WR) 981 c->guest.options_dyn |= MIPS_CPU_WATCH; 982 983 if (config1 & MIPS_CONF1_PC) 984 c->guest.options |= MIPS_CPU_PERF; 985 if (config1_dyn & MIPS_CONF1_PC) 986 c->guest.options_dyn |= MIPS_CPU_PERF; 987 988 if (config1 & MIPS_CONF_M) 989 c->guest.conf |= BIT(2); 990 return config1 & MIPS_CONF_M; 991 } 992 993 static inline unsigned int decode_guest_config2(struct cpuinfo_mips *c) 994 { 995 unsigned int config2; 996 997 probe_gc0_config(config2, config2, MIPS_CONF_M); 998 999 if (config2 & MIPS_CONF_M) 1000 c->guest.conf |= BIT(3); 1001 return config2 & MIPS_CONF_M; 1002 } 1003 1004 static inline unsigned int decode_guest_config3(struct cpuinfo_mips *c) 1005 { 1006 unsigned int config3, config3_dyn; 1007 1008 probe_gc0_config_dyn(config3, config3, config3_dyn, 1009 MIPS_CONF_M | MIPS_CONF3_MSA | MIPS_CONF3_ULRI | 1010 MIPS_CONF3_CTXTC); 1011 1012 if (config3 & MIPS_CONF3_CTXTC) 1013 c->guest.options |= MIPS_CPU_CTXTC; 1014 if (config3_dyn & MIPS_CONF3_CTXTC) 1015 c->guest.options_dyn |= MIPS_CPU_CTXTC; 1016 1017 if (config3 & MIPS_CONF3_PW) 1018 c->guest.options |= MIPS_CPU_HTW; 1019 1020 if (config3 & MIPS_CONF3_ULRI) 1021 c->guest.options |= MIPS_CPU_ULRI; 1022 1023 if (config3 & MIPS_CONF3_SC) 1024 c->guest.options |= MIPS_CPU_SEGMENTS; 1025 1026 if (config3 & MIPS_CONF3_BI) 1027 c->guest.options |= MIPS_CPU_BADINSTR; 1028 if (config3 & MIPS_CONF3_BP) 1029 c->guest.options |= MIPS_CPU_BADINSTRP; 1030 1031 if (config3 & MIPS_CONF3_MSA) 1032 c->guest.ases |= MIPS_ASE_MSA; 1033 if (config3_dyn & MIPS_CONF3_MSA) 1034 c->guest.ases_dyn |= MIPS_ASE_MSA; 1035 1036 if (config3 & MIPS_CONF_M) 1037 c->guest.conf |= BIT(4); 1038 return config3 & MIPS_CONF_M; 1039 } 1040 1041 static inline unsigned int decode_guest_config4(struct cpuinfo_mips *c) 1042 { 1043 unsigned int config4; 1044 1045 probe_gc0_config(config4, config4, 1046 MIPS_CONF_M | MIPS_CONF4_KSCREXIST); 1047 1048 c->guest.kscratch_mask = (config4 & MIPS_CONF4_KSCREXIST) 1049 >> MIPS_CONF4_KSCREXIST_SHIFT; 1050 1051 if (config4 & MIPS_CONF_M) 1052 c->guest.conf |= BIT(5); 1053 return config4 & MIPS_CONF_M; 1054 } 1055 1056 static inline unsigned int decode_guest_config5(struct cpuinfo_mips *c) 1057 { 1058 unsigned int config5, config5_dyn; 1059 1060 probe_gc0_config_dyn(config5, config5, config5_dyn, 1061 MIPS_CONF_M | MIPS_CONF5_MVH | MIPS_CONF5_MRP); 1062 1063 if (config5 & MIPS_CONF5_MRP) 1064 c->guest.options |= MIPS_CPU_MAAR; 1065 if (config5_dyn & MIPS_CONF5_MRP) 1066 c->guest.options_dyn |= MIPS_CPU_MAAR; 1067 1068 if (config5 & MIPS_CONF5_LLB) 1069 c->guest.options |= MIPS_CPU_RW_LLB; 1070 1071 if (config5 & MIPS_CONF5_MVH) 1072 c->guest.options |= MIPS_CPU_MVH; 1073 1074 if (config5 & MIPS_CONF_M) 1075 c->guest.conf |= BIT(6); 1076 return config5 & MIPS_CONF_M; 1077 } 1078 1079 static inline void decode_guest_configs(struct cpuinfo_mips *c) 1080 { 1081 unsigned int ok; 1082 1083 ok = decode_guest_config0(c); 1084 if (ok) 1085 ok = decode_guest_config1(c); 1086 if (ok) 1087 ok = decode_guest_config2(c); 1088 if (ok) 1089 ok = decode_guest_config3(c); 1090 if (ok) 1091 ok = decode_guest_config4(c); 1092 if (ok) 1093 decode_guest_config5(c); 1094 } 1095 1096 static inline void cpu_probe_guestctl0(struct cpuinfo_mips *c) 1097 { 1098 unsigned int guestctl0, temp; 1099 1100 guestctl0 = read_c0_guestctl0(); 1101 1102 if (guestctl0 & MIPS_GCTL0_G0E) 1103 c->options |= MIPS_CPU_GUESTCTL0EXT; 1104 if (guestctl0 & MIPS_GCTL0_G1) 1105 c->options |= MIPS_CPU_GUESTCTL1; 1106 if (guestctl0 & MIPS_GCTL0_G2) 1107 c->options |= MIPS_CPU_GUESTCTL2; 1108 if (!(guestctl0 & MIPS_GCTL0_RAD)) { 1109 c->options |= MIPS_CPU_GUESTID; 1110 1111 /* 1112 * Probe for Direct Root to Guest (DRG). Set GuestCtl1.RID = 0 1113 * first, otherwise all data accesses will be fully virtualised 1114 * as if they were performed by guest mode. 1115 */ 1116 write_c0_guestctl1(0); 1117 tlbw_use_hazard(); 1118 1119 write_c0_guestctl0(guestctl0 | MIPS_GCTL0_DRG); 1120 back_to_back_c0_hazard(); 1121 temp = read_c0_guestctl0(); 1122 1123 if (temp & MIPS_GCTL0_DRG) { 1124 write_c0_guestctl0(guestctl0); 1125 c->options |= MIPS_CPU_DRG; 1126 } 1127 } 1128 } 1129 1130 static inline void cpu_probe_guestctl1(struct cpuinfo_mips *c) 1131 { 1132 if (cpu_has_guestid) { 1133 /* determine the number of bits of GuestID available */ 1134 write_c0_guestctl1(MIPS_GCTL1_ID); 1135 back_to_back_c0_hazard(); 1136 c->guestid_mask = (read_c0_guestctl1() & MIPS_GCTL1_ID) 1137 >> MIPS_GCTL1_ID_SHIFT; 1138 write_c0_guestctl1(0); 1139 } 1140 } 1141 1142 static inline void cpu_probe_gtoffset(struct cpuinfo_mips *c) 1143 { 1144 /* determine the number of bits of GTOffset available */ 1145 write_c0_gtoffset(0xffffffff); 1146 back_to_back_c0_hazard(); 1147 c->gtoffset_mask = read_c0_gtoffset(); 1148 write_c0_gtoffset(0); 1149 } 1150 1151 static inline void cpu_probe_vz(struct cpuinfo_mips *c) 1152 { 1153 cpu_probe_guestctl0(c); 1154 if (cpu_has_guestctl1) 1155 cpu_probe_guestctl1(c); 1156 1157 cpu_probe_gtoffset(c); 1158 1159 decode_guest_configs(c); 1160 } 1161 1162 #define R4K_OPTS (MIPS_CPU_TLB | MIPS_CPU_4KEX | MIPS_CPU_4K_CACHE \ 1163 | MIPS_CPU_COUNTER) 1164 1165 static inline void cpu_probe_legacy(struct cpuinfo_mips *c, unsigned int cpu) 1166 { 1167 switch (c->processor_id & PRID_IMP_MASK) { 1168 case PRID_IMP_R2000: 1169 c->cputype = CPU_R2000; 1170 __cpu_name[cpu] = "R2000"; 1171 c->fpu_msk31 |= FPU_CSR_CONDX | FPU_CSR_FS; 1172 c->options = MIPS_CPU_TLB | MIPS_CPU_3K_CACHE | 1173 MIPS_CPU_NOFPUEX; 1174 if (__cpu_has_fpu()) 1175 c->options |= MIPS_CPU_FPU; 1176 c->tlbsize = 64; 1177 break; 1178 case PRID_IMP_R3000: 1179 if ((c->processor_id & PRID_REV_MASK) == PRID_REV_R3000A) { 1180 if (cpu_has_confreg()) { 1181 c->cputype = CPU_R3081E; 1182 __cpu_name[cpu] = "R3081"; 1183 } else { 1184 c->cputype = CPU_R3000A; 1185 __cpu_name[cpu] = "R3000A"; 1186 } 1187 } else { 1188 c->cputype = CPU_R3000; 1189 __cpu_name[cpu] = "R3000"; 1190 } 1191 c->fpu_msk31 |= FPU_CSR_CONDX | FPU_CSR_FS; 1192 c->options = MIPS_CPU_TLB | MIPS_CPU_3K_CACHE | 1193 MIPS_CPU_NOFPUEX; 1194 if (__cpu_has_fpu()) 1195 c->options |= MIPS_CPU_FPU; 1196 c->tlbsize = 64; 1197 break; 1198 case PRID_IMP_R4000: 1199 if (read_c0_config() & CONF_SC) { 1200 if ((c->processor_id & PRID_REV_MASK) >= 1201 PRID_REV_R4400) { 1202 c->cputype = CPU_R4400PC; 1203 __cpu_name[cpu] = "R4400PC"; 1204 } else { 1205 c->cputype = CPU_R4000PC; 1206 __cpu_name[cpu] = "R4000PC"; 1207 } 1208 } else { 1209 int cca = read_c0_config() & CONF_CM_CMASK; 1210 int mc; 1211 1212 /* 1213 * SC and MC versions can't be reliably told apart, 1214 * but only the latter support coherent caching 1215 * modes so assume the firmware has set the KSEG0 1216 * coherency attribute reasonably (if uncached, we 1217 * assume SC). 1218 */ 1219 switch (cca) { 1220 case CONF_CM_CACHABLE_CE: 1221 case CONF_CM_CACHABLE_COW: 1222 case CONF_CM_CACHABLE_CUW: 1223 mc = 1; 1224 break; 1225 default: 1226 mc = 0; 1227 break; 1228 } 1229 if ((c->processor_id & PRID_REV_MASK) >= 1230 PRID_REV_R4400) { 1231 c->cputype = mc ? CPU_R4400MC : CPU_R4400SC; 1232 __cpu_name[cpu] = mc ? "R4400MC" : "R4400SC"; 1233 } else { 1234 c->cputype = mc ? CPU_R4000MC : CPU_R4000SC; 1235 __cpu_name[cpu] = mc ? "R4000MC" : "R4000SC"; 1236 } 1237 } 1238 1239 set_isa(c, MIPS_CPU_ISA_III); 1240 c->fpu_msk31 |= FPU_CSR_CONDX; 1241 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR | 1242 MIPS_CPU_WATCH | MIPS_CPU_VCE | 1243 MIPS_CPU_LLSC; 1244 c->tlbsize = 48; 1245 break; 1246 case PRID_IMP_VR41XX: 1247 set_isa(c, MIPS_CPU_ISA_III); 1248 c->fpu_msk31 |= FPU_CSR_CONDX; 1249 c->options = R4K_OPTS; 1250 c->tlbsize = 32; 1251 switch (c->processor_id & 0xf0) { 1252 case PRID_REV_VR4111: 1253 c->cputype = CPU_VR4111; 1254 __cpu_name[cpu] = "NEC VR4111"; 1255 break; 1256 case PRID_REV_VR4121: 1257 c->cputype = CPU_VR4121; 1258 __cpu_name[cpu] = "NEC VR4121"; 1259 break; 1260 case PRID_REV_VR4122: 1261 if ((c->processor_id & 0xf) < 0x3) { 1262 c->cputype = CPU_VR4122; 1263 __cpu_name[cpu] = "NEC VR4122"; 1264 } else { 1265 c->cputype = CPU_VR4181A; 1266 __cpu_name[cpu] = "NEC VR4181A"; 1267 } 1268 break; 1269 case PRID_REV_VR4130: 1270 if ((c->processor_id & 0xf) < 0x4) { 1271 c->cputype = CPU_VR4131; 1272 __cpu_name[cpu] = "NEC VR4131"; 1273 } else { 1274 c->cputype = CPU_VR4133; 1275 c->options |= MIPS_CPU_LLSC; 1276 __cpu_name[cpu] = "NEC VR4133"; 1277 } 1278 break; 1279 default: 1280 printk(KERN_INFO "Unexpected CPU of NEC VR4100 series\n"); 1281 c->cputype = CPU_VR41XX; 1282 __cpu_name[cpu] = "NEC Vr41xx"; 1283 break; 1284 } 1285 break; 1286 case PRID_IMP_R4300: 1287 c->cputype = CPU_R4300; 1288 __cpu_name[cpu] = "R4300"; 1289 set_isa(c, MIPS_CPU_ISA_III); 1290 c->fpu_msk31 |= FPU_CSR_CONDX; 1291 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR | 1292 MIPS_CPU_LLSC; 1293 c->tlbsize = 32; 1294 break; 1295 case PRID_IMP_R4600: 1296 c->cputype = CPU_R4600; 1297 __cpu_name[cpu] = "R4600"; 1298 set_isa(c, MIPS_CPU_ISA_III); 1299 c->fpu_msk31 |= FPU_CSR_CONDX; 1300 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR | 1301 MIPS_CPU_LLSC; 1302 c->tlbsize = 48; 1303 break; 1304 #if 0 1305 case PRID_IMP_R4650: 1306 /* 1307 * This processor doesn't have an MMU, so it's not 1308 * "real easy" to run Linux on it. It is left purely 1309 * for documentation. Commented out because it shares 1310 * it's c0_prid id number with the TX3900. 1311 */ 1312 c->cputype = CPU_R4650; 1313 __cpu_name[cpu] = "R4650"; 1314 set_isa(c, MIPS_CPU_ISA_III); 1315 c->fpu_msk31 |= FPU_CSR_CONDX; 1316 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_LLSC; 1317 c->tlbsize = 48; 1318 break; 1319 #endif 1320 case PRID_IMP_TX39: 1321 c->fpu_msk31 |= FPU_CSR_CONDX | FPU_CSR_FS; 1322 c->options = MIPS_CPU_TLB | MIPS_CPU_TX39_CACHE; 1323 1324 if ((c->processor_id & 0xf0) == (PRID_REV_TX3927 & 0xf0)) { 1325 c->cputype = CPU_TX3927; 1326 __cpu_name[cpu] = "TX3927"; 1327 c->tlbsize = 64; 1328 } else { 1329 switch (c->processor_id & PRID_REV_MASK) { 1330 case PRID_REV_TX3912: 1331 c->cputype = CPU_TX3912; 1332 __cpu_name[cpu] = "TX3912"; 1333 c->tlbsize = 32; 1334 break; 1335 case PRID_REV_TX3922: 1336 c->cputype = CPU_TX3922; 1337 __cpu_name[cpu] = "TX3922"; 1338 c->tlbsize = 64; 1339 break; 1340 } 1341 } 1342 break; 1343 case PRID_IMP_R4700: 1344 c->cputype = CPU_R4700; 1345 __cpu_name[cpu] = "R4700"; 1346 set_isa(c, MIPS_CPU_ISA_III); 1347 c->fpu_msk31 |= FPU_CSR_CONDX; 1348 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR | 1349 MIPS_CPU_LLSC; 1350 c->tlbsize = 48; 1351 break; 1352 case PRID_IMP_TX49: 1353 c->cputype = CPU_TX49XX; 1354 __cpu_name[cpu] = "R49XX"; 1355 set_isa(c, MIPS_CPU_ISA_III); 1356 c->fpu_msk31 |= FPU_CSR_CONDX; 1357 c->options = R4K_OPTS | MIPS_CPU_LLSC; 1358 if (!(c->processor_id & 0x08)) 1359 c->options |= MIPS_CPU_FPU | MIPS_CPU_32FPR; 1360 c->tlbsize = 48; 1361 break; 1362 case PRID_IMP_R5000: 1363 c->cputype = CPU_R5000; 1364 __cpu_name[cpu] = "R5000"; 1365 set_isa(c, MIPS_CPU_ISA_IV); 1366 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR | 1367 MIPS_CPU_LLSC; 1368 c->tlbsize = 48; 1369 break; 1370 case PRID_IMP_R5432: 1371 c->cputype = CPU_R5432; 1372 __cpu_name[cpu] = "R5432"; 1373 set_isa(c, MIPS_CPU_ISA_IV); 1374 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR | 1375 MIPS_CPU_WATCH | MIPS_CPU_LLSC; 1376 c->tlbsize = 48; 1377 break; 1378 case PRID_IMP_R5500: 1379 c->cputype = CPU_R5500; 1380 __cpu_name[cpu] = "R5500"; 1381 set_isa(c, MIPS_CPU_ISA_IV); 1382 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR | 1383 MIPS_CPU_WATCH | MIPS_CPU_LLSC; 1384 c->tlbsize = 48; 1385 break; 1386 case PRID_IMP_NEVADA: 1387 c->cputype = CPU_NEVADA; 1388 __cpu_name[cpu] = "Nevada"; 1389 set_isa(c, MIPS_CPU_ISA_IV); 1390 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR | 1391 MIPS_CPU_DIVEC | MIPS_CPU_LLSC; 1392 c->tlbsize = 48; 1393 break; 1394 case PRID_IMP_R6000: 1395 c->cputype = CPU_R6000; 1396 __cpu_name[cpu] = "R6000"; 1397 set_isa(c, MIPS_CPU_ISA_II); 1398 c->fpu_msk31 |= FPU_CSR_CONDX | FPU_CSR_FS; 1399 c->options = MIPS_CPU_TLB | MIPS_CPU_FPU | 1400 MIPS_CPU_LLSC; 1401 c->tlbsize = 32; 1402 break; 1403 case PRID_IMP_R6000A: 1404 c->cputype = CPU_R6000A; 1405 __cpu_name[cpu] = "R6000A"; 1406 set_isa(c, MIPS_CPU_ISA_II); 1407 c->fpu_msk31 |= FPU_CSR_CONDX | FPU_CSR_FS; 1408 c->options = MIPS_CPU_TLB | MIPS_CPU_FPU | 1409 MIPS_CPU_LLSC; 1410 c->tlbsize = 32; 1411 break; 1412 case PRID_IMP_RM7000: 1413 c->cputype = CPU_RM7000; 1414 __cpu_name[cpu] = "RM7000"; 1415 set_isa(c, MIPS_CPU_ISA_IV); 1416 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR | 1417 MIPS_CPU_LLSC; 1418 /* 1419 * Undocumented RM7000: Bit 29 in the info register of 1420 * the RM7000 v2.0 indicates if the TLB has 48 or 64 1421 * entries. 1422 * 1423 * 29 1 => 64 entry JTLB 1424 * 0 => 48 entry JTLB 1425 */ 1426 c->tlbsize = (read_c0_info() & (1 << 29)) ? 64 : 48; 1427 break; 1428 case PRID_IMP_R8000: 1429 c->cputype = CPU_R8000; 1430 __cpu_name[cpu] = "RM8000"; 1431 set_isa(c, MIPS_CPU_ISA_IV); 1432 c->options = MIPS_CPU_TLB | MIPS_CPU_4KEX | 1433 MIPS_CPU_FPU | MIPS_CPU_32FPR | 1434 MIPS_CPU_LLSC; 1435 c->tlbsize = 384; /* has weird TLB: 3-way x 128 */ 1436 break; 1437 case PRID_IMP_R10000: 1438 c->cputype = CPU_R10000; 1439 __cpu_name[cpu] = "R10000"; 1440 set_isa(c, MIPS_CPU_ISA_IV); 1441 c->options = MIPS_CPU_TLB | MIPS_CPU_4K_CACHE | MIPS_CPU_4KEX | 1442 MIPS_CPU_FPU | MIPS_CPU_32FPR | 1443 MIPS_CPU_COUNTER | MIPS_CPU_WATCH | 1444 MIPS_CPU_LLSC; 1445 c->tlbsize = 64; 1446 break; 1447 case PRID_IMP_R12000: 1448 c->cputype = CPU_R12000; 1449 __cpu_name[cpu] = "R12000"; 1450 set_isa(c, MIPS_CPU_ISA_IV); 1451 c->options = MIPS_CPU_TLB | MIPS_CPU_4K_CACHE | MIPS_CPU_4KEX | 1452 MIPS_CPU_FPU | MIPS_CPU_32FPR | 1453 MIPS_CPU_COUNTER | MIPS_CPU_WATCH | 1454 MIPS_CPU_LLSC | MIPS_CPU_BP_GHIST; 1455 c->tlbsize = 64; 1456 break; 1457 case PRID_IMP_R14000: 1458 if (((c->processor_id >> 4) & 0x0f) > 2) { 1459 c->cputype = CPU_R16000; 1460 __cpu_name[cpu] = "R16000"; 1461 } else { 1462 c->cputype = CPU_R14000; 1463 __cpu_name[cpu] = "R14000"; 1464 } 1465 set_isa(c, MIPS_CPU_ISA_IV); 1466 c->options = MIPS_CPU_TLB | MIPS_CPU_4K_CACHE | MIPS_CPU_4KEX | 1467 MIPS_CPU_FPU | MIPS_CPU_32FPR | 1468 MIPS_CPU_COUNTER | MIPS_CPU_WATCH | 1469 MIPS_CPU_LLSC | MIPS_CPU_BP_GHIST; 1470 c->tlbsize = 64; 1471 break; 1472 case PRID_IMP_LOONGSON_64: /* Loongson-2/3 */ 1473 switch (c->processor_id & PRID_REV_MASK) { 1474 case PRID_REV_LOONGSON2E: 1475 c->cputype = CPU_LOONGSON2; 1476 __cpu_name[cpu] = "ICT Loongson-2"; 1477 set_elf_platform(cpu, "loongson2e"); 1478 set_isa(c, MIPS_CPU_ISA_III); 1479 c->fpu_msk31 |= FPU_CSR_CONDX; 1480 break; 1481 case PRID_REV_LOONGSON2F: 1482 c->cputype = CPU_LOONGSON2; 1483 __cpu_name[cpu] = "ICT Loongson-2"; 1484 set_elf_platform(cpu, "loongson2f"); 1485 set_isa(c, MIPS_CPU_ISA_III); 1486 c->fpu_msk31 |= FPU_CSR_CONDX; 1487 break; 1488 case PRID_REV_LOONGSON3A_R1: 1489 c->cputype = CPU_LOONGSON3; 1490 __cpu_name[cpu] = "ICT Loongson-3"; 1491 set_elf_platform(cpu, "loongson3a"); 1492 set_isa(c, MIPS_CPU_ISA_M64R1); 1493 break; 1494 case PRID_REV_LOONGSON3B_R1: 1495 case PRID_REV_LOONGSON3B_R2: 1496 c->cputype = CPU_LOONGSON3; 1497 __cpu_name[cpu] = "ICT Loongson-3"; 1498 set_elf_platform(cpu, "loongson3b"); 1499 set_isa(c, MIPS_CPU_ISA_M64R1); 1500 break; 1501 } 1502 1503 c->options = R4K_OPTS | 1504 MIPS_CPU_FPU | MIPS_CPU_LLSC | 1505 MIPS_CPU_32FPR; 1506 c->tlbsize = 64; 1507 c->writecombine = _CACHE_UNCACHED_ACCELERATED; 1508 break; 1509 case PRID_IMP_LOONGSON_32: /* Loongson-1 */ 1510 decode_configs(c); 1511 1512 c->cputype = CPU_LOONGSON1; 1513 1514 switch (c->processor_id & PRID_REV_MASK) { 1515 case PRID_REV_LOONGSON1B: 1516 __cpu_name[cpu] = "Loongson 1B"; 1517 break; 1518 } 1519 1520 break; 1521 } 1522 } 1523 1524 static inline void cpu_probe_mips(struct cpuinfo_mips *c, unsigned int cpu) 1525 { 1526 c->writecombine = _CACHE_UNCACHED_ACCELERATED; 1527 switch (c->processor_id & PRID_IMP_MASK) { 1528 case PRID_IMP_QEMU_GENERIC: 1529 c->writecombine = _CACHE_UNCACHED; 1530 c->cputype = CPU_QEMU_GENERIC; 1531 __cpu_name[cpu] = "MIPS GENERIC QEMU"; 1532 break; 1533 case PRID_IMP_4KC: 1534 c->cputype = CPU_4KC; 1535 c->writecombine = _CACHE_UNCACHED; 1536 __cpu_name[cpu] = "MIPS 4Kc"; 1537 break; 1538 case PRID_IMP_4KEC: 1539 case PRID_IMP_4KECR2: 1540 c->cputype = CPU_4KEC; 1541 c->writecombine = _CACHE_UNCACHED; 1542 __cpu_name[cpu] = "MIPS 4KEc"; 1543 break; 1544 case PRID_IMP_4KSC: 1545 case PRID_IMP_4KSD: 1546 c->cputype = CPU_4KSC; 1547 c->writecombine = _CACHE_UNCACHED; 1548 __cpu_name[cpu] = "MIPS 4KSc"; 1549 break; 1550 case PRID_IMP_5KC: 1551 c->cputype = CPU_5KC; 1552 c->writecombine = _CACHE_UNCACHED; 1553 __cpu_name[cpu] = "MIPS 5Kc"; 1554 break; 1555 case PRID_IMP_5KE: 1556 c->cputype = CPU_5KE; 1557 c->writecombine = _CACHE_UNCACHED; 1558 __cpu_name[cpu] = "MIPS 5KE"; 1559 break; 1560 case PRID_IMP_20KC: 1561 c->cputype = CPU_20KC; 1562 c->writecombine = _CACHE_UNCACHED; 1563 __cpu_name[cpu] = "MIPS 20Kc"; 1564 break; 1565 case PRID_IMP_24K: 1566 c->cputype = CPU_24K; 1567 c->writecombine = _CACHE_UNCACHED; 1568 __cpu_name[cpu] = "MIPS 24Kc"; 1569 break; 1570 case PRID_IMP_24KE: 1571 c->cputype = CPU_24K; 1572 c->writecombine = _CACHE_UNCACHED; 1573 __cpu_name[cpu] = "MIPS 24KEc"; 1574 break; 1575 case PRID_IMP_25KF: 1576 c->cputype = CPU_25KF; 1577 c->writecombine = _CACHE_UNCACHED; 1578 __cpu_name[cpu] = "MIPS 25Kc"; 1579 break; 1580 case PRID_IMP_34K: 1581 c->cputype = CPU_34K; 1582 c->writecombine = _CACHE_UNCACHED; 1583 __cpu_name[cpu] = "MIPS 34Kc"; 1584 break; 1585 case PRID_IMP_74K: 1586 c->cputype = CPU_74K; 1587 c->writecombine = _CACHE_UNCACHED; 1588 __cpu_name[cpu] = "MIPS 74Kc"; 1589 break; 1590 case PRID_IMP_M14KC: 1591 c->cputype = CPU_M14KC; 1592 c->writecombine = _CACHE_UNCACHED; 1593 __cpu_name[cpu] = "MIPS M14Kc"; 1594 break; 1595 case PRID_IMP_M14KEC: 1596 c->cputype = CPU_M14KEC; 1597 c->writecombine = _CACHE_UNCACHED; 1598 __cpu_name[cpu] = "MIPS M14KEc"; 1599 break; 1600 case PRID_IMP_1004K: 1601 c->cputype = CPU_1004K; 1602 c->writecombine = _CACHE_UNCACHED; 1603 __cpu_name[cpu] = "MIPS 1004Kc"; 1604 break; 1605 case PRID_IMP_1074K: 1606 c->cputype = CPU_1074K; 1607 c->writecombine = _CACHE_UNCACHED; 1608 __cpu_name[cpu] = "MIPS 1074Kc"; 1609 break; 1610 case PRID_IMP_INTERAPTIV_UP: 1611 c->cputype = CPU_INTERAPTIV; 1612 __cpu_name[cpu] = "MIPS interAptiv"; 1613 break; 1614 case PRID_IMP_INTERAPTIV_MP: 1615 c->cputype = CPU_INTERAPTIV; 1616 __cpu_name[cpu] = "MIPS interAptiv (multi)"; 1617 break; 1618 case PRID_IMP_PROAPTIV_UP: 1619 c->cputype = CPU_PROAPTIV; 1620 __cpu_name[cpu] = "MIPS proAptiv"; 1621 break; 1622 case PRID_IMP_PROAPTIV_MP: 1623 c->cputype = CPU_PROAPTIV; 1624 __cpu_name[cpu] = "MIPS proAptiv (multi)"; 1625 break; 1626 case PRID_IMP_P5600: 1627 c->cputype = CPU_P5600; 1628 __cpu_name[cpu] = "MIPS P5600"; 1629 break; 1630 case PRID_IMP_P6600: 1631 c->cputype = CPU_P6600; 1632 __cpu_name[cpu] = "MIPS P6600"; 1633 break; 1634 case PRID_IMP_I6400: 1635 c->cputype = CPU_I6400; 1636 __cpu_name[cpu] = "MIPS I6400"; 1637 break; 1638 case PRID_IMP_M5150: 1639 c->cputype = CPU_M5150; 1640 __cpu_name[cpu] = "MIPS M5150"; 1641 break; 1642 case PRID_IMP_M6250: 1643 c->cputype = CPU_M6250; 1644 __cpu_name[cpu] = "MIPS M6250"; 1645 break; 1646 } 1647 1648 decode_configs(c); 1649 1650 spram_config(); 1651 } 1652 1653 static inline void cpu_probe_alchemy(struct cpuinfo_mips *c, unsigned int cpu) 1654 { 1655 decode_configs(c); 1656 switch (c->processor_id & PRID_IMP_MASK) { 1657 case PRID_IMP_AU1_REV1: 1658 case PRID_IMP_AU1_REV2: 1659 c->cputype = CPU_ALCHEMY; 1660 switch ((c->processor_id >> 24) & 0xff) { 1661 case 0: 1662 __cpu_name[cpu] = "Au1000"; 1663 break; 1664 case 1: 1665 __cpu_name[cpu] = "Au1500"; 1666 break; 1667 case 2: 1668 __cpu_name[cpu] = "Au1100"; 1669 break; 1670 case 3: 1671 __cpu_name[cpu] = "Au1550"; 1672 break; 1673 case 4: 1674 __cpu_name[cpu] = "Au1200"; 1675 if ((c->processor_id & PRID_REV_MASK) == 2) 1676 __cpu_name[cpu] = "Au1250"; 1677 break; 1678 case 5: 1679 __cpu_name[cpu] = "Au1210"; 1680 break; 1681 default: 1682 __cpu_name[cpu] = "Au1xxx"; 1683 break; 1684 } 1685 break; 1686 } 1687 } 1688 1689 static inline void cpu_probe_sibyte(struct cpuinfo_mips *c, unsigned int cpu) 1690 { 1691 decode_configs(c); 1692 1693 c->writecombine = _CACHE_UNCACHED_ACCELERATED; 1694 switch (c->processor_id & PRID_IMP_MASK) { 1695 case PRID_IMP_SB1: 1696 c->cputype = CPU_SB1; 1697 __cpu_name[cpu] = "SiByte SB1"; 1698 /* FPU in pass1 is known to have issues. */ 1699 if ((c->processor_id & PRID_REV_MASK) < 0x02) 1700 c->options &= ~(MIPS_CPU_FPU | MIPS_CPU_32FPR); 1701 break; 1702 case PRID_IMP_SB1A: 1703 c->cputype = CPU_SB1A; 1704 __cpu_name[cpu] = "SiByte SB1A"; 1705 break; 1706 } 1707 } 1708 1709 static inline void cpu_probe_sandcraft(struct cpuinfo_mips *c, unsigned int cpu) 1710 { 1711 decode_configs(c); 1712 switch (c->processor_id & PRID_IMP_MASK) { 1713 case PRID_IMP_SR71000: 1714 c->cputype = CPU_SR71000; 1715 __cpu_name[cpu] = "Sandcraft SR71000"; 1716 c->scache.ways = 8; 1717 c->tlbsize = 64; 1718 break; 1719 } 1720 } 1721 1722 static inline void cpu_probe_nxp(struct cpuinfo_mips *c, unsigned int cpu) 1723 { 1724 decode_configs(c); 1725 switch (c->processor_id & PRID_IMP_MASK) { 1726 case PRID_IMP_PR4450: 1727 c->cputype = CPU_PR4450; 1728 __cpu_name[cpu] = "Philips PR4450"; 1729 set_isa(c, MIPS_CPU_ISA_M32R1); 1730 break; 1731 } 1732 } 1733 1734 static inline void cpu_probe_broadcom(struct cpuinfo_mips *c, unsigned int cpu) 1735 { 1736 decode_configs(c); 1737 switch (c->processor_id & PRID_IMP_MASK) { 1738 case PRID_IMP_BMIPS32_REV4: 1739 case PRID_IMP_BMIPS32_REV8: 1740 c->cputype = CPU_BMIPS32; 1741 __cpu_name[cpu] = "Broadcom BMIPS32"; 1742 set_elf_platform(cpu, "bmips32"); 1743 break; 1744 case PRID_IMP_BMIPS3300: 1745 case PRID_IMP_BMIPS3300_ALT: 1746 case PRID_IMP_BMIPS3300_BUG: 1747 c->cputype = CPU_BMIPS3300; 1748 __cpu_name[cpu] = "Broadcom BMIPS3300"; 1749 set_elf_platform(cpu, "bmips3300"); 1750 break; 1751 case PRID_IMP_BMIPS43XX: { 1752 int rev = c->processor_id & PRID_REV_MASK; 1753 1754 if (rev >= PRID_REV_BMIPS4380_LO && 1755 rev <= PRID_REV_BMIPS4380_HI) { 1756 c->cputype = CPU_BMIPS4380; 1757 __cpu_name[cpu] = "Broadcom BMIPS4380"; 1758 set_elf_platform(cpu, "bmips4380"); 1759 c->options |= MIPS_CPU_RIXI; 1760 } else { 1761 c->cputype = CPU_BMIPS4350; 1762 __cpu_name[cpu] = "Broadcom BMIPS4350"; 1763 set_elf_platform(cpu, "bmips4350"); 1764 } 1765 break; 1766 } 1767 case PRID_IMP_BMIPS5000: 1768 case PRID_IMP_BMIPS5200: 1769 c->cputype = CPU_BMIPS5000; 1770 if ((c->processor_id & PRID_IMP_MASK) == PRID_IMP_BMIPS5200) 1771 __cpu_name[cpu] = "Broadcom BMIPS5200"; 1772 else 1773 __cpu_name[cpu] = "Broadcom BMIPS5000"; 1774 set_elf_platform(cpu, "bmips5000"); 1775 c->options |= MIPS_CPU_ULRI | MIPS_CPU_RIXI; 1776 break; 1777 } 1778 } 1779 1780 static inline void cpu_probe_cavium(struct cpuinfo_mips *c, unsigned int cpu) 1781 { 1782 decode_configs(c); 1783 switch (c->processor_id & PRID_IMP_MASK) { 1784 case PRID_IMP_CAVIUM_CN38XX: 1785 case PRID_IMP_CAVIUM_CN31XX: 1786 case PRID_IMP_CAVIUM_CN30XX: 1787 c->cputype = CPU_CAVIUM_OCTEON; 1788 __cpu_name[cpu] = "Cavium Octeon"; 1789 goto platform; 1790 case PRID_IMP_CAVIUM_CN58XX: 1791 case PRID_IMP_CAVIUM_CN56XX: 1792 case PRID_IMP_CAVIUM_CN50XX: 1793 case PRID_IMP_CAVIUM_CN52XX: 1794 c->cputype = CPU_CAVIUM_OCTEON_PLUS; 1795 __cpu_name[cpu] = "Cavium Octeon+"; 1796 platform: 1797 set_elf_platform(cpu, "octeon"); 1798 break; 1799 case PRID_IMP_CAVIUM_CN61XX: 1800 case PRID_IMP_CAVIUM_CN63XX: 1801 case PRID_IMP_CAVIUM_CN66XX: 1802 case PRID_IMP_CAVIUM_CN68XX: 1803 case PRID_IMP_CAVIUM_CNF71XX: 1804 c->cputype = CPU_CAVIUM_OCTEON2; 1805 __cpu_name[cpu] = "Cavium Octeon II"; 1806 set_elf_platform(cpu, "octeon2"); 1807 break; 1808 case PRID_IMP_CAVIUM_CN70XX: 1809 case PRID_IMP_CAVIUM_CN73XX: 1810 case PRID_IMP_CAVIUM_CNF75XX: 1811 case PRID_IMP_CAVIUM_CN78XX: 1812 c->cputype = CPU_CAVIUM_OCTEON3; 1813 __cpu_name[cpu] = "Cavium Octeon III"; 1814 set_elf_platform(cpu, "octeon3"); 1815 break; 1816 default: 1817 printk(KERN_INFO "Unknown Octeon chip!\n"); 1818 c->cputype = CPU_UNKNOWN; 1819 break; 1820 } 1821 } 1822 1823 static inline void cpu_probe_loongson(struct cpuinfo_mips *c, unsigned int cpu) 1824 { 1825 switch (c->processor_id & PRID_IMP_MASK) { 1826 case PRID_IMP_LOONGSON_64: /* Loongson-2/3 */ 1827 switch (c->processor_id & PRID_REV_MASK) { 1828 case PRID_REV_LOONGSON3A_R2: 1829 c->cputype = CPU_LOONGSON3; 1830 __cpu_name[cpu] = "ICT Loongson-3"; 1831 set_elf_platform(cpu, "loongson3a"); 1832 set_isa(c, MIPS_CPU_ISA_M64R2); 1833 break; 1834 } 1835 1836 decode_configs(c); 1837 c->options |= MIPS_CPU_FTLB | MIPS_CPU_TLBINV | MIPS_CPU_LDPTE; 1838 c->writecombine = _CACHE_UNCACHED_ACCELERATED; 1839 break; 1840 default: 1841 panic("Unknown Loongson Processor ID!"); 1842 break; 1843 } 1844 } 1845 1846 static inline void cpu_probe_ingenic(struct cpuinfo_mips *c, unsigned int cpu) 1847 { 1848 decode_configs(c); 1849 /* JZRISC does not implement the CP0 counter. */ 1850 c->options &= ~MIPS_CPU_COUNTER; 1851 BUG_ON(!__builtin_constant_p(cpu_has_counter) || cpu_has_counter); 1852 switch (c->processor_id & PRID_IMP_MASK) { 1853 case PRID_IMP_JZRISC: 1854 c->cputype = CPU_JZRISC; 1855 c->writecombine = _CACHE_UNCACHED_ACCELERATED; 1856 __cpu_name[cpu] = "Ingenic JZRISC"; 1857 break; 1858 default: 1859 panic("Unknown Ingenic Processor ID!"); 1860 break; 1861 } 1862 } 1863 1864 static inline void cpu_probe_netlogic(struct cpuinfo_mips *c, int cpu) 1865 { 1866 decode_configs(c); 1867 1868 if ((c->processor_id & PRID_IMP_MASK) == PRID_IMP_NETLOGIC_AU13XX) { 1869 c->cputype = CPU_ALCHEMY; 1870 __cpu_name[cpu] = "Au1300"; 1871 /* following stuff is not for Alchemy */ 1872 return; 1873 } 1874 1875 c->options = (MIPS_CPU_TLB | 1876 MIPS_CPU_4KEX | 1877 MIPS_CPU_COUNTER | 1878 MIPS_CPU_DIVEC | 1879 MIPS_CPU_WATCH | 1880 MIPS_CPU_EJTAG | 1881 MIPS_CPU_LLSC); 1882 1883 switch (c->processor_id & PRID_IMP_MASK) { 1884 case PRID_IMP_NETLOGIC_XLP2XX: 1885 case PRID_IMP_NETLOGIC_XLP9XX: 1886 case PRID_IMP_NETLOGIC_XLP5XX: 1887 c->cputype = CPU_XLP; 1888 __cpu_name[cpu] = "Broadcom XLPII"; 1889 break; 1890 1891 case PRID_IMP_NETLOGIC_XLP8XX: 1892 case PRID_IMP_NETLOGIC_XLP3XX: 1893 c->cputype = CPU_XLP; 1894 __cpu_name[cpu] = "Netlogic XLP"; 1895 break; 1896 1897 case PRID_IMP_NETLOGIC_XLR732: 1898 case PRID_IMP_NETLOGIC_XLR716: 1899 case PRID_IMP_NETLOGIC_XLR532: 1900 case PRID_IMP_NETLOGIC_XLR308: 1901 case PRID_IMP_NETLOGIC_XLR532C: 1902 case PRID_IMP_NETLOGIC_XLR516C: 1903 case PRID_IMP_NETLOGIC_XLR508C: 1904 case PRID_IMP_NETLOGIC_XLR308C: 1905 c->cputype = CPU_XLR; 1906 __cpu_name[cpu] = "Netlogic XLR"; 1907 break; 1908 1909 case PRID_IMP_NETLOGIC_XLS608: 1910 case PRID_IMP_NETLOGIC_XLS408: 1911 case PRID_IMP_NETLOGIC_XLS404: 1912 case PRID_IMP_NETLOGIC_XLS208: 1913 case PRID_IMP_NETLOGIC_XLS204: 1914 case PRID_IMP_NETLOGIC_XLS108: 1915 case PRID_IMP_NETLOGIC_XLS104: 1916 case PRID_IMP_NETLOGIC_XLS616B: 1917 case PRID_IMP_NETLOGIC_XLS608B: 1918 case PRID_IMP_NETLOGIC_XLS416B: 1919 case PRID_IMP_NETLOGIC_XLS412B: 1920 case PRID_IMP_NETLOGIC_XLS408B: 1921 case PRID_IMP_NETLOGIC_XLS404B: 1922 c->cputype = CPU_XLR; 1923 __cpu_name[cpu] = "Netlogic XLS"; 1924 break; 1925 1926 default: 1927 pr_info("Unknown Netlogic chip id [%02x]!\n", 1928 c->processor_id); 1929 c->cputype = CPU_XLR; 1930 break; 1931 } 1932 1933 if (c->cputype == CPU_XLP) { 1934 set_isa(c, MIPS_CPU_ISA_M64R2); 1935 c->options |= (MIPS_CPU_FPU | MIPS_CPU_ULRI | MIPS_CPU_MCHECK); 1936 /* This will be updated again after all threads are woken up */ 1937 c->tlbsize = ((read_c0_config6() >> 16) & 0xffff) + 1; 1938 } else { 1939 set_isa(c, MIPS_CPU_ISA_M64R1); 1940 c->tlbsize = ((read_c0_config1() >> 25) & 0x3f) + 1; 1941 } 1942 c->kscratch_mask = 0xf; 1943 } 1944 1945 #ifdef CONFIG_64BIT 1946 /* For use by uaccess.h */ 1947 u64 __ua_limit; 1948 EXPORT_SYMBOL(__ua_limit); 1949 #endif 1950 1951 const char *__cpu_name[NR_CPUS]; 1952 const char *__elf_platform; 1953 1954 void cpu_probe(void) 1955 { 1956 struct cpuinfo_mips *c = ¤t_cpu_data; 1957 unsigned int cpu = smp_processor_id(); 1958 1959 /* 1960 * Set a default elf platform, cpu probe may later 1961 * overwrite it with a more precise value 1962 */ 1963 set_elf_platform(cpu, "mips"); 1964 1965 c->processor_id = PRID_IMP_UNKNOWN; 1966 c->fpu_id = FPIR_IMP_NONE; 1967 c->cputype = CPU_UNKNOWN; 1968 c->writecombine = _CACHE_UNCACHED; 1969 1970 c->fpu_csr31 = FPU_CSR_RN; 1971 c->fpu_msk31 = FPU_CSR_RSVD | FPU_CSR_ABS2008 | FPU_CSR_NAN2008; 1972 1973 c->processor_id = read_c0_prid(); 1974 switch (c->processor_id & PRID_COMP_MASK) { 1975 case PRID_COMP_LEGACY: 1976 cpu_probe_legacy(c, cpu); 1977 break; 1978 case PRID_COMP_MIPS: 1979 cpu_probe_mips(c, cpu); 1980 break; 1981 case PRID_COMP_ALCHEMY: 1982 cpu_probe_alchemy(c, cpu); 1983 break; 1984 case PRID_COMP_SIBYTE: 1985 cpu_probe_sibyte(c, cpu); 1986 break; 1987 case PRID_COMP_BROADCOM: 1988 cpu_probe_broadcom(c, cpu); 1989 break; 1990 case PRID_COMP_SANDCRAFT: 1991 cpu_probe_sandcraft(c, cpu); 1992 break; 1993 case PRID_COMP_NXP: 1994 cpu_probe_nxp(c, cpu); 1995 break; 1996 case PRID_COMP_CAVIUM: 1997 cpu_probe_cavium(c, cpu); 1998 break; 1999 case PRID_COMP_LOONGSON: 2000 cpu_probe_loongson(c, cpu); 2001 break; 2002 case PRID_COMP_INGENIC_D0: 2003 case PRID_COMP_INGENIC_D1: 2004 case PRID_COMP_INGENIC_E1: 2005 cpu_probe_ingenic(c, cpu); 2006 break; 2007 case PRID_COMP_NETLOGIC: 2008 cpu_probe_netlogic(c, cpu); 2009 break; 2010 } 2011 2012 BUG_ON(!__cpu_name[cpu]); 2013 BUG_ON(c->cputype == CPU_UNKNOWN); 2014 2015 /* 2016 * Platform code can force the cpu type to optimize code 2017 * generation. In that case be sure the cpu type is correctly 2018 * manually setup otherwise it could trigger some nasty bugs. 2019 */ 2020 BUG_ON(current_cpu_type() != c->cputype); 2021 2022 if (cpu_has_rixi) { 2023 /* Enable the RIXI exceptions */ 2024 set_c0_pagegrain(PG_IEC); 2025 back_to_back_c0_hazard(); 2026 /* Verify the IEC bit is set */ 2027 if (read_c0_pagegrain() & PG_IEC) 2028 c->options |= MIPS_CPU_RIXIEX; 2029 } 2030 2031 if (mips_fpu_disabled) 2032 c->options &= ~MIPS_CPU_FPU; 2033 2034 if (mips_dsp_disabled) 2035 c->ases &= ~(MIPS_ASE_DSP | MIPS_ASE_DSP2P); 2036 2037 if (mips_htw_disabled) { 2038 c->options &= ~MIPS_CPU_HTW; 2039 write_c0_pwctl(read_c0_pwctl() & 2040 ~(1 << MIPS_PWCTL_PWEN_SHIFT)); 2041 } 2042 2043 if (c->options & MIPS_CPU_FPU) 2044 cpu_set_fpu_opts(c); 2045 else 2046 cpu_set_nofpu_opts(c); 2047 2048 if (cpu_has_bp_ghist) 2049 write_c0_r10k_diag(read_c0_r10k_diag() | 2050 R10K_DIAG_E_GHIST); 2051 2052 if (cpu_has_mips_r2_r6) { 2053 c->srsets = ((read_c0_srsctl() >> 26) & 0x0f) + 1; 2054 /* R2 has Performance Counter Interrupt indicator */ 2055 c->options |= MIPS_CPU_PCI; 2056 } 2057 else 2058 c->srsets = 1; 2059 2060 if (cpu_has_mips_r6) 2061 elf_hwcap |= HWCAP_MIPS_R6; 2062 2063 if (cpu_has_msa) { 2064 c->msa_id = cpu_get_msa_id(); 2065 WARN(c->msa_id & MSA_IR_WRPF, 2066 "Vector register partitioning unimplemented!"); 2067 elf_hwcap |= HWCAP_MIPS_MSA; 2068 } 2069 2070 if (cpu_has_vz) 2071 cpu_probe_vz(c); 2072 2073 cpu_probe_vmbits(c); 2074 2075 #ifdef CONFIG_64BIT 2076 if (cpu == 0) 2077 __ua_limit = ~((1ull << cpu_vmbits) - 1); 2078 #endif 2079 } 2080 2081 void cpu_report(void) 2082 { 2083 struct cpuinfo_mips *c = ¤t_cpu_data; 2084 2085 pr_info("CPU%d revision is: %08x (%s)\n", 2086 smp_processor_id(), c->processor_id, cpu_name_string()); 2087 if (c->options & MIPS_CPU_FPU) 2088 printk(KERN_INFO "FPU revision is: %08x\n", c->fpu_id); 2089 if (cpu_has_msa) 2090 pr_info("MSA revision is: %08x\n", c->msa_id); 2091 } 2092