1 /* 2 * Processor capabilities determination functions. 3 * 4 * Copyright (C) xxxx the Anonymous 5 * Copyright (C) 1994 - 2006 Ralf Baechle 6 * Copyright (C) 2003, 2004 Maciej W. Rozycki 7 * Copyright (C) 2001, 2004, 2011, 2012 MIPS Technologies, Inc. 8 * 9 * This program is free software; you can redistribute it and/or 10 * modify it under the terms of the GNU General Public License 11 * as published by the Free Software Foundation; either version 12 * 2 of the License, or (at your option) any later version. 13 */ 14 #include <linux/init.h> 15 #include <linux/kernel.h> 16 #include <linux/ptrace.h> 17 #include <linux/smp.h> 18 #include <linux/stddef.h> 19 #include <linux/export.h> 20 21 #include <asm/bugs.h> 22 #include <asm/cpu.h> 23 #include <asm/cpu-type.h> 24 #include <asm/fpu.h> 25 #include <asm/mipsregs.h> 26 #include <asm/mipsmtregs.h> 27 #include <asm/msa.h> 28 #include <asm/watch.h> 29 #include <asm/elf.h> 30 #include <asm/pgtable-bits.h> 31 #include <asm/spram.h> 32 #include <asm/uaccess.h> 33 34 static int mips_fpu_disabled; 35 36 static int __init fpu_disable(char *s) 37 { 38 cpu_data[0].options &= ~MIPS_CPU_FPU; 39 mips_fpu_disabled = 1; 40 41 return 1; 42 } 43 44 __setup("nofpu", fpu_disable); 45 46 int mips_dsp_disabled; 47 48 static int __init dsp_disable(char *s) 49 { 50 cpu_data[0].ases &= ~(MIPS_ASE_DSP | MIPS_ASE_DSP2P); 51 mips_dsp_disabled = 1; 52 53 return 1; 54 } 55 56 __setup("nodsp", dsp_disable); 57 58 static int mips_htw_disabled; 59 60 static int __init htw_disable(char *s) 61 { 62 mips_htw_disabled = 1; 63 cpu_data[0].options &= ~MIPS_CPU_HTW; 64 write_c0_pwctl(read_c0_pwctl() & 65 ~(1 << MIPS_PWCTL_PWEN_SHIFT)); 66 67 return 1; 68 } 69 70 __setup("nohtw", htw_disable); 71 72 static int mips_ftlb_disabled; 73 static int mips_has_ftlb_configured; 74 75 static void set_ftlb_enable(struct cpuinfo_mips *c, int enable); 76 77 static int __init ftlb_disable(char *s) 78 { 79 unsigned int config4, mmuextdef; 80 81 /* 82 * If the core hasn't done any FTLB configuration, there is nothing 83 * for us to do here. 84 */ 85 if (!mips_has_ftlb_configured) 86 return 1; 87 88 /* Disable it in the boot cpu */ 89 set_ftlb_enable(&cpu_data[0], 0); 90 91 back_to_back_c0_hazard(); 92 93 config4 = read_c0_config4(); 94 95 /* Check that FTLB has been disabled */ 96 mmuextdef = config4 & MIPS_CONF4_MMUEXTDEF; 97 /* MMUSIZEEXT == VTLB ON, FTLB OFF */ 98 if (mmuextdef == MIPS_CONF4_MMUEXTDEF_FTLBSIZEEXT) { 99 /* This should never happen */ 100 pr_warn("FTLB could not be disabled!\n"); 101 return 1; 102 } 103 104 mips_ftlb_disabled = 1; 105 mips_has_ftlb_configured = 0; 106 107 /* 108 * noftlb is mainly used for debug purposes so print 109 * an informative message instead of using pr_debug() 110 */ 111 pr_info("FTLB has been disabled\n"); 112 113 /* 114 * Some of these bits are duplicated in the decode_config4. 115 * MIPS_CONF4_MMUEXTDEF_MMUSIZEEXT is the only possible case 116 * once FTLB has been disabled so undo what decode_config4 did. 117 */ 118 cpu_data[0].tlbsize -= cpu_data[0].tlbsizeftlbways * 119 cpu_data[0].tlbsizeftlbsets; 120 cpu_data[0].tlbsizeftlbsets = 0; 121 cpu_data[0].tlbsizeftlbways = 0; 122 123 return 1; 124 } 125 126 __setup("noftlb", ftlb_disable); 127 128 129 static inline void check_errata(void) 130 { 131 struct cpuinfo_mips *c = ¤t_cpu_data; 132 133 switch (current_cpu_type()) { 134 case CPU_34K: 135 /* 136 * Erratum "RPS May Cause Incorrect Instruction Execution" 137 * This code only handles VPE0, any SMP/RTOS code 138 * making use of VPE1 will be responsable for that VPE. 139 */ 140 if ((c->processor_id & PRID_REV_MASK) <= PRID_REV_34K_V1_0_2) 141 write_c0_config7(read_c0_config7() | MIPS_CONF7_RPS); 142 break; 143 default: 144 break; 145 } 146 } 147 148 void __init check_bugs32(void) 149 { 150 check_errata(); 151 } 152 153 /* 154 * Probe whether cpu has config register by trying to play with 155 * alternate cache bit and see whether it matters. 156 * It's used by cpu_probe to distinguish between R3000A and R3081. 157 */ 158 static inline int cpu_has_confreg(void) 159 { 160 #ifdef CONFIG_CPU_R3000 161 extern unsigned long r3k_cache_size(unsigned long); 162 unsigned long size1, size2; 163 unsigned long cfg = read_c0_conf(); 164 165 size1 = r3k_cache_size(ST0_ISC); 166 write_c0_conf(cfg ^ R30XX_CONF_AC); 167 size2 = r3k_cache_size(ST0_ISC); 168 write_c0_conf(cfg); 169 return size1 != size2; 170 #else 171 return 0; 172 #endif 173 } 174 175 static inline void set_elf_platform(int cpu, const char *plat) 176 { 177 if (cpu == 0) 178 __elf_platform = plat; 179 } 180 181 /* 182 * Get the FPU Implementation/Revision. 183 */ 184 static inline unsigned long cpu_get_fpu_id(void) 185 { 186 unsigned long tmp, fpu_id; 187 188 tmp = read_c0_status(); 189 __enable_fpu(FPU_AS_IS); 190 fpu_id = read_32bit_cp1_register(CP1_REVISION); 191 write_c0_status(tmp); 192 return fpu_id; 193 } 194 195 /* 196 * Check the CPU has an FPU the official way. 197 */ 198 static inline int __cpu_has_fpu(void) 199 { 200 return (cpu_get_fpu_id() & FPIR_IMP_MASK) != FPIR_IMP_NONE; 201 } 202 203 static inline unsigned long cpu_get_msa_id(void) 204 { 205 unsigned long status, msa_id; 206 207 status = read_c0_status(); 208 __enable_fpu(FPU_64BIT); 209 enable_msa(); 210 msa_id = read_msa_ir(); 211 disable_msa(); 212 write_c0_status(status); 213 return msa_id; 214 } 215 216 static inline void cpu_probe_vmbits(struct cpuinfo_mips *c) 217 { 218 #ifdef __NEED_VMBITS_PROBE 219 write_c0_entryhi(0x3fffffffffffe000ULL); 220 back_to_back_c0_hazard(); 221 c->vmbits = fls64(read_c0_entryhi() & 0x3fffffffffffe000ULL); 222 #endif 223 } 224 225 static void set_isa(struct cpuinfo_mips *c, unsigned int isa) 226 { 227 switch (isa) { 228 case MIPS_CPU_ISA_M64R2: 229 c->isa_level |= MIPS_CPU_ISA_M32R2 | MIPS_CPU_ISA_M64R2; 230 case MIPS_CPU_ISA_M64R1: 231 c->isa_level |= MIPS_CPU_ISA_M32R1 | MIPS_CPU_ISA_M64R1; 232 case MIPS_CPU_ISA_V: 233 c->isa_level |= MIPS_CPU_ISA_V; 234 case MIPS_CPU_ISA_IV: 235 c->isa_level |= MIPS_CPU_ISA_IV; 236 case MIPS_CPU_ISA_III: 237 c->isa_level |= MIPS_CPU_ISA_II | MIPS_CPU_ISA_III; 238 break; 239 240 case MIPS_CPU_ISA_M32R2: 241 c->isa_level |= MIPS_CPU_ISA_M32R2; 242 case MIPS_CPU_ISA_M32R1: 243 c->isa_level |= MIPS_CPU_ISA_M32R1; 244 case MIPS_CPU_ISA_II: 245 c->isa_level |= MIPS_CPU_ISA_II; 246 break; 247 } 248 } 249 250 static char unknown_isa[] = KERN_ERR \ 251 "Unsupported ISA type, c0.config0: %d."; 252 253 static void set_ftlb_enable(struct cpuinfo_mips *c, int enable) 254 { 255 unsigned int config6; 256 257 /* It's implementation dependent how the FTLB can be enabled */ 258 switch (c->cputype) { 259 case CPU_PROAPTIV: 260 case CPU_P5600: 261 /* proAptiv & related cores use Config6 to enable the FTLB */ 262 config6 = read_c0_config6(); 263 if (enable) 264 /* Enable FTLB */ 265 write_c0_config6(config6 | MIPS_CONF6_FTLBEN); 266 else 267 /* Disable FTLB */ 268 write_c0_config6(config6 & ~MIPS_CONF6_FTLBEN); 269 back_to_back_c0_hazard(); 270 break; 271 } 272 } 273 274 static inline unsigned int decode_config0(struct cpuinfo_mips *c) 275 { 276 unsigned int config0; 277 int isa; 278 279 config0 = read_c0_config(); 280 281 /* 282 * Look for Standard TLB or Dual VTLB and FTLB 283 */ 284 if ((((config0 & MIPS_CONF_MT) >> 7) == 1) || 285 (((config0 & MIPS_CONF_MT) >> 7) == 4)) 286 c->options |= MIPS_CPU_TLB; 287 288 isa = (config0 & MIPS_CONF_AT) >> 13; 289 switch (isa) { 290 case 0: 291 switch ((config0 & MIPS_CONF_AR) >> 10) { 292 case 0: 293 set_isa(c, MIPS_CPU_ISA_M32R1); 294 break; 295 case 1: 296 set_isa(c, MIPS_CPU_ISA_M32R2); 297 break; 298 default: 299 goto unknown; 300 } 301 break; 302 case 2: 303 switch ((config0 & MIPS_CONF_AR) >> 10) { 304 case 0: 305 set_isa(c, MIPS_CPU_ISA_M64R1); 306 break; 307 case 1: 308 set_isa(c, MIPS_CPU_ISA_M64R2); 309 break; 310 default: 311 goto unknown; 312 } 313 break; 314 default: 315 goto unknown; 316 } 317 318 return config0 & MIPS_CONF_M; 319 320 unknown: 321 panic(unknown_isa, config0); 322 } 323 324 static inline unsigned int decode_config1(struct cpuinfo_mips *c) 325 { 326 unsigned int config1; 327 328 config1 = read_c0_config1(); 329 330 if (config1 & MIPS_CONF1_MD) 331 c->ases |= MIPS_ASE_MDMX; 332 if (config1 & MIPS_CONF1_WR) 333 c->options |= MIPS_CPU_WATCH; 334 if (config1 & MIPS_CONF1_CA) 335 c->ases |= MIPS_ASE_MIPS16; 336 if (config1 & MIPS_CONF1_EP) 337 c->options |= MIPS_CPU_EJTAG; 338 if (config1 & MIPS_CONF1_FP) { 339 c->options |= MIPS_CPU_FPU; 340 c->options |= MIPS_CPU_32FPR; 341 } 342 if (cpu_has_tlb) { 343 c->tlbsize = ((config1 & MIPS_CONF1_TLBS) >> 25) + 1; 344 c->tlbsizevtlb = c->tlbsize; 345 c->tlbsizeftlbsets = 0; 346 } 347 348 return config1 & MIPS_CONF_M; 349 } 350 351 static inline unsigned int decode_config2(struct cpuinfo_mips *c) 352 { 353 unsigned int config2; 354 355 config2 = read_c0_config2(); 356 357 if (config2 & MIPS_CONF2_SL) 358 c->scache.flags &= ~MIPS_CACHE_NOT_PRESENT; 359 360 return config2 & MIPS_CONF_M; 361 } 362 363 static inline unsigned int decode_config3(struct cpuinfo_mips *c) 364 { 365 unsigned int config3; 366 367 config3 = read_c0_config3(); 368 369 if (config3 & MIPS_CONF3_SM) { 370 c->ases |= MIPS_ASE_SMARTMIPS; 371 c->options |= MIPS_CPU_RIXI; 372 } 373 if (config3 & MIPS_CONF3_RXI) 374 c->options |= MIPS_CPU_RIXI; 375 if (config3 & MIPS_CONF3_DSP) 376 c->ases |= MIPS_ASE_DSP; 377 if (config3 & MIPS_CONF3_DSP2P) 378 c->ases |= MIPS_ASE_DSP2P; 379 if (config3 & MIPS_CONF3_VINT) 380 c->options |= MIPS_CPU_VINT; 381 if (config3 & MIPS_CONF3_VEIC) 382 c->options |= MIPS_CPU_VEIC; 383 if (config3 & MIPS_CONF3_MT) 384 c->ases |= MIPS_ASE_MIPSMT; 385 if (config3 & MIPS_CONF3_ULRI) 386 c->options |= MIPS_CPU_ULRI; 387 if (config3 & MIPS_CONF3_ISA) 388 c->options |= MIPS_CPU_MICROMIPS; 389 if (config3 & MIPS_CONF3_VZ) 390 c->ases |= MIPS_ASE_VZ; 391 if (config3 & MIPS_CONF3_SC) 392 c->options |= MIPS_CPU_SEGMENTS; 393 if (config3 & MIPS_CONF3_MSA) 394 c->ases |= MIPS_ASE_MSA; 395 /* Only tested on 32-bit cores */ 396 if ((config3 & MIPS_CONF3_PW) && config_enabled(CONFIG_32BIT)) 397 c->options |= MIPS_CPU_HTW; 398 399 return config3 & MIPS_CONF_M; 400 } 401 402 static inline unsigned int decode_config4(struct cpuinfo_mips *c) 403 { 404 unsigned int config4; 405 unsigned int newcf4; 406 unsigned int mmuextdef; 407 unsigned int ftlb_page = MIPS_CONF4_FTLBPAGESIZE; 408 409 config4 = read_c0_config4(); 410 411 if (cpu_has_tlb) { 412 if (((config4 & MIPS_CONF4_IE) >> 29) == 2) 413 c->options |= MIPS_CPU_TLBINV; 414 mmuextdef = config4 & MIPS_CONF4_MMUEXTDEF; 415 switch (mmuextdef) { 416 case MIPS_CONF4_MMUEXTDEF_MMUSIZEEXT: 417 c->tlbsize += (config4 & MIPS_CONF4_MMUSIZEEXT) * 0x40; 418 c->tlbsizevtlb = c->tlbsize; 419 break; 420 case MIPS_CONF4_MMUEXTDEF_VTLBSIZEEXT: 421 c->tlbsizevtlb += 422 ((config4 & MIPS_CONF4_VTLBSIZEEXT) >> 423 MIPS_CONF4_VTLBSIZEEXT_SHIFT) * 0x40; 424 c->tlbsize = c->tlbsizevtlb; 425 ftlb_page = MIPS_CONF4_VFTLBPAGESIZE; 426 /* fall through */ 427 case MIPS_CONF4_MMUEXTDEF_FTLBSIZEEXT: 428 if (mips_ftlb_disabled) 429 break; 430 newcf4 = (config4 & ~ftlb_page) | 431 (page_size_ftlb(mmuextdef) << 432 MIPS_CONF4_FTLBPAGESIZE_SHIFT); 433 write_c0_config4(newcf4); 434 back_to_back_c0_hazard(); 435 config4 = read_c0_config4(); 436 if (config4 != newcf4) { 437 pr_err("PAGE_SIZE 0x%lx is not supported by FTLB (config4=0x%x)\n", 438 PAGE_SIZE, config4); 439 /* Switch FTLB off */ 440 set_ftlb_enable(c, 0); 441 break; 442 } 443 c->tlbsizeftlbsets = 1 << 444 ((config4 & MIPS_CONF4_FTLBSETS) >> 445 MIPS_CONF4_FTLBSETS_SHIFT); 446 c->tlbsizeftlbways = ((config4 & MIPS_CONF4_FTLBWAYS) >> 447 MIPS_CONF4_FTLBWAYS_SHIFT) + 2; 448 c->tlbsize += c->tlbsizeftlbways * c->tlbsizeftlbsets; 449 mips_has_ftlb_configured = 1; 450 break; 451 } 452 } 453 454 c->kscratch_mask = (config4 >> 16) & 0xff; 455 456 return config4 & MIPS_CONF_M; 457 } 458 459 static inline unsigned int decode_config5(struct cpuinfo_mips *c) 460 { 461 unsigned int config5; 462 463 config5 = read_c0_config5(); 464 config5 &= ~(MIPS_CONF5_UFR | MIPS_CONF5_UFE); 465 write_c0_config5(config5); 466 467 if (config5 & MIPS_CONF5_EVA) 468 c->options |= MIPS_CPU_EVA; 469 if (config5 & MIPS_CONF5_MRP) 470 c->options |= MIPS_CPU_MAAR; 471 472 return config5 & MIPS_CONF_M; 473 } 474 475 static void decode_configs(struct cpuinfo_mips *c) 476 { 477 int ok; 478 479 /* MIPS32 or MIPS64 compliant CPU. */ 480 c->options = MIPS_CPU_4KEX | MIPS_CPU_4K_CACHE | MIPS_CPU_COUNTER | 481 MIPS_CPU_DIVEC | MIPS_CPU_LLSC | MIPS_CPU_MCHECK; 482 483 c->scache.flags = MIPS_CACHE_NOT_PRESENT; 484 485 /* Enable FTLB if present and not disabled */ 486 set_ftlb_enable(c, !mips_ftlb_disabled); 487 488 ok = decode_config0(c); /* Read Config registers. */ 489 BUG_ON(!ok); /* Arch spec violation! */ 490 if (ok) 491 ok = decode_config1(c); 492 if (ok) 493 ok = decode_config2(c); 494 if (ok) 495 ok = decode_config3(c); 496 if (ok) 497 ok = decode_config4(c); 498 if (ok) 499 ok = decode_config5(c); 500 501 mips_probe_watch_registers(c); 502 503 if (cpu_has_rixi) { 504 /* Enable the RIXI exceptions */ 505 write_c0_pagegrain(read_c0_pagegrain() | PG_IEC); 506 back_to_back_c0_hazard(); 507 /* Verify the IEC bit is set */ 508 if (read_c0_pagegrain() & PG_IEC) 509 c->options |= MIPS_CPU_RIXIEX; 510 } 511 512 #ifndef CONFIG_MIPS_CPS 513 if (cpu_has_mips_r2) { 514 c->core = get_ebase_cpunum(); 515 if (cpu_has_mipsmt) 516 c->core >>= fls(core_nvpes()) - 1; 517 } 518 #endif 519 } 520 521 #define R4K_OPTS (MIPS_CPU_TLB | MIPS_CPU_4KEX | MIPS_CPU_4K_CACHE \ 522 | MIPS_CPU_COUNTER) 523 524 static inline void cpu_probe_legacy(struct cpuinfo_mips *c, unsigned int cpu) 525 { 526 switch (c->processor_id & PRID_IMP_MASK) { 527 case PRID_IMP_R2000: 528 c->cputype = CPU_R2000; 529 __cpu_name[cpu] = "R2000"; 530 c->options = MIPS_CPU_TLB | MIPS_CPU_3K_CACHE | 531 MIPS_CPU_NOFPUEX; 532 if (__cpu_has_fpu()) 533 c->options |= MIPS_CPU_FPU; 534 c->tlbsize = 64; 535 break; 536 case PRID_IMP_R3000: 537 if ((c->processor_id & PRID_REV_MASK) == PRID_REV_R3000A) { 538 if (cpu_has_confreg()) { 539 c->cputype = CPU_R3081E; 540 __cpu_name[cpu] = "R3081"; 541 } else { 542 c->cputype = CPU_R3000A; 543 __cpu_name[cpu] = "R3000A"; 544 } 545 } else { 546 c->cputype = CPU_R3000; 547 __cpu_name[cpu] = "R3000"; 548 } 549 c->options = MIPS_CPU_TLB | MIPS_CPU_3K_CACHE | 550 MIPS_CPU_NOFPUEX; 551 if (__cpu_has_fpu()) 552 c->options |= MIPS_CPU_FPU; 553 c->tlbsize = 64; 554 break; 555 case PRID_IMP_R4000: 556 if (read_c0_config() & CONF_SC) { 557 if ((c->processor_id & PRID_REV_MASK) >= 558 PRID_REV_R4400) { 559 c->cputype = CPU_R4400PC; 560 __cpu_name[cpu] = "R4400PC"; 561 } else { 562 c->cputype = CPU_R4000PC; 563 __cpu_name[cpu] = "R4000PC"; 564 } 565 } else { 566 int cca = read_c0_config() & CONF_CM_CMASK; 567 int mc; 568 569 /* 570 * SC and MC versions can't be reliably told apart, 571 * but only the latter support coherent caching 572 * modes so assume the firmware has set the KSEG0 573 * coherency attribute reasonably (if uncached, we 574 * assume SC). 575 */ 576 switch (cca) { 577 case CONF_CM_CACHABLE_CE: 578 case CONF_CM_CACHABLE_COW: 579 case CONF_CM_CACHABLE_CUW: 580 mc = 1; 581 break; 582 default: 583 mc = 0; 584 break; 585 } 586 if ((c->processor_id & PRID_REV_MASK) >= 587 PRID_REV_R4400) { 588 c->cputype = mc ? CPU_R4400MC : CPU_R4400SC; 589 __cpu_name[cpu] = mc ? "R4400MC" : "R4400SC"; 590 } else { 591 c->cputype = mc ? CPU_R4000MC : CPU_R4000SC; 592 __cpu_name[cpu] = mc ? "R4000MC" : "R4000SC"; 593 } 594 } 595 596 set_isa(c, MIPS_CPU_ISA_III); 597 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR | 598 MIPS_CPU_WATCH | MIPS_CPU_VCE | 599 MIPS_CPU_LLSC; 600 c->tlbsize = 48; 601 break; 602 case PRID_IMP_VR41XX: 603 set_isa(c, MIPS_CPU_ISA_III); 604 c->options = R4K_OPTS; 605 c->tlbsize = 32; 606 switch (c->processor_id & 0xf0) { 607 case PRID_REV_VR4111: 608 c->cputype = CPU_VR4111; 609 __cpu_name[cpu] = "NEC VR4111"; 610 break; 611 case PRID_REV_VR4121: 612 c->cputype = CPU_VR4121; 613 __cpu_name[cpu] = "NEC VR4121"; 614 break; 615 case PRID_REV_VR4122: 616 if ((c->processor_id & 0xf) < 0x3) { 617 c->cputype = CPU_VR4122; 618 __cpu_name[cpu] = "NEC VR4122"; 619 } else { 620 c->cputype = CPU_VR4181A; 621 __cpu_name[cpu] = "NEC VR4181A"; 622 } 623 break; 624 case PRID_REV_VR4130: 625 if ((c->processor_id & 0xf) < 0x4) { 626 c->cputype = CPU_VR4131; 627 __cpu_name[cpu] = "NEC VR4131"; 628 } else { 629 c->cputype = CPU_VR4133; 630 c->options |= MIPS_CPU_LLSC; 631 __cpu_name[cpu] = "NEC VR4133"; 632 } 633 break; 634 default: 635 printk(KERN_INFO "Unexpected CPU of NEC VR4100 series\n"); 636 c->cputype = CPU_VR41XX; 637 __cpu_name[cpu] = "NEC Vr41xx"; 638 break; 639 } 640 break; 641 case PRID_IMP_R4300: 642 c->cputype = CPU_R4300; 643 __cpu_name[cpu] = "R4300"; 644 set_isa(c, MIPS_CPU_ISA_III); 645 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR | 646 MIPS_CPU_LLSC; 647 c->tlbsize = 32; 648 break; 649 case PRID_IMP_R4600: 650 c->cputype = CPU_R4600; 651 __cpu_name[cpu] = "R4600"; 652 set_isa(c, MIPS_CPU_ISA_III); 653 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR | 654 MIPS_CPU_LLSC; 655 c->tlbsize = 48; 656 break; 657 #if 0 658 case PRID_IMP_R4650: 659 /* 660 * This processor doesn't have an MMU, so it's not 661 * "real easy" to run Linux on it. It is left purely 662 * for documentation. Commented out because it shares 663 * it's c0_prid id number with the TX3900. 664 */ 665 c->cputype = CPU_R4650; 666 __cpu_name[cpu] = "R4650"; 667 set_isa(c, MIPS_CPU_ISA_III); 668 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_LLSC; 669 c->tlbsize = 48; 670 break; 671 #endif 672 case PRID_IMP_TX39: 673 c->options = MIPS_CPU_TLB | MIPS_CPU_TX39_CACHE; 674 675 if ((c->processor_id & 0xf0) == (PRID_REV_TX3927 & 0xf0)) { 676 c->cputype = CPU_TX3927; 677 __cpu_name[cpu] = "TX3927"; 678 c->tlbsize = 64; 679 } else { 680 switch (c->processor_id & PRID_REV_MASK) { 681 case PRID_REV_TX3912: 682 c->cputype = CPU_TX3912; 683 __cpu_name[cpu] = "TX3912"; 684 c->tlbsize = 32; 685 break; 686 case PRID_REV_TX3922: 687 c->cputype = CPU_TX3922; 688 __cpu_name[cpu] = "TX3922"; 689 c->tlbsize = 64; 690 break; 691 } 692 } 693 break; 694 case PRID_IMP_R4700: 695 c->cputype = CPU_R4700; 696 __cpu_name[cpu] = "R4700"; 697 set_isa(c, MIPS_CPU_ISA_III); 698 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR | 699 MIPS_CPU_LLSC; 700 c->tlbsize = 48; 701 break; 702 case PRID_IMP_TX49: 703 c->cputype = CPU_TX49XX; 704 __cpu_name[cpu] = "R49XX"; 705 set_isa(c, MIPS_CPU_ISA_III); 706 c->options = R4K_OPTS | MIPS_CPU_LLSC; 707 if (!(c->processor_id & 0x08)) 708 c->options |= MIPS_CPU_FPU | MIPS_CPU_32FPR; 709 c->tlbsize = 48; 710 break; 711 case PRID_IMP_R5000: 712 c->cputype = CPU_R5000; 713 __cpu_name[cpu] = "R5000"; 714 set_isa(c, MIPS_CPU_ISA_IV); 715 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR | 716 MIPS_CPU_LLSC; 717 c->tlbsize = 48; 718 break; 719 case PRID_IMP_R5432: 720 c->cputype = CPU_R5432; 721 __cpu_name[cpu] = "R5432"; 722 set_isa(c, MIPS_CPU_ISA_IV); 723 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR | 724 MIPS_CPU_WATCH | MIPS_CPU_LLSC; 725 c->tlbsize = 48; 726 break; 727 case PRID_IMP_R5500: 728 c->cputype = CPU_R5500; 729 __cpu_name[cpu] = "R5500"; 730 set_isa(c, MIPS_CPU_ISA_IV); 731 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR | 732 MIPS_CPU_WATCH | MIPS_CPU_LLSC; 733 c->tlbsize = 48; 734 break; 735 case PRID_IMP_NEVADA: 736 c->cputype = CPU_NEVADA; 737 __cpu_name[cpu] = "Nevada"; 738 set_isa(c, MIPS_CPU_ISA_IV); 739 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR | 740 MIPS_CPU_DIVEC | MIPS_CPU_LLSC; 741 c->tlbsize = 48; 742 break; 743 case PRID_IMP_R6000: 744 c->cputype = CPU_R6000; 745 __cpu_name[cpu] = "R6000"; 746 set_isa(c, MIPS_CPU_ISA_II); 747 c->options = MIPS_CPU_TLB | MIPS_CPU_FPU | 748 MIPS_CPU_LLSC; 749 c->tlbsize = 32; 750 break; 751 case PRID_IMP_R6000A: 752 c->cputype = CPU_R6000A; 753 __cpu_name[cpu] = "R6000A"; 754 set_isa(c, MIPS_CPU_ISA_II); 755 c->options = MIPS_CPU_TLB | MIPS_CPU_FPU | 756 MIPS_CPU_LLSC; 757 c->tlbsize = 32; 758 break; 759 case PRID_IMP_RM7000: 760 c->cputype = CPU_RM7000; 761 __cpu_name[cpu] = "RM7000"; 762 set_isa(c, MIPS_CPU_ISA_IV); 763 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR | 764 MIPS_CPU_LLSC; 765 /* 766 * Undocumented RM7000: Bit 29 in the info register of 767 * the RM7000 v2.0 indicates if the TLB has 48 or 64 768 * entries. 769 * 770 * 29 1 => 64 entry JTLB 771 * 0 => 48 entry JTLB 772 */ 773 c->tlbsize = (read_c0_info() & (1 << 29)) ? 64 : 48; 774 break; 775 case PRID_IMP_R8000: 776 c->cputype = CPU_R8000; 777 __cpu_name[cpu] = "RM8000"; 778 set_isa(c, MIPS_CPU_ISA_IV); 779 c->options = MIPS_CPU_TLB | MIPS_CPU_4KEX | 780 MIPS_CPU_FPU | MIPS_CPU_32FPR | 781 MIPS_CPU_LLSC; 782 c->tlbsize = 384; /* has weird TLB: 3-way x 128 */ 783 break; 784 case PRID_IMP_R10000: 785 c->cputype = CPU_R10000; 786 __cpu_name[cpu] = "R10000"; 787 set_isa(c, MIPS_CPU_ISA_IV); 788 c->options = MIPS_CPU_TLB | MIPS_CPU_4K_CACHE | MIPS_CPU_4KEX | 789 MIPS_CPU_FPU | MIPS_CPU_32FPR | 790 MIPS_CPU_COUNTER | MIPS_CPU_WATCH | 791 MIPS_CPU_LLSC; 792 c->tlbsize = 64; 793 break; 794 case PRID_IMP_R12000: 795 c->cputype = CPU_R12000; 796 __cpu_name[cpu] = "R12000"; 797 set_isa(c, MIPS_CPU_ISA_IV); 798 c->options = MIPS_CPU_TLB | MIPS_CPU_4K_CACHE | MIPS_CPU_4KEX | 799 MIPS_CPU_FPU | MIPS_CPU_32FPR | 800 MIPS_CPU_COUNTER | MIPS_CPU_WATCH | 801 MIPS_CPU_LLSC; 802 c->tlbsize = 64; 803 break; 804 case PRID_IMP_R14000: 805 c->cputype = CPU_R14000; 806 __cpu_name[cpu] = "R14000"; 807 set_isa(c, MIPS_CPU_ISA_IV); 808 c->options = MIPS_CPU_TLB | MIPS_CPU_4K_CACHE | MIPS_CPU_4KEX | 809 MIPS_CPU_FPU | MIPS_CPU_32FPR | 810 MIPS_CPU_COUNTER | MIPS_CPU_WATCH | 811 MIPS_CPU_LLSC; 812 c->tlbsize = 64; 813 break; 814 case PRID_IMP_LOONGSON_64: /* Loongson-2/3 */ 815 switch (c->processor_id & PRID_REV_MASK) { 816 case PRID_REV_LOONGSON2E: 817 c->cputype = CPU_LOONGSON2; 818 __cpu_name[cpu] = "ICT Loongson-2"; 819 set_elf_platform(cpu, "loongson2e"); 820 set_isa(c, MIPS_CPU_ISA_III); 821 break; 822 case PRID_REV_LOONGSON2F: 823 c->cputype = CPU_LOONGSON2; 824 __cpu_name[cpu] = "ICT Loongson-2"; 825 set_elf_platform(cpu, "loongson2f"); 826 set_isa(c, MIPS_CPU_ISA_III); 827 break; 828 case PRID_REV_LOONGSON3A: 829 c->cputype = CPU_LOONGSON3; 830 __cpu_name[cpu] = "ICT Loongson-3"; 831 set_elf_platform(cpu, "loongson3a"); 832 set_isa(c, MIPS_CPU_ISA_M64R1); 833 break; 834 case PRID_REV_LOONGSON3B_R1: 835 case PRID_REV_LOONGSON3B_R2: 836 c->cputype = CPU_LOONGSON3; 837 __cpu_name[cpu] = "ICT Loongson-3"; 838 set_elf_platform(cpu, "loongson3b"); 839 set_isa(c, MIPS_CPU_ISA_M64R1); 840 break; 841 } 842 843 c->options = R4K_OPTS | 844 MIPS_CPU_FPU | MIPS_CPU_LLSC | 845 MIPS_CPU_32FPR; 846 c->tlbsize = 64; 847 c->writecombine = _CACHE_UNCACHED_ACCELERATED; 848 break; 849 case PRID_IMP_LOONGSON_32: /* Loongson-1 */ 850 decode_configs(c); 851 852 c->cputype = CPU_LOONGSON1; 853 854 switch (c->processor_id & PRID_REV_MASK) { 855 case PRID_REV_LOONGSON1B: 856 __cpu_name[cpu] = "Loongson 1B"; 857 break; 858 } 859 860 break; 861 } 862 } 863 864 static inline void cpu_probe_mips(struct cpuinfo_mips *c, unsigned int cpu) 865 { 866 c->writecombine = _CACHE_UNCACHED_ACCELERATED; 867 switch (c->processor_id & PRID_IMP_MASK) { 868 case PRID_IMP_4KC: 869 c->cputype = CPU_4KC; 870 c->writecombine = _CACHE_UNCACHED; 871 __cpu_name[cpu] = "MIPS 4Kc"; 872 break; 873 case PRID_IMP_4KEC: 874 case PRID_IMP_4KECR2: 875 c->cputype = CPU_4KEC; 876 c->writecombine = _CACHE_UNCACHED; 877 __cpu_name[cpu] = "MIPS 4KEc"; 878 break; 879 case PRID_IMP_4KSC: 880 case PRID_IMP_4KSD: 881 c->cputype = CPU_4KSC; 882 c->writecombine = _CACHE_UNCACHED; 883 __cpu_name[cpu] = "MIPS 4KSc"; 884 break; 885 case PRID_IMP_5KC: 886 c->cputype = CPU_5KC; 887 c->writecombine = _CACHE_UNCACHED; 888 __cpu_name[cpu] = "MIPS 5Kc"; 889 break; 890 case PRID_IMP_5KE: 891 c->cputype = CPU_5KE; 892 c->writecombine = _CACHE_UNCACHED; 893 __cpu_name[cpu] = "MIPS 5KE"; 894 break; 895 case PRID_IMP_20KC: 896 c->cputype = CPU_20KC; 897 c->writecombine = _CACHE_UNCACHED; 898 __cpu_name[cpu] = "MIPS 20Kc"; 899 break; 900 case PRID_IMP_24K: 901 c->cputype = CPU_24K; 902 c->writecombine = _CACHE_UNCACHED; 903 __cpu_name[cpu] = "MIPS 24Kc"; 904 break; 905 case PRID_IMP_24KE: 906 c->cputype = CPU_24K; 907 c->writecombine = _CACHE_UNCACHED; 908 __cpu_name[cpu] = "MIPS 24KEc"; 909 break; 910 case PRID_IMP_25KF: 911 c->cputype = CPU_25KF; 912 c->writecombine = _CACHE_UNCACHED; 913 __cpu_name[cpu] = "MIPS 25Kc"; 914 break; 915 case PRID_IMP_34K: 916 c->cputype = CPU_34K; 917 c->writecombine = _CACHE_UNCACHED; 918 __cpu_name[cpu] = "MIPS 34Kc"; 919 break; 920 case PRID_IMP_74K: 921 c->cputype = CPU_74K; 922 c->writecombine = _CACHE_UNCACHED; 923 __cpu_name[cpu] = "MIPS 74Kc"; 924 break; 925 case PRID_IMP_M14KC: 926 c->cputype = CPU_M14KC; 927 c->writecombine = _CACHE_UNCACHED; 928 __cpu_name[cpu] = "MIPS M14Kc"; 929 break; 930 case PRID_IMP_M14KEC: 931 c->cputype = CPU_M14KEC; 932 c->writecombine = _CACHE_UNCACHED; 933 __cpu_name[cpu] = "MIPS M14KEc"; 934 break; 935 case PRID_IMP_1004K: 936 c->cputype = CPU_1004K; 937 c->writecombine = _CACHE_UNCACHED; 938 __cpu_name[cpu] = "MIPS 1004Kc"; 939 break; 940 case PRID_IMP_1074K: 941 c->cputype = CPU_1074K; 942 c->writecombine = _CACHE_UNCACHED; 943 __cpu_name[cpu] = "MIPS 1074Kc"; 944 break; 945 case PRID_IMP_INTERAPTIV_UP: 946 c->cputype = CPU_INTERAPTIV; 947 __cpu_name[cpu] = "MIPS interAptiv"; 948 break; 949 case PRID_IMP_INTERAPTIV_MP: 950 c->cputype = CPU_INTERAPTIV; 951 __cpu_name[cpu] = "MIPS interAptiv (multi)"; 952 break; 953 case PRID_IMP_PROAPTIV_UP: 954 c->cputype = CPU_PROAPTIV; 955 __cpu_name[cpu] = "MIPS proAptiv"; 956 break; 957 case PRID_IMP_PROAPTIV_MP: 958 c->cputype = CPU_PROAPTIV; 959 __cpu_name[cpu] = "MIPS proAptiv (multi)"; 960 break; 961 case PRID_IMP_P5600: 962 c->cputype = CPU_P5600; 963 __cpu_name[cpu] = "MIPS P5600"; 964 break; 965 case PRID_IMP_M5150: 966 c->cputype = CPU_M5150; 967 __cpu_name[cpu] = "MIPS M5150"; 968 break; 969 } 970 971 decode_configs(c); 972 973 spram_config(); 974 } 975 976 static inline void cpu_probe_alchemy(struct cpuinfo_mips *c, unsigned int cpu) 977 { 978 decode_configs(c); 979 switch (c->processor_id & PRID_IMP_MASK) { 980 case PRID_IMP_AU1_REV1: 981 case PRID_IMP_AU1_REV2: 982 c->cputype = CPU_ALCHEMY; 983 switch ((c->processor_id >> 24) & 0xff) { 984 case 0: 985 __cpu_name[cpu] = "Au1000"; 986 break; 987 case 1: 988 __cpu_name[cpu] = "Au1500"; 989 break; 990 case 2: 991 __cpu_name[cpu] = "Au1100"; 992 break; 993 case 3: 994 __cpu_name[cpu] = "Au1550"; 995 break; 996 case 4: 997 __cpu_name[cpu] = "Au1200"; 998 if ((c->processor_id & PRID_REV_MASK) == 2) 999 __cpu_name[cpu] = "Au1250"; 1000 break; 1001 case 5: 1002 __cpu_name[cpu] = "Au1210"; 1003 break; 1004 default: 1005 __cpu_name[cpu] = "Au1xxx"; 1006 break; 1007 } 1008 break; 1009 } 1010 } 1011 1012 static inline void cpu_probe_sibyte(struct cpuinfo_mips *c, unsigned int cpu) 1013 { 1014 decode_configs(c); 1015 1016 c->writecombine = _CACHE_UNCACHED_ACCELERATED; 1017 switch (c->processor_id & PRID_IMP_MASK) { 1018 case PRID_IMP_SB1: 1019 c->cputype = CPU_SB1; 1020 __cpu_name[cpu] = "SiByte SB1"; 1021 /* FPU in pass1 is known to have issues. */ 1022 if ((c->processor_id & PRID_REV_MASK) < 0x02) 1023 c->options &= ~(MIPS_CPU_FPU | MIPS_CPU_32FPR); 1024 break; 1025 case PRID_IMP_SB1A: 1026 c->cputype = CPU_SB1A; 1027 __cpu_name[cpu] = "SiByte SB1A"; 1028 break; 1029 } 1030 } 1031 1032 static inline void cpu_probe_sandcraft(struct cpuinfo_mips *c, unsigned int cpu) 1033 { 1034 decode_configs(c); 1035 switch (c->processor_id & PRID_IMP_MASK) { 1036 case PRID_IMP_SR71000: 1037 c->cputype = CPU_SR71000; 1038 __cpu_name[cpu] = "Sandcraft SR71000"; 1039 c->scache.ways = 8; 1040 c->tlbsize = 64; 1041 break; 1042 } 1043 } 1044 1045 static inline void cpu_probe_nxp(struct cpuinfo_mips *c, unsigned int cpu) 1046 { 1047 decode_configs(c); 1048 switch (c->processor_id & PRID_IMP_MASK) { 1049 case PRID_IMP_PR4450: 1050 c->cputype = CPU_PR4450; 1051 __cpu_name[cpu] = "Philips PR4450"; 1052 set_isa(c, MIPS_CPU_ISA_M32R1); 1053 break; 1054 } 1055 } 1056 1057 static inline void cpu_probe_broadcom(struct cpuinfo_mips *c, unsigned int cpu) 1058 { 1059 decode_configs(c); 1060 switch (c->processor_id & PRID_IMP_MASK) { 1061 case PRID_IMP_BMIPS32_REV4: 1062 case PRID_IMP_BMIPS32_REV8: 1063 c->cputype = CPU_BMIPS32; 1064 __cpu_name[cpu] = "Broadcom BMIPS32"; 1065 set_elf_platform(cpu, "bmips32"); 1066 break; 1067 case PRID_IMP_BMIPS3300: 1068 case PRID_IMP_BMIPS3300_ALT: 1069 case PRID_IMP_BMIPS3300_BUG: 1070 c->cputype = CPU_BMIPS3300; 1071 __cpu_name[cpu] = "Broadcom BMIPS3300"; 1072 set_elf_platform(cpu, "bmips3300"); 1073 break; 1074 case PRID_IMP_BMIPS43XX: { 1075 int rev = c->processor_id & PRID_REV_MASK; 1076 1077 if (rev >= PRID_REV_BMIPS4380_LO && 1078 rev <= PRID_REV_BMIPS4380_HI) { 1079 c->cputype = CPU_BMIPS4380; 1080 __cpu_name[cpu] = "Broadcom BMIPS4380"; 1081 set_elf_platform(cpu, "bmips4380"); 1082 } else { 1083 c->cputype = CPU_BMIPS4350; 1084 __cpu_name[cpu] = "Broadcom BMIPS4350"; 1085 set_elf_platform(cpu, "bmips4350"); 1086 } 1087 break; 1088 } 1089 case PRID_IMP_BMIPS5000: 1090 case PRID_IMP_BMIPS5200: 1091 c->cputype = CPU_BMIPS5000; 1092 __cpu_name[cpu] = "Broadcom BMIPS5000"; 1093 set_elf_platform(cpu, "bmips5000"); 1094 c->options |= MIPS_CPU_ULRI; 1095 break; 1096 } 1097 } 1098 1099 static inline void cpu_probe_cavium(struct cpuinfo_mips *c, unsigned int cpu) 1100 { 1101 decode_configs(c); 1102 switch (c->processor_id & PRID_IMP_MASK) { 1103 case PRID_IMP_CAVIUM_CN38XX: 1104 case PRID_IMP_CAVIUM_CN31XX: 1105 case PRID_IMP_CAVIUM_CN30XX: 1106 c->cputype = CPU_CAVIUM_OCTEON; 1107 __cpu_name[cpu] = "Cavium Octeon"; 1108 goto platform; 1109 case PRID_IMP_CAVIUM_CN58XX: 1110 case PRID_IMP_CAVIUM_CN56XX: 1111 case PRID_IMP_CAVIUM_CN50XX: 1112 case PRID_IMP_CAVIUM_CN52XX: 1113 c->cputype = CPU_CAVIUM_OCTEON_PLUS; 1114 __cpu_name[cpu] = "Cavium Octeon+"; 1115 platform: 1116 set_elf_platform(cpu, "octeon"); 1117 break; 1118 case PRID_IMP_CAVIUM_CN61XX: 1119 case PRID_IMP_CAVIUM_CN63XX: 1120 case PRID_IMP_CAVIUM_CN66XX: 1121 case PRID_IMP_CAVIUM_CN68XX: 1122 case PRID_IMP_CAVIUM_CNF71XX: 1123 c->cputype = CPU_CAVIUM_OCTEON2; 1124 __cpu_name[cpu] = "Cavium Octeon II"; 1125 set_elf_platform(cpu, "octeon2"); 1126 break; 1127 case PRID_IMP_CAVIUM_CN70XX: 1128 case PRID_IMP_CAVIUM_CN78XX: 1129 c->cputype = CPU_CAVIUM_OCTEON3; 1130 __cpu_name[cpu] = "Cavium Octeon III"; 1131 set_elf_platform(cpu, "octeon3"); 1132 break; 1133 default: 1134 printk(KERN_INFO "Unknown Octeon chip!\n"); 1135 c->cputype = CPU_UNKNOWN; 1136 break; 1137 } 1138 } 1139 1140 static inline void cpu_probe_ingenic(struct cpuinfo_mips *c, unsigned int cpu) 1141 { 1142 decode_configs(c); 1143 /* JZRISC does not implement the CP0 counter. */ 1144 c->options &= ~MIPS_CPU_COUNTER; 1145 BUG_ON(!__builtin_constant_p(cpu_has_counter) || cpu_has_counter); 1146 switch (c->processor_id & PRID_IMP_MASK) { 1147 case PRID_IMP_JZRISC: 1148 c->cputype = CPU_JZRISC; 1149 c->writecombine = _CACHE_UNCACHED_ACCELERATED; 1150 __cpu_name[cpu] = "Ingenic JZRISC"; 1151 break; 1152 default: 1153 panic("Unknown Ingenic Processor ID!"); 1154 break; 1155 } 1156 } 1157 1158 static inline void cpu_probe_netlogic(struct cpuinfo_mips *c, int cpu) 1159 { 1160 decode_configs(c); 1161 1162 if ((c->processor_id & PRID_IMP_MASK) == PRID_IMP_NETLOGIC_AU13XX) { 1163 c->cputype = CPU_ALCHEMY; 1164 __cpu_name[cpu] = "Au1300"; 1165 /* following stuff is not for Alchemy */ 1166 return; 1167 } 1168 1169 c->options = (MIPS_CPU_TLB | 1170 MIPS_CPU_4KEX | 1171 MIPS_CPU_COUNTER | 1172 MIPS_CPU_DIVEC | 1173 MIPS_CPU_WATCH | 1174 MIPS_CPU_EJTAG | 1175 MIPS_CPU_LLSC); 1176 1177 switch (c->processor_id & PRID_IMP_MASK) { 1178 case PRID_IMP_NETLOGIC_XLP2XX: 1179 case PRID_IMP_NETLOGIC_XLP9XX: 1180 case PRID_IMP_NETLOGIC_XLP5XX: 1181 c->cputype = CPU_XLP; 1182 __cpu_name[cpu] = "Broadcom XLPII"; 1183 break; 1184 1185 case PRID_IMP_NETLOGIC_XLP8XX: 1186 case PRID_IMP_NETLOGIC_XLP3XX: 1187 c->cputype = CPU_XLP; 1188 __cpu_name[cpu] = "Netlogic XLP"; 1189 break; 1190 1191 case PRID_IMP_NETLOGIC_XLR732: 1192 case PRID_IMP_NETLOGIC_XLR716: 1193 case PRID_IMP_NETLOGIC_XLR532: 1194 case PRID_IMP_NETLOGIC_XLR308: 1195 case PRID_IMP_NETLOGIC_XLR532C: 1196 case PRID_IMP_NETLOGIC_XLR516C: 1197 case PRID_IMP_NETLOGIC_XLR508C: 1198 case PRID_IMP_NETLOGIC_XLR308C: 1199 c->cputype = CPU_XLR; 1200 __cpu_name[cpu] = "Netlogic XLR"; 1201 break; 1202 1203 case PRID_IMP_NETLOGIC_XLS608: 1204 case PRID_IMP_NETLOGIC_XLS408: 1205 case PRID_IMP_NETLOGIC_XLS404: 1206 case PRID_IMP_NETLOGIC_XLS208: 1207 case PRID_IMP_NETLOGIC_XLS204: 1208 case PRID_IMP_NETLOGIC_XLS108: 1209 case PRID_IMP_NETLOGIC_XLS104: 1210 case PRID_IMP_NETLOGIC_XLS616B: 1211 case PRID_IMP_NETLOGIC_XLS608B: 1212 case PRID_IMP_NETLOGIC_XLS416B: 1213 case PRID_IMP_NETLOGIC_XLS412B: 1214 case PRID_IMP_NETLOGIC_XLS408B: 1215 case PRID_IMP_NETLOGIC_XLS404B: 1216 c->cputype = CPU_XLR; 1217 __cpu_name[cpu] = "Netlogic XLS"; 1218 break; 1219 1220 default: 1221 pr_info("Unknown Netlogic chip id [%02x]!\n", 1222 c->processor_id); 1223 c->cputype = CPU_XLR; 1224 break; 1225 } 1226 1227 if (c->cputype == CPU_XLP) { 1228 set_isa(c, MIPS_CPU_ISA_M64R2); 1229 c->options |= (MIPS_CPU_FPU | MIPS_CPU_ULRI | MIPS_CPU_MCHECK); 1230 /* This will be updated again after all threads are woken up */ 1231 c->tlbsize = ((read_c0_config6() >> 16) & 0xffff) + 1; 1232 } else { 1233 set_isa(c, MIPS_CPU_ISA_M64R1); 1234 c->tlbsize = ((read_c0_config1() >> 25) & 0x3f) + 1; 1235 } 1236 c->kscratch_mask = 0xf; 1237 } 1238 1239 #ifdef CONFIG_64BIT 1240 /* For use by uaccess.h */ 1241 u64 __ua_limit; 1242 EXPORT_SYMBOL(__ua_limit); 1243 #endif 1244 1245 const char *__cpu_name[NR_CPUS]; 1246 const char *__elf_platform; 1247 1248 void cpu_probe(void) 1249 { 1250 struct cpuinfo_mips *c = ¤t_cpu_data; 1251 unsigned int cpu = smp_processor_id(); 1252 1253 c->processor_id = PRID_IMP_UNKNOWN; 1254 c->fpu_id = FPIR_IMP_NONE; 1255 c->cputype = CPU_UNKNOWN; 1256 c->writecombine = _CACHE_UNCACHED; 1257 1258 c->processor_id = read_c0_prid(); 1259 switch (c->processor_id & PRID_COMP_MASK) { 1260 case PRID_COMP_LEGACY: 1261 cpu_probe_legacy(c, cpu); 1262 break; 1263 case PRID_COMP_MIPS: 1264 cpu_probe_mips(c, cpu); 1265 break; 1266 case PRID_COMP_ALCHEMY: 1267 cpu_probe_alchemy(c, cpu); 1268 break; 1269 case PRID_COMP_SIBYTE: 1270 cpu_probe_sibyte(c, cpu); 1271 break; 1272 case PRID_COMP_BROADCOM: 1273 cpu_probe_broadcom(c, cpu); 1274 break; 1275 case PRID_COMP_SANDCRAFT: 1276 cpu_probe_sandcraft(c, cpu); 1277 break; 1278 case PRID_COMP_NXP: 1279 cpu_probe_nxp(c, cpu); 1280 break; 1281 case PRID_COMP_CAVIUM: 1282 cpu_probe_cavium(c, cpu); 1283 break; 1284 case PRID_COMP_INGENIC: 1285 cpu_probe_ingenic(c, cpu); 1286 break; 1287 case PRID_COMP_NETLOGIC: 1288 cpu_probe_netlogic(c, cpu); 1289 break; 1290 } 1291 1292 BUG_ON(!__cpu_name[cpu]); 1293 BUG_ON(c->cputype == CPU_UNKNOWN); 1294 1295 /* 1296 * Platform code can force the cpu type to optimize code 1297 * generation. In that case be sure the cpu type is correctly 1298 * manually setup otherwise it could trigger some nasty bugs. 1299 */ 1300 BUG_ON(current_cpu_type() != c->cputype); 1301 1302 if (mips_fpu_disabled) 1303 c->options &= ~MIPS_CPU_FPU; 1304 1305 if (mips_dsp_disabled) 1306 c->ases &= ~(MIPS_ASE_DSP | MIPS_ASE_DSP2P); 1307 1308 if (mips_htw_disabled) { 1309 c->options &= ~MIPS_CPU_HTW; 1310 write_c0_pwctl(read_c0_pwctl() & 1311 ~(1 << MIPS_PWCTL_PWEN_SHIFT)); 1312 } 1313 1314 if (c->options & MIPS_CPU_FPU) { 1315 c->fpu_id = cpu_get_fpu_id(); 1316 1317 if (c->isa_level & (MIPS_CPU_ISA_M32R1 | MIPS_CPU_ISA_M32R2 | 1318 MIPS_CPU_ISA_M64R1 | MIPS_CPU_ISA_M64R2)) { 1319 if (c->fpu_id & MIPS_FPIR_3D) 1320 c->ases |= MIPS_ASE_MIPS3D; 1321 if (c->fpu_id & MIPS_FPIR_FREP) 1322 c->options |= MIPS_CPU_FRE; 1323 } 1324 } 1325 1326 if (cpu_has_mips_r2) { 1327 c->srsets = ((read_c0_srsctl() >> 26) & 0x0f) + 1; 1328 /* R2 has Performance Counter Interrupt indicator */ 1329 c->options |= MIPS_CPU_PCI; 1330 } 1331 else 1332 c->srsets = 1; 1333 1334 if (cpu_has_msa) { 1335 c->msa_id = cpu_get_msa_id(); 1336 WARN(c->msa_id & MSA_IR_WRPF, 1337 "Vector register partitioning unimplemented!"); 1338 } 1339 1340 cpu_probe_vmbits(c); 1341 1342 #ifdef CONFIG_64BIT 1343 if (cpu == 0) 1344 __ua_limit = ~((1ull << cpu_vmbits) - 1); 1345 #endif 1346 } 1347 1348 void cpu_report(void) 1349 { 1350 struct cpuinfo_mips *c = ¤t_cpu_data; 1351 1352 pr_info("CPU%d revision is: %08x (%s)\n", 1353 smp_processor_id(), c->processor_id, cpu_name_string()); 1354 if (c->options & MIPS_CPU_FPU) 1355 printk(KERN_INFO "FPU revision is: %08x\n", c->fpu_id); 1356 if (cpu_has_msa) 1357 pr_info("MSA revision is: %08x\n", c->msa_id); 1358 } 1359