1 /* 2 * Processor capabilities determination functions. 3 * 4 * Copyright (C) xxxx the Anonymous 5 * Copyright (C) 1994 - 2006 Ralf Baechle 6 * Copyright (C) 2003, 2004 Maciej W. Rozycki 7 * Copyright (C) 2001, 2004, 2011, 2012 MIPS Technologies, Inc. 8 * 9 * This program is free software; you can redistribute it and/or 10 * modify it under the terms of the GNU General Public License 11 * as published by the Free Software Foundation; either version 12 * 2 of the License, or (at your option) any later version. 13 */ 14 #include <linux/init.h> 15 #include <linux/kernel.h> 16 #include <linux/ptrace.h> 17 #include <linux/smp.h> 18 #include <linux/stddef.h> 19 #include <linux/export.h> 20 21 #include <asm/bugs.h> 22 #include <asm/cpu.h> 23 #include <asm/fpu.h> 24 #include <asm/mipsregs.h> 25 #include <asm/watch.h> 26 #include <asm/elf.h> 27 #include <asm/spram.h> 28 #include <asm/uaccess.h> 29 30 /* 31 * Not all of the MIPS CPUs have the "wait" instruction available. Moreover, 32 * the implementation of the "wait" feature differs between CPU families. This 33 * points to the function that implements CPU specific wait. 34 * The wait instruction stops the pipeline and reduces the power consumption of 35 * the CPU very much. 36 */ 37 void (*cpu_wait)(void); 38 EXPORT_SYMBOL(cpu_wait); 39 40 static void r3081_wait(void) 41 { 42 unsigned long cfg = read_c0_conf(); 43 write_c0_conf(cfg | R30XX_CONF_HALT); 44 } 45 46 static void r39xx_wait(void) 47 { 48 local_irq_disable(); 49 if (!need_resched()) 50 write_c0_conf(read_c0_conf() | TX39_CONF_HALT); 51 local_irq_enable(); 52 } 53 54 extern void r4k_wait(void); 55 56 /* 57 * This variant is preferable as it allows testing need_resched and going to 58 * sleep depending on the outcome atomically. Unfortunately the "It is 59 * implementation-dependent whether the pipeline restarts when a non-enabled 60 * interrupt is requested" restriction in the MIPS32/MIPS64 architecture makes 61 * using this version a gamble. 62 */ 63 void r4k_wait_irqoff(void) 64 { 65 local_irq_disable(); 66 if (!need_resched()) 67 __asm__(" .set push \n" 68 " .set mips3 \n" 69 " wait \n" 70 " .set pop \n"); 71 local_irq_enable(); 72 __asm__(" .globl __pastwait \n" 73 "__pastwait: \n"); 74 } 75 76 /* 77 * The RM7000 variant has to handle erratum 38. The workaround is to not 78 * have any pending stores when the WAIT instruction is executed. 79 */ 80 static void rm7k_wait_irqoff(void) 81 { 82 local_irq_disable(); 83 if (!need_resched()) 84 __asm__( 85 " .set push \n" 86 " .set mips3 \n" 87 " .set noat \n" 88 " mfc0 $1, $12 \n" 89 " sync \n" 90 " mtc0 $1, $12 # stalls until W stage \n" 91 " wait \n" 92 " mtc0 $1, $12 # stalls until W stage \n" 93 " .set pop \n"); 94 local_irq_enable(); 95 } 96 97 /* 98 * The Au1xxx wait is available only if using 32khz counter or 99 * external timer source, but specifically not CP0 Counter. 100 * alchemy/common/time.c may override cpu_wait! 101 */ 102 static void au1k_wait(void) 103 { 104 __asm__(" .set mips3 \n" 105 " cache 0x14, 0(%0) \n" 106 " cache 0x14, 32(%0) \n" 107 " sync \n" 108 " nop \n" 109 " wait \n" 110 " nop \n" 111 " nop \n" 112 " nop \n" 113 " nop \n" 114 " .set mips0 \n" 115 : : "r" (au1k_wait)); 116 } 117 118 static int __initdata nowait; 119 120 static int __init wait_disable(char *s) 121 { 122 nowait = 1; 123 124 return 1; 125 } 126 127 __setup("nowait", wait_disable); 128 129 static int __cpuinitdata mips_fpu_disabled; 130 131 static int __init fpu_disable(char *s) 132 { 133 cpu_data[0].options &= ~MIPS_CPU_FPU; 134 mips_fpu_disabled = 1; 135 136 return 1; 137 } 138 139 __setup("nofpu", fpu_disable); 140 141 int __cpuinitdata mips_dsp_disabled; 142 143 static int __init dsp_disable(char *s) 144 { 145 cpu_data[0].ases &= ~(MIPS_ASE_DSP | MIPS_ASE_DSP2P); 146 mips_dsp_disabled = 1; 147 148 return 1; 149 } 150 151 __setup("nodsp", dsp_disable); 152 153 void __init check_wait(void) 154 { 155 struct cpuinfo_mips *c = ¤t_cpu_data; 156 157 if (nowait) { 158 printk("Wait instruction disabled.\n"); 159 return; 160 } 161 162 switch (c->cputype) { 163 case CPU_R3081: 164 case CPU_R3081E: 165 cpu_wait = r3081_wait; 166 break; 167 case CPU_TX3927: 168 cpu_wait = r39xx_wait; 169 break; 170 case CPU_R4200: 171 /* case CPU_R4300: */ 172 case CPU_R4600: 173 case CPU_R4640: 174 case CPU_R4650: 175 case CPU_R4700: 176 case CPU_R5000: 177 case CPU_R5500: 178 case CPU_NEVADA: 179 case CPU_4KC: 180 case CPU_4KEC: 181 case CPU_4KSC: 182 case CPU_5KC: 183 case CPU_25KF: 184 case CPU_PR4450: 185 case CPU_BMIPS3300: 186 case CPU_BMIPS4350: 187 case CPU_BMIPS4380: 188 case CPU_BMIPS5000: 189 case CPU_CAVIUM_OCTEON: 190 case CPU_CAVIUM_OCTEON_PLUS: 191 case CPU_CAVIUM_OCTEON2: 192 case CPU_JZRISC: 193 case CPU_LOONGSON1: 194 case CPU_XLR: 195 case CPU_XLP: 196 cpu_wait = r4k_wait; 197 break; 198 199 case CPU_RM7000: 200 cpu_wait = rm7k_wait_irqoff; 201 break; 202 203 case CPU_M14KC: 204 case CPU_M14KEC: 205 case CPU_24K: 206 case CPU_34K: 207 case CPU_1004K: 208 cpu_wait = r4k_wait; 209 if (read_c0_config7() & MIPS_CONF7_WII) 210 cpu_wait = r4k_wait_irqoff; 211 break; 212 213 case CPU_74K: 214 cpu_wait = r4k_wait; 215 if ((c->processor_id & 0xff) >= PRID_REV_ENCODE_332(2, 1, 0)) 216 cpu_wait = r4k_wait_irqoff; 217 break; 218 219 case CPU_TX49XX: 220 cpu_wait = r4k_wait_irqoff; 221 break; 222 case CPU_ALCHEMY: 223 cpu_wait = au1k_wait; 224 break; 225 case CPU_20KC: 226 /* 227 * WAIT on Rev1.0 has E1, E2, E3 and E16. 228 * WAIT on Rev2.0 and Rev3.0 has E16. 229 * Rev3.1 WAIT is nop, why bother 230 */ 231 if ((c->processor_id & 0xff) <= 0x64) 232 break; 233 234 /* 235 * Another rev is incremeting c0_count at a reduced clock 236 * rate while in WAIT mode. So we basically have the choice 237 * between using the cp0 timer as clocksource or avoiding 238 * the WAIT instruction. Until more details are known, 239 * disable the use of WAIT for 20Kc entirely. 240 cpu_wait = r4k_wait; 241 */ 242 break; 243 case CPU_RM9000: 244 if ((c->processor_id & 0x00ff) >= 0x40) 245 cpu_wait = r4k_wait; 246 break; 247 default: 248 break; 249 } 250 } 251 252 static inline void check_errata(void) 253 { 254 struct cpuinfo_mips *c = ¤t_cpu_data; 255 256 switch (c->cputype) { 257 case CPU_34K: 258 /* 259 * Erratum "RPS May Cause Incorrect Instruction Execution" 260 * This code only handles VPE0, any SMP/SMTC/RTOS code 261 * making use of VPE1 will be responsable for that VPE. 262 */ 263 if ((c->processor_id & PRID_REV_MASK) <= PRID_REV_34K_V1_0_2) 264 write_c0_config7(read_c0_config7() | MIPS_CONF7_RPS); 265 break; 266 default: 267 break; 268 } 269 } 270 271 void __init check_bugs32(void) 272 { 273 check_errata(); 274 } 275 276 /* 277 * Probe whether cpu has config register by trying to play with 278 * alternate cache bit and see whether it matters. 279 * It's used by cpu_probe to distinguish between R3000A and R3081. 280 */ 281 static inline int cpu_has_confreg(void) 282 { 283 #ifdef CONFIG_CPU_R3000 284 extern unsigned long r3k_cache_size(unsigned long); 285 unsigned long size1, size2; 286 unsigned long cfg = read_c0_conf(); 287 288 size1 = r3k_cache_size(ST0_ISC); 289 write_c0_conf(cfg ^ R30XX_CONF_AC); 290 size2 = r3k_cache_size(ST0_ISC); 291 write_c0_conf(cfg); 292 return size1 != size2; 293 #else 294 return 0; 295 #endif 296 } 297 298 static inline void set_elf_platform(int cpu, const char *plat) 299 { 300 if (cpu == 0) 301 __elf_platform = plat; 302 } 303 304 /* 305 * Get the FPU Implementation/Revision. 306 */ 307 static inline unsigned long cpu_get_fpu_id(void) 308 { 309 unsigned long tmp, fpu_id; 310 311 tmp = read_c0_status(); 312 __enable_fpu(); 313 fpu_id = read_32bit_cp1_register(CP1_REVISION); 314 write_c0_status(tmp); 315 return fpu_id; 316 } 317 318 /* 319 * Check the CPU has an FPU the official way. 320 */ 321 static inline int __cpu_has_fpu(void) 322 { 323 return ((cpu_get_fpu_id() & 0xff00) != FPIR_IMP_NONE); 324 } 325 326 static inline void cpu_probe_vmbits(struct cpuinfo_mips *c) 327 { 328 #ifdef __NEED_VMBITS_PROBE 329 write_c0_entryhi(0x3fffffffffffe000ULL); 330 back_to_back_c0_hazard(); 331 c->vmbits = fls64(read_c0_entryhi() & 0x3fffffffffffe000ULL); 332 #endif 333 } 334 335 static void __cpuinit set_isa(struct cpuinfo_mips *c, unsigned int isa) 336 { 337 switch (isa) { 338 case MIPS_CPU_ISA_M64R2: 339 c->isa_level |= MIPS_CPU_ISA_M32R2 | MIPS_CPU_ISA_M64R2; 340 case MIPS_CPU_ISA_M64R1: 341 c->isa_level |= MIPS_CPU_ISA_M32R1 | MIPS_CPU_ISA_M64R1; 342 case MIPS_CPU_ISA_V: 343 c->isa_level |= MIPS_CPU_ISA_V; 344 case MIPS_CPU_ISA_IV: 345 c->isa_level |= MIPS_CPU_ISA_IV; 346 case MIPS_CPU_ISA_III: 347 c->isa_level |= MIPS_CPU_ISA_I | MIPS_CPU_ISA_II | 348 MIPS_CPU_ISA_III; 349 break; 350 351 case MIPS_CPU_ISA_M32R2: 352 c->isa_level |= MIPS_CPU_ISA_M32R2; 353 case MIPS_CPU_ISA_M32R1: 354 c->isa_level |= MIPS_CPU_ISA_M32R1; 355 case MIPS_CPU_ISA_II: 356 c->isa_level |= MIPS_CPU_ISA_II; 357 case MIPS_CPU_ISA_I: 358 c->isa_level |= MIPS_CPU_ISA_I; 359 break; 360 } 361 } 362 363 static char unknown_isa[] __cpuinitdata = KERN_ERR \ 364 "Unsupported ISA type, c0.config0: %d."; 365 366 static inline unsigned int decode_config0(struct cpuinfo_mips *c) 367 { 368 unsigned int config0; 369 int isa; 370 371 config0 = read_c0_config(); 372 373 if (((config0 & MIPS_CONF_MT) >> 7) == 1) 374 c->options |= MIPS_CPU_TLB; 375 isa = (config0 & MIPS_CONF_AT) >> 13; 376 switch (isa) { 377 case 0: 378 switch ((config0 & MIPS_CONF_AR) >> 10) { 379 case 0: 380 set_isa(c, MIPS_CPU_ISA_M32R1); 381 break; 382 case 1: 383 set_isa(c, MIPS_CPU_ISA_M32R2); 384 break; 385 default: 386 goto unknown; 387 } 388 break; 389 case 2: 390 switch ((config0 & MIPS_CONF_AR) >> 10) { 391 case 0: 392 set_isa(c, MIPS_CPU_ISA_M64R1); 393 break; 394 case 1: 395 set_isa(c, MIPS_CPU_ISA_M64R2); 396 break; 397 default: 398 goto unknown; 399 } 400 break; 401 default: 402 goto unknown; 403 } 404 405 return config0 & MIPS_CONF_M; 406 407 unknown: 408 panic(unknown_isa, config0); 409 } 410 411 static inline unsigned int decode_config1(struct cpuinfo_mips *c) 412 { 413 unsigned int config1; 414 415 config1 = read_c0_config1(); 416 417 if (config1 & MIPS_CONF1_MD) 418 c->ases |= MIPS_ASE_MDMX; 419 if (config1 & MIPS_CONF1_WR) 420 c->options |= MIPS_CPU_WATCH; 421 if (config1 & MIPS_CONF1_CA) 422 c->ases |= MIPS_ASE_MIPS16; 423 if (config1 & MIPS_CONF1_EP) 424 c->options |= MIPS_CPU_EJTAG; 425 if (config1 & MIPS_CONF1_FP) { 426 c->options |= MIPS_CPU_FPU; 427 c->options |= MIPS_CPU_32FPR; 428 } 429 if (cpu_has_tlb) 430 c->tlbsize = ((config1 & MIPS_CONF1_TLBS) >> 25) + 1; 431 432 return config1 & MIPS_CONF_M; 433 } 434 435 static inline unsigned int decode_config2(struct cpuinfo_mips *c) 436 { 437 unsigned int config2; 438 439 config2 = read_c0_config2(); 440 441 if (config2 & MIPS_CONF2_SL) 442 c->scache.flags &= ~MIPS_CACHE_NOT_PRESENT; 443 444 return config2 & MIPS_CONF_M; 445 } 446 447 static inline unsigned int decode_config3(struct cpuinfo_mips *c) 448 { 449 unsigned int config3; 450 451 config3 = read_c0_config3(); 452 453 if (config3 & MIPS_CONF3_SM) { 454 c->ases |= MIPS_ASE_SMARTMIPS; 455 c->options |= MIPS_CPU_RIXI; 456 } 457 if (config3 & MIPS_CONF3_RXI) 458 c->options |= MIPS_CPU_RIXI; 459 if (config3 & MIPS_CONF3_DSP) 460 c->ases |= MIPS_ASE_DSP; 461 if (config3 & MIPS_CONF3_DSP2P) 462 c->ases |= MIPS_ASE_DSP2P; 463 if (config3 & MIPS_CONF3_VINT) 464 c->options |= MIPS_CPU_VINT; 465 if (config3 & MIPS_CONF3_VEIC) 466 c->options |= MIPS_CPU_VEIC; 467 if (config3 & MIPS_CONF3_MT) 468 c->ases |= MIPS_ASE_MIPSMT; 469 if (config3 & MIPS_CONF3_ULRI) 470 c->options |= MIPS_CPU_ULRI; 471 if (config3 & MIPS_CONF3_ISA) 472 c->options |= MIPS_CPU_MICROMIPS; 473 if (config3 & MIPS_CONF3_VZ) 474 c->ases |= MIPS_ASE_VZ; 475 476 return config3 & MIPS_CONF_M; 477 } 478 479 static inline unsigned int decode_config4(struct cpuinfo_mips *c) 480 { 481 unsigned int config4; 482 483 config4 = read_c0_config4(); 484 485 if ((config4 & MIPS_CONF4_MMUEXTDEF) == MIPS_CONF4_MMUEXTDEF_MMUSIZEEXT 486 && cpu_has_tlb) 487 c->tlbsize += (config4 & MIPS_CONF4_MMUSIZEEXT) * 0x40; 488 489 c->kscratch_mask = (config4 >> 16) & 0xff; 490 491 return config4 & MIPS_CONF_M; 492 } 493 494 static void __cpuinit decode_configs(struct cpuinfo_mips *c) 495 { 496 int ok; 497 498 /* MIPS32 or MIPS64 compliant CPU. */ 499 c->options = MIPS_CPU_4KEX | MIPS_CPU_4K_CACHE | MIPS_CPU_COUNTER | 500 MIPS_CPU_DIVEC | MIPS_CPU_LLSC | MIPS_CPU_MCHECK; 501 502 c->scache.flags = MIPS_CACHE_NOT_PRESENT; 503 504 ok = decode_config0(c); /* Read Config registers. */ 505 BUG_ON(!ok); /* Arch spec violation! */ 506 if (ok) 507 ok = decode_config1(c); 508 if (ok) 509 ok = decode_config2(c); 510 if (ok) 511 ok = decode_config3(c); 512 if (ok) 513 ok = decode_config4(c); 514 515 mips_probe_watch_registers(c); 516 517 if (cpu_has_mips_r2) 518 c->core = read_c0_ebase() & 0x3ff; 519 } 520 521 #define R4K_OPTS (MIPS_CPU_TLB | MIPS_CPU_4KEX | MIPS_CPU_4K_CACHE \ 522 | MIPS_CPU_COUNTER) 523 524 static inline void cpu_probe_legacy(struct cpuinfo_mips *c, unsigned int cpu) 525 { 526 switch (c->processor_id & 0xff00) { 527 case PRID_IMP_R2000: 528 c->cputype = CPU_R2000; 529 __cpu_name[cpu] = "R2000"; 530 set_isa(c, MIPS_CPU_ISA_I); 531 c->options = MIPS_CPU_TLB | MIPS_CPU_3K_CACHE | 532 MIPS_CPU_NOFPUEX; 533 if (__cpu_has_fpu()) 534 c->options |= MIPS_CPU_FPU; 535 c->tlbsize = 64; 536 break; 537 case PRID_IMP_R3000: 538 if ((c->processor_id & 0xff) == PRID_REV_R3000A) { 539 if (cpu_has_confreg()) { 540 c->cputype = CPU_R3081E; 541 __cpu_name[cpu] = "R3081"; 542 } else { 543 c->cputype = CPU_R3000A; 544 __cpu_name[cpu] = "R3000A"; 545 } 546 } else { 547 c->cputype = CPU_R3000; 548 __cpu_name[cpu] = "R3000"; 549 } 550 set_isa(c, MIPS_CPU_ISA_I); 551 c->options = MIPS_CPU_TLB | MIPS_CPU_3K_CACHE | 552 MIPS_CPU_NOFPUEX; 553 if (__cpu_has_fpu()) 554 c->options |= MIPS_CPU_FPU; 555 c->tlbsize = 64; 556 break; 557 case PRID_IMP_R4000: 558 if (read_c0_config() & CONF_SC) { 559 if ((c->processor_id & 0xff) >= PRID_REV_R4400) { 560 c->cputype = CPU_R4400PC; 561 __cpu_name[cpu] = "R4400PC"; 562 } else { 563 c->cputype = CPU_R4000PC; 564 __cpu_name[cpu] = "R4000PC"; 565 } 566 } else { 567 if ((c->processor_id & 0xff) >= PRID_REV_R4400) { 568 c->cputype = CPU_R4400SC; 569 __cpu_name[cpu] = "R4400SC"; 570 } else { 571 c->cputype = CPU_R4000SC; 572 __cpu_name[cpu] = "R4000SC"; 573 } 574 } 575 576 set_isa(c, MIPS_CPU_ISA_III); 577 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR | 578 MIPS_CPU_WATCH | MIPS_CPU_VCE | 579 MIPS_CPU_LLSC; 580 c->tlbsize = 48; 581 break; 582 case PRID_IMP_VR41XX: 583 set_isa(c, MIPS_CPU_ISA_III); 584 c->options = R4K_OPTS; 585 c->tlbsize = 32; 586 switch (c->processor_id & 0xf0) { 587 case PRID_REV_VR4111: 588 c->cputype = CPU_VR4111; 589 __cpu_name[cpu] = "NEC VR4111"; 590 break; 591 case PRID_REV_VR4121: 592 c->cputype = CPU_VR4121; 593 __cpu_name[cpu] = "NEC VR4121"; 594 break; 595 case PRID_REV_VR4122: 596 if ((c->processor_id & 0xf) < 0x3) { 597 c->cputype = CPU_VR4122; 598 __cpu_name[cpu] = "NEC VR4122"; 599 } else { 600 c->cputype = CPU_VR4181A; 601 __cpu_name[cpu] = "NEC VR4181A"; 602 } 603 break; 604 case PRID_REV_VR4130: 605 if ((c->processor_id & 0xf) < 0x4) { 606 c->cputype = CPU_VR4131; 607 __cpu_name[cpu] = "NEC VR4131"; 608 } else { 609 c->cputype = CPU_VR4133; 610 c->options |= MIPS_CPU_LLSC; 611 __cpu_name[cpu] = "NEC VR4133"; 612 } 613 break; 614 default: 615 printk(KERN_INFO "Unexpected CPU of NEC VR4100 series\n"); 616 c->cputype = CPU_VR41XX; 617 __cpu_name[cpu] = "NEC Vr41xx"; 618 break; 619 } 620 break; 621 case PRID_IMP_R4300: 622 c->cputype = CPU_R4300; 623 __cpu_name[cpu] = "R4300"; 624 set_isa(c, MIPS_CPU_ISA_III); 625 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR | 626 MIPS_CPU_LLSC; 627 c->tlbsize = 32; 628 break; 629 case PRID_IMP_R4600: 630 c->cputype = CPU_R4600; 631 __cpu_name[cpu] = "R4600"; 632 set_isa(c, MIPS_CPU_ISA_III); 633 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR | 634 MIPS_CPU_LLSC; 635 c->tlbsize = 48; 636 break; 637 #if 0 638 case PRID_IMP_R4650: 639 /* 640 * This processor doesn't have an MMU, so it's not 641 * "real easy" to run Linux on it. It is left purely 642 * for documentation. Commented out because it shares 643 * it's c0_prid id number with the TX3900. 644 */ 645 c->cputype = CPU_R4650; 646 __cpu_name[cpu] = "R4650"; 647 set_isa(c, MIPS_CPU_ISA_III); 648 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_LLSC; 649 c->tlbsize = 48; 650 break; 651 #endif 652 case PRID_IMP_TX39: 653 set_isa(c, MIPS_CPU_ISA_I); 654 c->options = MIPS_CPU_TLB | MIPS_CPU_TX39_CACHE; 655 656 if ((c->processor_id & 0xf0) == (PRID_REV_TX3927 & 0xf0)) { 657 c->cputype = CPU_TX3927; 658 __cpu_name[cpu] = "TX3927"; 659 c->tlbsize = 64; 660 } else { 661 switch (c->processor_id & 0xff) { 662 case PRID_REV_TX3912: 663 c->cputype = CPU_TX3912; 664 __cpu_name[cpu] = "TX3912"; 665 c->tlbsize = 32; 666 break; 667 case PRID_REV_TX3922: 668 c->cputype = CPU_TX3922; 669 __cpu_name[cpu] = "TX3922"; 670 c->tlbsize = 64; 671 break; 672 } 673 } 674 break; 675 case PRID_IMP_R4700: 676 c->cputype = CPU_R4700; 677 __cpu_name[cpu] = "R4700"; 678 set_isa(c, MIPS_CPU_ISA_III); 679 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR | 680 MIPS_CPU_LLSC; 681 c->tlbsize = 48; 682 break; 683 case PRID_IMP_TX49: 684 c->cputype = CPU_TX49XX; 685 __cpu_name[cpu] = "R49XX"; 686 set_isa(c, MIPS_CPU_ISA_III); 687 c->options = R4K_OPTS | MIPS_CPU_LLSC; 688 if (!(c->processor_id & 0x08)) 689 c->options |= MIPS_CPU_FPU | MIPS_CPU_32FPR; 690 c->tlbsize = 48; 691 break; 692 case PRID_IMP_R5000: 693 c->cputype = CPU_R5000; 694 __cpu_name[cpu] = "R5000"; 695 set_isa(c, MIPS_CPU_ISA_IV); 696 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR | 697 MIPS_CPU_LLSC; 698 c->tlbsize = 48; 699 break; 700 case PRID_IMP_R5432: 701 c->cputype = CPU_R5432; 702 __cpu_name[cpu] = "R5432"; 703 set_isa(c, MIPS_CPU_ISA_IV); 704 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR | 705 MIPS_CPU_WATCH | MIPS_CPU_LLSC; 706 c->tlbsize = 48; 707 break; 708 case PRID_IMP_R5500: 709 c->cputype = CPU_R5500; 710 __cpu_name[cpu] = "R5500"; 711 set_isa(c, MIPS_CPU_ISA_IV); 712 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR | 713 MIPS_CPU_WATCH | MIPS_CPU_LLSC; 714 c->tlbsize = 48; 715 break; 716 case PRID_IMP_NEVADA: 717 c->cputype = CPU_NEVADA; 718 __cpu_name[cpu] = "Nevada"; 719 set_isa(c, MIPS_CPU_ISA_IV); 720 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR | 721 MIPS_CPU_DIVEC | MIPS_CPU_LLSC; 722 c->tlbsize = 48; 723 break; 724 case PRID_IMP_R6000: 725 c->cputype = CPU_R6000; 726 __cpu_name[cpu] = "R6000"; 727 set_isa(c, MIPS_CPU_ISA_II); 728 c->options = MIPS_CPU_TLB | MIPS_CPU_FPU | 729 MIPS_CPU_LLSC; 730 c->tlbsize = 32; 731 break; 732 case PRID_IMP_R6000A: 733 c->cputype = CPU_R6000A; 734 __cpu_name[cpu] = "R6000A"; 735 set_isa(c, MIPS_CPU_ISA_II); 736 c->options = MIPS_CPU_TLB | MIPS_CPU_FPU | 737 MIPS_CPU_LLSC; 738 c->tlbsize = 32; 739 break; 740 case PRID_IMP_RM7000: 741 c->cputype = CPU_RM7000; 742 __cpu_name[cpu] = "RM7000"; 743 set_isa(c, MIPS_CPU_ISA_IV); 744 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR | 745 MIPS_CPU_LLSC; 746 /* 747 * Undocumented RM7000: Bit 29 in the info register of 748 * the RM7000 v2.0 indicates if the TLB has 48 or 64 749 * entries. 750 * 751 * 29 1 => 64 entry JTLB 752 * 0 => 48 entry JTLB 753 */ 754 c->tlbsize = (read_c0_info() & (1 << 29)) ? 64 : 48; 755 break; 756 case PRID_IMP_RM9000: 757 c->cputype = CPU_RM9000; 758 __cpu_name[cpu] = "RM9000"; 759 set_isa(c, MIPS_CPU_ISA_IV); 760 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR | 761 MIPS_CPU_LLSC; 762 /* 763 * Bit 29 in the info register of the RM9000 764 * indicates if the TLB has 48 or 64 entries. 765 * 766 * 29 1 => 64 entry JTLB 767 * 0 => 48 entry JTLB 768 */ 769 c->tlbsize = (read_c0_info() & (1 << 29)) ? 64 : 48; 770 break; 771 case PRID_IMP_R8000: 772 c->cputype = CPU_R8000; 773 __cpu_name[cpu] = "RM8000"; 774 set_isa(c, MIPS_CPU_ISA_IV); 775 c->options = MIPS_CPU_TLB | MIPS_CPU_4KEX | 776 MIPS_CPU_FPU | MIPS_CPU_32FPR | 777 MIPS_CPU_LLSC; 778 c->tlbsize = 384; /* has weird TLB: 3-way x 128 */ 779 break; 780 case PRID_IMP_R10000: 781 c->cputype = CPU_R10000; 782 __cpu_name[cpu] = "R10000"; 783 set_isa(c, MIPS_CPU_ISA_IV); 784 c->options = MIPS_CPU_TLB | MIPS_CPU_4K_CACHE | MIPS_CPU_4KEX | 785 MIPS_CPU_FPU | MIPS_CPU_32FPR | 786 MIPS_CPU_COUNTER | MIPS_CPU_WATCH | 787 MIPS_CPU_LLSC; 788 c->tlbsize = 64; 789 break; 790 case PRID_IMP_R12000: 791 c->cputype = CPU_R12000; 792 __cpu_name[cpu] = "R12000"; 793 set_isa(c, MIPS_CPU_ISA_IV); 794 c->options = MIPS_CPU_TLB | MIPS_CPU_4K_CACHE | MIPS_CPU_4KEX | 795 MIPS_CPU_FPU | MIPS_CPU_32FPR | 796 MIPS_CPU_COUNTER | MIPS_CPU_WATCH | 797 MIPS_CPU_LLSC; 798 c->tlbsize = 64; 799 break; 800 case PRID_IMP_R14000: 801 c->cputype = CPU_R14000; 802 __cpu_name[cpu] = "R14000"; 803 set_isa(c, MIPS_CPU_ISA_IV); 804 c->options = MIPS_CPU_TLB | MIPS_CPU_4K_CACHE | MIPS_CPU_4KEX | 805 MIPS_CPU_FPU | MIPS_CPU_32FPR | 806 MIPS_CPU_COUNTER | MIPS_CPU_WATCH | 807 MIPS_CPU_LLSC; 808 c->tlbsize = 64; 809 break; 810 case PRID_IMP_LOONGSON2: 811 c->cputype = CPU_LOONGSON2; 812 __cpu_name[cpu] = "ICT Loongson-2"; 813 814 switch (c->processor_id & PRID_REV_MASK) { 815 case PRID_REV_LOONGSON2E: 816 set_elf_platform(cpu, "loongson2e"); 817 break; 818 case PRID_REV_LOONGSON2F: 819 set_elf_platform(cpu, "loongson2f"); 820 break; 821 } 822 823 set_isa(c, MIPS_CPU_ISA_III); 824 c->options = R4K_OPTS | 825 MIPS_CPU_FPU | MIPS_CPU_LLSC | 826 MIPS_CPU_32FPR; 827 c->tlbsize = 64; 828 break; 829 case PRID_IMP_LOONGSON1: 830 decode_configs(c); 831 832 c->cputype = CPU_LOONGSON1; 833 834 switch (c->processor_id & PRID_REV_MASK) { 835 case PRID_REV_LOONGSON1B: 836 __cpu_name[cpu] = "Loongson 1B"; 837 break; 838 } 839 840 break; 841 } 842 } 843 844 static inline void cpu_probe_mips(struct cpuinfo_mips *c, unsigned int cpu) 845 { 846 decode_configs(c); 847 switch (c->processor_id & 0xff00) { 848 case PRID_IMP_4KC: 849 c->cputype = CPU_4KC; 850 __cpu_name[cpu] = "MIPS 4Kc"; 851 break; 852 case PRID_IMP_4KEC: 853 case PRID_IMP_4KECR2: 854 c->cputype = CPU_4KEC; 855 __cpu_name[cpu] = "MIPS 4KEc"; 856 break; 857 case PRID_IMP_4KSC: 858 case PRID_IMP_4KSD: 859 c->cputype = CPU_4KSC; 860 __cpu_name[cpu] = "MIPS 4KSc"; 861 break; 862 case PRID_IMP_5KC: 863 c->cputype = CPU_5KC; 864 __cpu_name[cpu] = "MIPS 5Kc"; 865 break; 866 case PRID_IMP_5KE: 867 c->cputype = CPU_5KE; 868 __cpu_name[cpu] = "MIPS 5KE"; 869 break; 870 case PRID_IMP_20KC: 871 c->cputype = CPU_20KC; 872 __cpu_name[cpu] = "MIPS 20Kc"; 873 break; 874 case PRID_IMP_24K: 875 c->cputype = CPU_24K; 876 __cpu_name[cpu] = "MIPS 24Kc"; 877 break; 878 case PRID_IMP_24KE: 879 c->cputype = CPU_24K; 880 __cpu_name[cpu] = "MIPS 24KEc"; 881 break; 882 case PRID_IMP_25KF: 883 c->cputype = CPU_25KF; 884 __cpu_name[cpu] = "MIPS 25Kc"; 885 break; 886 case PRID_IMP_34K: 887 c->cputype = CPU_34K; 888 __cpu_name[cpu] = "MIPS 34Kc"; 889 break; 890 case PRID_IMP_74K: 891 c->cputype = CPU_74K; 892 __cpu_name[cpu] = "MIPS 74Kc"; 893 break; 894 case PRID_IMP_M14KC: 895 c->cputype = CPU_M14KC; 896 __cpu_name[cpu] = "MIPS M14Kc"; 897 break; 898 case PRID_IMP_M14KEC: 899 c->cputype = CPU_M14KEC; 900 __cpu_name[cpu] = "MIPS M14KEc"; 901 break; 902 case PRID_IMP_1004K: 903 c->cputype = CPU_1004K; 904 __cpu_name[cpu] = "MIPS 1004Kc"; 905 break; 906 case PRID_IMP_1074K: 907 c->cputype = CPU_74K; 908 __cpu_name[cpu] = "MIPS 1074Kc"; 909 break; 910 } 911 912 spram_config(); 913 } 914 915 static inline void cpu_probe_alchemy(struct cpuinfo_mips *c, unsigned int cpu) 916 { 917 decode_configs(c); 918 switch (c->processor_id & 0xff00) { 919 case PRID_IMP_AU1_REV1: 920 case PRID_IMP_AU1_REV2: 921 c->cputype = CPU_ALCHEMY; 922 switch ((c->processor_id >> 24) & 0xff) { 923 case 0: 924 __cpu_name[cpu] = "Au1000"; 925 break; 926 case 1: 927 __cpu_name[cpu] = "Au1500"; 928 break; 929 case 2: 930 __cpu_name[cpu] = "Au1100"; 931 break; 932 case 3: 933 __cpu_name[cpu] = "Au1550"; 934 break; 935 case 4: 936 __cpu_name[cpu] = "Au1200"; 937 if ((c->processor_id & 0xff) == 2) 938 __cpu_name[cpu] = "Au1250"; 939 break; 940 case 5: 941 __cpu_name[cpu] = "Au1210"; 942 break; 943 default: 944 __cpu_name[cpu] = "Au1xxx"; 945 break; 946 } 947 break; 948 } 949 } 950 951 static inline void cpu_probe_sibyte(struct cpuinfo_mips *c, unsigned int cpu) 952 { 953 decode_configs(c); 954 955 switch (c->processor_id & 0xff00) { 956 case PRID_IMP_SB1: 957 c->cputype = CPU_SB1; 958 __cpu_name[cpu] = "SiByte SB1"; 959 /* FPU in pass1 is known to have issues. */ 960 if ((c->processor_id & 0xff) < 0x02) 961 c->options &= ~(MIPS_CPU_FPU | MIPS_CPU_32FPR); 962 break; 963 case PRID_IMP_SB1A: 964 c->cputype = CPU_SB1A; 965 __cpu_name[cpu] = "SiByte SB1A"; 966 break; 967 } 968 } 969 970 static inline void cpu_probe_sandcraft(struct cpuinfo_mips *c, unsigned int cpu) 971 { 972 decode_configs(c); 973 switch (c->processor_id & 0xff00) { 974 case PRID_IMP_SR71000: 975 c->cputype = CPU_SR71000; 976 __cpu_name[cpu] = "Sandcraft SR71000"; 977 c->scache.ways = 8; 978 c->tlbsize = 64; 979 break; 980 } 981 } 982 983 static inline void cpu_probe_nxp(struct cpuinfo_mips *c, unsigned int cpu) 984 { 985 decode_configs(c); 986 switch (c->processor_id & 0xff00) { 987 case PRID_IMP_PR4450: 988 c->cputype = CPU_PR4450; 989 __cpu_name[cpu] = "Philips PR4450"; 990 set_isa(c, MIPS_CPU_ISA_M32R1); 991 break; 992 } 993 } 994 995 static inline void cpu_probe_broadcom(struct cpuinfo_mips *c, unsigned int cpu) 996 { 997 decode_configs(c); 998 switch (c->processor_id & 0xff00) { 999 case PRID_IMP_BMIPS32_REV4: 1000 case PRID_IMP_BMIPS32_REV8: 1001 c->cputype = CPU_BMIPS32; 1002 __cpu_name[cpu] = "Broadcom BMIPS32"; 1003 set_elf_platform(cpu, "bmips32"); 1004 break; 1005 case PRID_IMP_BMIPS3300: 1006 case PRID_IMP_BMIPS3300_ALT: 1007 case PRID_IMP_BMIPS3300_BUG: 1008 c->cputype = CPU_BMIPS3300; 1009 __cpu_name[cpu] = "Broadcom BMIPS3300"; 1010 set_elf_platform(cpu, "bmips3300"); 1011 break; 1012 case PRID_IMP_BMIPS43XX: { 1013 int rev = c->processor_id & 0xff; 1014 1015 if (rev >= PRID_REV_BMIPS4380_LO && 1016 rev <= PRID_REV_BMIPS4380_HI) { 1017 c->cputype = CPU_BMIPS4380; 1018 __cpu_name[cpu] = "Broadcom BMIPS4380"; 1019 set_elf_platform(cpu, "bmips4380"); 1020 } else { 1021 c->cputype = CPU_BMIPS4350; 1022 __cpu_name[cpu] = "Broadcom BMIPS4350"; 1023 set_elf_platform(cpu, "bmips4350"); 1024 } 1025 break; 1026 } 1027 case PRID_IMP_BMIPS5000: 1028 c->cputype = CPU_BMIPS5000; 1029 __cpu_name[cpu] = "Broadcom BMIPS5000"; 1030 set_elf_platform(cpu, "bmips5000"); 1031 c->options |= MIPS_CPU_ULRI; 1032 break; 1033 } 1034 } 1035 1036 static inline void cpu_probe_cavium(struct cpuinfo_mips *c, unsigned int cpu) 1037 { 1038 decode_configs(c); 1039 switch (c->processor_id & 0xff00) { 1040 case PRID_IMP_CAVIUM_CN38XX: 1041 case PRID_IMP_CAVIUM_CN31XX: 1042 case PRID_IMP_CAVIUM_CN30XX: 1043 c->cputype = CPU_CAVIUM_OCTEON; 1044 __cpu_name[cpu] = "Cavium Octeon"; 1045 goto platform; 1046 case PRID_IMP_CAVIUM_CN58XX: 1047 case PRID_IMP_CAVIUM_CN56XX: 1048 case PRID_IMP_CAVIUM_CN50XX: 1049 case PRID_IMP_CAVIUM_CN52XX: 1050 c->cputype = CPU_CAVIUM_OCTEON_PLUS; 1051 __cpu_name[cpu] = "Cavium Octeon+"; 1052 platform: 1053 set_elf_platform(cpu, "octeon"); 1054 break; 1055 case PRID_IMP_CAVIUM_CN61XX: 1056 case PRID_IMP_CAVIUM_CN63XX: 1057 case PRID_IMP_CAVIUM_CN66XX: 1058 case PRID_IMP_CAVIUM_CN68XX: 1059 c->cputype = CPU_CAVIUM_OCTEON2; 1060 __cpu_name[cpu] = "Cavium Octeon II"; 1061 set_elf_platform(cpu, "octeon2"); 1062 break; 1063 default: 1064 printk(KERN_INFO "Unknown Octeon chip!\n"); 1065 c->cputype = CPU_UNKNOWN; 1066 break; 1067 } 1068 } 1069 1070 static inline void cpu_probe_ingenic(struct cpuinfo_mips *c, unsigned int cpu) 1071 { 1072 decode_configs(c); 1073 /* JZRISC does not implement the CP0 counter. */ 1074 c->options &= ~MIPS_CPU_COUNTER; 1075 switch (c->processor_id & 0xff00) { 1076 case PRID_IMP_JZRISC: 1077 c->cputype = CPU_JZRISC; 1078 __cpu_name[cpu] = "Ingenic JZRISC"; 1079 break; 1080 default: 1081 panic("Unknown Ingenic Processor ID!"); 1082 break; 1083 } 1084 } 1085 1086 static inline void cpu_probe_netlogic(struct cpuinfo_mips *c, int cpu) 1087 { 1088 decode_configs(c); 1089 1090 if ((c->processor_id & 0xff00) == PRID_IMP_NETLOGIC_AU13XX) { 1091 c->cputype = CPU_ALCHEMY; 1092 __cpu_name[cpu] = "Au1300"; 1093 /* following stuff is not for Alchemy */ 1094 return; 1095 } 1096 1097 c->options = (MIPS_CPU_TLB | 1098 MIPS_CPU_4KEX | 1099 MIPS_CPU_COUNTER | 1100 MIPS_CPU_DIVEC | 1101 MIPS_CPU_WATCH | 1102 MIPS_CPU_EJTAG | 1103 MIPS_CPU_LLSC); 1104 1105 switch (c->processor_id & 0xff00) { 1106 case PRID_IMP_NETLOGIC_XLP8XX: 1107 case PRID_IMP_NETLOGIC_XLP3XX: 1108 c->cputype = CPU_XLP; 1109 __cpu_name[cpu] = "Netlogic XLP"; 1110 break; 1111 1112 case PRID_IMP_NETLOGIC_XLR732: 1113 case PRID_IMP_NETLOGIC_XLR716: 1114 case PRID_IMP_NETLOGIC_XLR532: 1115 case PRID_IMP_NETLOGIC_XLR308: 1116 case PRID_IMP_NETLOGIC_XLR532C: 1117 case PRID_IMP_NETLOGIC_XLR516C: 1118 case PRID_IMP_NETLOGIC_XLR508C: 1119 case PRID_IMP_NETLOGIC_XLR308C: 1120 c->cputype = CPU_XLR; 1121 __cpu_name[cpu] = "Netlogic XLR"; 1122 break; 1123 1124 case PRID_IMP_NETLOGIC_XLS608: 1125 case PRID_IMP_NETLOGIC_XLS408: 1126 case PRID_IMP_NETLOGIC_XLS404: 1127 case PRID_IMP_NETLOGIC_XLS208: 1128 case PRID_IMP_NETLOGIC_XLS204: 1129 case PRID_IMP_NETLOGIC_XLS108: 1130 case PRID_IMP_NETLOGIC_XLS104: 1131 case PRID_IMP_NETLOGIC_XLS616B: 1132 case PRID_IMP_NETLOGIC_XLS608B: 1133 case PRID_IMP_NETLOGIC_XLS416B: 1134 case PRID_IMP_NETLOGIC_XLS412B: 1135 case PRID_IMP_NETLOGIC_XLS408B: 1136 case PRID_IMP_NETLOGIC_XLS404B: 1137 c->cputype = CPU_XLR; 1138 __cpu_name[cpu] = "Netlogic XLS"; 1139 break; 1140 1141 default: 1142 pr_info("Unknown Netlogic chip id [%02x]!\n", 1143 c->processor_id); 1144 c->cputype = CPU_XLR; 1145 break; 1146 } 1147 1148 if (c->cputype == CPU_XLP) { 1149 set_isa(c, MIPS_CPU_ISA_M64R2); 1150 c->options |= (MIPS_CPU_FPU | MIPS_CPU_ULRI | MIPS_CPU_MCHECK); 1151 /* This will be updated again after all threads are woken up */ 1152 c->tlbsize = ((read_c0_config6() >> 16) & 0xffff) + 1; 1153 } else { 1154 set_isa(c, MIPS_CPU_ISA_M64R1); 1155 c->tlbsize = ((read_c0_config1() >> 25) & 0x3f) + 1; 1156 } 1157 } 1158 1159 #ifdef CONFIG_64BIT 1160 /* For use by uaccess.h */ 1161 u64 __ua_limit; 1162 EXPORT_SYMBOL(__ua_limit); 1163 #endif 1164 1165 const char *__cpu_name[NR_CPUS]; 1166 const char *__elf_platform; 1167 1168 __cpuinit void cpu_probe(void) 1169 { 1170 struct cpuinfo_mips *c = ¤t_cpu_data; 1171 unsigned int cpu = smp_processor_id(); 1172 1173 c->processor_id = PRID_IMP_UNKNOWN; 1174 c->fpu_id = FPIR_IMP_NONE; 1175 c->cputype = CPU_UNKNOWN; 1176 1177 c->processor_id = read_c0_prid(); 1178 switch (c->processor_id & 0xff0000) { 1179 case PRID_COMP_LEGACY: 1180 cpu_probe_legacy(c, cpu); 1181 break; 1182 case PRID_COMP_MIPS: 1183 cpu_probe_mips(c, cpu); 1184 break; 1185 case PRID_COMP_ALCHEMY: 1186 cpu_probe_alchemy(c, cpu); 1187 break; 1188 case PRID_COMP_SIBYTE: 1189 cpu_probe_sibyte(c, cpu); 1190 break; 1191 case PRID_COMP_BROADCOM: 1192 cpu_probe_broadcom(c, cpu); 1193 break; 1194 case PRID_COMP_SANDCRAFT: 1195 cpu_probe_sandcraft(c, cpu); 1196 break; 1197 case PRID_COMP_NXP: 1198 cpu_probe_nxp(c, cpu); 1199 break; 1200 case PRID_COMP_CAVIUM: 1201 cpu_probe_cavium(c, cpu); 1202 break; 1203 case PRID_COMP_INGENIC: 1204 cpu_probe_ingenic(c, cpu); 1205 break; 1206 case PRID_COMP_NETLOGIC: 1207 cpu_probe_netlogic(c, cpu); 1208 break; 1209 } 1210 1211 BUG_ON(!__cpu_name[cpu]); 1212 BUG_ON(c->cputype == CPU_UNKNOWN); 1213 1214 /* 1215 * Platform code can force the cpu type to optimize code 1216 * generation. In that case be sure the cpu type is correctly 1217 * manually setup otherwise it could trigger some nasty bugs. 1218 */ 1219 BUG_ON(current_cpu_type() != c->cputype); 1220 1221 if (mips_fpu_disabled) 1222 c->options &= ~MIPS_CPU_FPU; 1223 1224 if (mips_dsp_disabled) 1225 c->ases &= ~(MIPS_ASE_DSP | MIPS_ASE_DSP2P); 1226 1227 if (c->options & MIPS_CPU_FPU) { 1228 c->fpu_id = cpu_get_fpu_id(); 1229 1230 if (c->isa_level & (MIPS_CPU_ISA_M32R1 | MIPS_CPU_ISA_M32R2 | 1231 MIPS_CPU_ISA_M64R1 | MIPS_CPU_ISA_M64R2)) { 1232 if (c->fpu_id & MIPS_FPIR_3D) 1233 c->ases |= MIPS_ASE_MIPS3D; 1234 } 1235 } 1236 1237 if (cpu_has_mips_r2) { 1238 c->srsets = ((read_c0_srsctl() >> 26) & 0x0f) + 1; 1239 /* R2 has Performance Counter Interrupt indicator */ 1240 c->options |= MIPS_CPU_PCI; 1241 } 1242 else 1243 c->srsets = 1; 1244 1245 cpu_probe_vmbits(c); 1246 1247 #ifdef CONFIG_64BIT 1248 if (cpu == 0) 1249 __ua_limit = ~((1ull << cpu_vmbits) - 1); 1250 #endif 1251 } 1252 1253 __cpuinit void cpu_report(void) 1254 { 1255 struct cpuinfo_mips *c = ¤t_cpu_data; 1256 1257 printk(KERN_INFO "CPU revision is: %08x (%s)\n", 1258 c->processor_id, cpu_name_string()); 1259 if (c->options & MIPS_CPU_FPU) 1260 printk(KERN_INFO "FPU revision is: %08x\n", c->fpu_id); 1261 } 1262