1 /* 2 * Processor capabilities determination functions. 3 * 4 * Copyright (C) xxxx the Anonymous 5 * Copyright (C) 1994 - 2006 Ralf Baechle 6 * Copyright (C) 2003, 2004 Maciej W. Rozycki 7 * Copyright (C) 2001, 2004 MIPS Inc. 8 * 9 * This program is free software; you can redistribute it and/or 10 * modify it under the terms of the GNU General Public License 11 * as published by the Free Software Foundation; either version 12 * 2 of the License, or (at your option) any later version. 13 */ 14 #include <linux/init.h> 15 #include <linux/kernel.h> 16 #include <linux/ptrace.h> 17 #include <linux/stddef.h> 18 19 #include <asm/bugs.h> 20 #include <asm/cpu.h> 21 #include <asm/fpu.h> 22 #include <asm/mipsregs.h> 23 #include <asm/system.h> 24 25 /* 26 * Not all of the MIPS CPUs have the "wait" instruction available. Moreover, 27 * the implementation of the "wait" feature differs between CPU families. This 28 * points to the function that implements CPU specific wait. 29 * The wait instruction stops the pipeline and reduces the power consumption of 30 * the CPU very much. 31 */ 32 void (*cpu_wait)(void) = NULL; 33 34 static void r3081_wait(void) 35 { 36 unsigned long cfg = read_c0_conf(); 37 write_c0_conf(cfg | R30XX_CONF_HALT); 38 } 39 40 static void r39xx_wait(void) 41 { 42 local_irq_disable(); 43 if (!need_resched()) 44 write_c0_conf(read_c0_conf() | TX39_CONF_HALT); 45 local_irq_enable(); 46 } 47 48 extern void r4k_wait(void); 49 50 /* 51 * This variant is preferable as it allows testing need_resched and going to 52 * sleep depending on the outcome atomically. Unfortunately the "It is 53 * implementation-dependent whether the pipeline restarts when a non-enabled 54 * interrupt is requested" restriction in the MIPS32/MIPS64 architecture makes 55 * using this version a gamble. 56 */ 57 static void r4k_wait_irqoff(void) 58 { 59 local_irq_disable(); 60 if (!need_resched()) 61 __asm__(" .set mips3 \n" 62 " wait \n" 63 " .set mips0 \n"); 64 local_irq_enable(); 65 } 66 67 /* 68 * The RM7000 variant has to handle erratum 38. The workaround is to not 69 * have any pending stores when the WAIT instruction is executed. 70 */ 71 static void rm7k_wait_irqoff(void) 72 { 73 local_irq_disable(); 74 if (!need_resched()) 75 __asm__( 76 " .set push \n" 77 " .set mips3 \n" 78 " .set noat \n" 79 " mfc0 $1, $12 \n" 80 " sync \n" 81 " mtc0 $1, $12 # stalls until W stage \n" 82 " wait \n" 83 " mtc0 $1, $12 # stalls until W stage \n" 84 " .set pop \n"); 85 local_irq_enable(); 86 } 87 88 /* The Au1xxx wait is available only if using 32khz counter or 89 * external timer source, but specifically not CP0 Counter. */ 90 int allow_au1k_wait; 91 92 static void au1k_wait(void) 93 { 94 /* using the wait instruction makes CP0 counter unusable */ 95 __asm__(" .set mips3 \n" 96 " cache 0x14, 0(%0) \n" 97 " cache 0x14, 32(%0) \n" 98 " sync \n" 99 " nop \n" 100 " wait \n" 101 " nop \n" 102 " nop \n" 103 " nop \n" 104 " nop \n" 105 " .set mips0 \n" 106 : : "r" (au1k_wait)); 107 } 108 109 static int __initdata nowait = 0; 110 111 static int __init wait_disable(char *s) 112 { 113 nowait = 1; 114 115 return 1; 116 } 117 118 __setup("nowait", wait_disable); 119 120 void __init check_wait(void) 121 { 122 struct cpuinfo_mips *c = ¤t_cpu_data; 123 124 if (nowait) { 125 printk("Wait instruction disabled.\n"); 126 return; 127 } 128 129 switch (c->cputype) { 130 case CPU_R3081: 131 case CPU_R3081E: 132 cpu_wait = r3081_wait; 133 break; 134 case CPU_TX3927: 135 cpu_wait = r39xx_wait; 136 break; 137 case CPU_R4200: 138 /* case CPU_R4300: */ 139 case CPU_R4600: 140 case CPU_R4640: 141 case CPU_R4650: 142 case CPU_R4700: 143 case CPU_R5000: 144 case CPU_NEVADA: 145 case CPU_4KC: 146 case CPU_4KEC: 147 case CPU_4KSC: 148 case CPU_5KC: 149 case CPU_25KF: 150 case CPU_PR4450: 151 case CPU_BCM3302: 152 cpu_wait = r4k_wait; 153 break; 154 155 case CPU_RM7000: 156 cpu_wait = rm7k_wait_irqoff; 157 break; 158 159 case CPU_24K: 160 case CPU_34K: 161 case CPU_1004K: 162 cpu_wait = r4k_wait; 163 if (read_c0_config7() & MIPS_CONF7_WII) 164 cpu_wait = r4k_wait_irqoff; 165 break; 166 167 case CPU_74K: 168 cpu_wait = r4k_wait; 169 if ((c->processor_id & 0xff) >= PRID_REV_ENCODE_332(2, 1, 0)) 170 cpu_wait = r4k_wait_irqoff; 171 break; 172 173 case CPU_TX49XX: 174 cpu_wait = r4k_wait_irqoff; 175 break; 176 case CPU_AU1000: 177 case CPU_AU1100: 178 case CPU_AU1500: 179 case CPU_AU1550: 180 case CPU_AU1200: 181 case CPU_AU1210: 182 case CPU_AU1250: 183 if (allow_au1k_wait) 184 cpu_wait = au1k_wait; 185 break; 186 case CPU_20KC: 187 /* 188 * WAIT on Rev1.0 has E1, E2, E3 and E16. 189 * WAIT on Rev2.0 and Rev3.0 has E16. 190 * Rev3.1 WAIT is nop, why bother 191 */ 192 if ((c->processor_id & 0xff) <= 0x64) 193 break; 194 195 /* 196 * Another rev is incremeting c0_count at a reduced clock 197 * rate while in WAIT mode. So we basically have the choice 198 * between using the cp0 timer as clocksource or avoiding 199 * the WAIT instruction. Until more details are known, 200 * disable the use of WAIT for 20Kc entirely. 201 cpu_wait = r4k_wait; 202 */ 203 break; 204 case CPU_RM9000: 205 if ((c->processor_id & 0x00ff) >= 0x40) 206 cpu_wait = r4k_wait; 207 break; 208 default: 209 break; 210 } 211 } 212 213 static inline void check_errata(void) 214 { 215 struct cpuinfo_mips *c = ¤t_cpu_data; 216 217 switch (c->cputype) { 218 case CPU_34K: 219 /* 220 * Erratum "RPS May Cause Incorrect Instruction Execution" 221 * This code only handles VPE0, any SMP/SMTC/RTOS code 222 * making use of VPE1 will be responsable for that VPE. 223 */ 224 if ((c->processor_id & PRID_REV_MASK) <= PRID_REV_34K_V1_0_2) 225 write_c0_config7(read_c0_config7() | MIPS_CONF7_RPS); 226 break; 227 default: 228 break; 229 } 230 } 231 232 void __init check_bugs32(void) 233 { 234 check_errata(); 235 } 236 237 /* 238 * Probe whether cpu has config register by trying to play with 239 * alternate cache bit and see whether it matters. 240 * It's used by cpu_probe to distinguish between R3000A and R3081. 241 */ 242 static inline int cpu_has_confreg(void) 243 { 244 #ifdef CONFIG_CPU_R3000 245 extern unsigned long r3k_cache_size(unsigned long); 246 unsigned long size1, size2; 247 unsigned long cfg = read_c0_conf(); 248 249 size1 = r3k_cache_size(ST0_ISC); 250 write_c0_conf(cfg ^ R30XX_CONF_AC); 251 size2 = r3k_cache_size(ST0_ISC); 252 write_c0_conf(cfg); 253 return size1 != size2; 254 #else 255 return 0; 256 #endif 257 } 258 259 /* 260 * Get the FPU Implementation/Revision. 261 */ 262 static inline unsigned long cpu_get_fpu_id(void) 263 { 264 unsigned long tmp, fpu_id; 265 266 tmp = read_c0_status(); 267 __enable_fpu(); 268 fpu_id = read_32bit_cp1_register(CP1_REVISION); 269 write_c0_status(tmp); 270 return fpu_id; 271 } 272 273 /* 274 * Check the CPU has an FPU the official way. 275 */ 276 static inline int __cpu_has_fpu(void) 277 { 278 return ((cpu_get_fpu_id() & 0xff00) != FPIR_IMP_NONE); 279 } 280 281 #define R4K_OPTS (MIPS_CPU_TLB | MIPS_CPU_4KEX | MIPS_CPU_4K_CACHE \ 282 | MIPS_CPU_COUNTER) 283 284 static inline void cpu_probe_legacy(struct cpuinfo_mips *c) 285 { 286 switch (c->processor_id & 0xff00) { 287 case PRID_IMP_R2000: 288 c->cputype = CPU_R2000; 289 c->isa_level = MIPS_CPU_ISA_I; 290 c->options = MIPS_CPU_TLB | MIPS_CPU_3K_CACHE | 291 MIPS_CPU_NOFPUEX; 292 if (__cpu_has_fpu()) 293 c->options |= MIPS_CPU_FPU; 294 c->tlbsize = 64; 295 break; 296 case PRID_IMP_R3000: 297 if ((c->processor_id & 0xff) == PRID_REV_R3000A) 298 if (cpu_has_confreg()) 299 c->cputype = CPU_R3081E; 300 else 301 c->cputype = CPU_R3000A; 302 else 303 c->cputype = CPU_R3000; 304 c->isa_level = MIPS_CPU_ISA_I; 305 c->options = MIPS_CPU_TLB | MIPS_CPU_3K_CACHE | 306 MIPS_CPU_NOFPUEX; 307 if (__cpu_has_fpu()) 308 c->options |= MIPS_CPU_FPU; 309 c->tlbsize = 64; 310 break; 311 case PRID_IMP_R4000: 312 if (read_c0_config() & CONF_SC) { 313 if ((c->processor_id & 0xff) >= PRID_REV_R4400) 314 c->cputype = CPU_R4400PC; 315 else 316 c->cputype = CPU_R4000PC; 317 } else { 318 if ((c->processor_id & 0xff) >= PRID_REV_R4400) 319 c->cputype = CPU_R4400SC; 320 else 321 c->cputype = CPU_R4000SC; 322 } 323 324 c->isa_level = MIPS_CPU_ISA_III; 325 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR | 326 MIPS_CPU_WATCH | MIPS_CPU_VCE | 327 MIPS_CPU_LLSC; 328 c->tlbsize = 48; 329 break; 330 case PRID_IMP_VR41XX: 331 switch (c->processor_id & 0xf0) { 332 case PRID_REV_VR4111: 333 c->cputype = CPU_VR4111; 334 break; 335 case PRID_REV_VR4121: 336 c->cputype = CPU_VR4121; 337 break; 338 case PRID_REV_VR4122: 339 if ((c->processor_id & 0xf) < 0x3) 340 c->cputype = CPU_VR4122; 341 else 342 c->cputype = CPU_VR4181A; 343 break; 344 case PRID_REV_VR4130: 345 if ((c->processor_id & 0xf) < 0x4) 346 c->cputype = CPU_VR4131; 347 else 348 c->cputype = CPU_VR4133; 349 break; 350 default: 351 printk(KERN_INFO "Unexpected CPU of NEC VR4100 series\n"); 352 c->cputype = CPU_VR41XX; 353 break; 354 } 355 c->isa_level = MIPS_CPU_ISA_III; 356 c->options = R4K_OPTS; 357 c->tlbsize = 32; 358 break; 359 case PRID_IMP_R4300: 360 c->cputype = CPU_R4300; 361 c->isa_level = MIPS_CPU_ISA_III; 362 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR | 363 MIPS_CPU_LLSC; 364 c->tlbsize = 32; 365 break; 366 case PRID_IMP_R4600: 367 c->cputype = CPU_R4600; 368 c->isa_level = MIPS_CPU_ISA_III; 369 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR | 370 MIPS_CPU_LLSC; 371 c->tlbsize = 48; 372 break; 373 #if 0 374 case PRID_IMP_R4650: 375 /* 376 * This processor doesn't have an MMU, so it's not 377 * "real easy" to run Linux on it. It is left purely 378 * for documentation. Commented out because it shares 379 * it's c0_prid id number with the TX3900. 380 */ 381 c->cputype = CPU_R4650; 382 c->isa_level = MIPS_CPU_ISA_III; 383 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_LLSC; 384 c->tlbsize = 48; 385 break; 386 #endif 387 case PRID_IMP_TX39: 388 c->isa_level = MIPS_CPU_ISA_I; 389 c->options = MIPS_CPU_TLB | MIPS_CPU_TX39_CACHE; 390 391 if ((c->processor_id & 0xf0) == (PRID_REV_TX3927 & 0xf0)) { 392 c->cputype = CPU_TX3927; 393 c->tlbsize = 64; 394 } else { 395 switch (c->processor_id & 0xff) { 396 case PRID_REV_TX3912: 397 c->cputype = CPU_TX3912; 398 c->tlbsize = 32; 399 break; 400 case PRID_REV_TX3922: 401 c->cputype = CPU_TX3922; 402 c->tlbsize = 64; 403 break; 404 default: 405 c->cputype = CPU_UNKNOWN; 406 break; 407 } 408 } 409 break; 410 case PRID_IMP_R4700: 411 c->cputype = CPU_R4700; 412 c->isa_level = MIPS_CPU_ISA_III; 413 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR | 414 MIPS_CPU_LLSC; 415 c->tlbsize = 48; 416 break; 417 case PRID_IMP_TX49: 418 c->cputype = CPU_TX49XX; 419 c->isa_level = MIPS_CPU_ISA_III; 420 c->options = R4K_OPTS | MIPS_CPU_LLSC; 421 if (!(c->processor_id & 0x08)) 422 c->options |= MIPS_CPU_FPU | MIPS_CPU_32FPR; 423 c->tlbsize = 48; 424 break; 425 case PRID_IMP_R5000: 426 c->cputype = CPU_R5000; 427 c->isa_level = MIPS_CPU_ISA_IV; 428 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR | 429 MIPS_CPU_LLSC; 430 c->tlbsize = 48; 431 break; 432 case PRID_IMP_R5432: 433 c->cputype = CPU_R5432; 434 c->isa_level = MIPS_CPU_ISA_IV; 435 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR | 436 MIPS_CPU_WATCH | MIPS_CPU_LLSC; 437 c->tlbsize = 48; 438 break; 439 case PRID_IMP_R5500: 440 c->cputype = CPU_R5500; 441 c->isa_level = MIPS_CPU_ISA_IV; 442 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR | 443 MIPS_CPU_WATCH | MIPS_CPU_LLSC; 444 c->tlbsize = 48; 445 break; 446 case PRID_IMP_NEVADA: 447 c->cputype = CPU_NEVADA; 448 c->isa_level = MIPS_CPU_ISA_IV; 449 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR | 450 MIPS_CPU_DIVEC | MIPS_CPU_LLSC; 451 c->tlbsize = 48; 452 break; 453 case PRID_IMP_R6000: 454 c->cputype = CPU_R6000; 455 c->isa_level = MIPS_CPU_ISA_II; 456 c->options = MIPS_CPU_TLB | MIPS_CPU_FPU | 457 MIPS_CPU_LLSC; 458 c->tlbsize = 32; 459 break; 460 case PRID_IMP_R6000A: 461 c->cputype = CPU_R6000A; 462 c->isa_level = MIPS_CPU_ISA_II; 463 c->options = MIPS_CPU_TLB | MIPS_CPU_FPU | 464 MIPS_CPU_LLSC; 465 c->tlbsize = 32; 466 break; 467 case PRID_IMP_RM7000: 468 c->cputype = CPU_RM7000; 469 c->isa_level = MIPS_CPU_ISA_IV; 470 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR | 471 MIPS_CPU_LLSC; 472 /* 473 * Undocumented RM7000: Bit 29 in the info register of 474 * the RM7000 v2.0 indicates if the TLB has 48 or 64 475 * entries. 476 * 477 * 29 1 => 64 entry JTLB 478 * 0 => 48 entry JTLB 479 */ 480 c->tlbsize = (read_c0_info() & (1 << 29)) ? 64 : 48; 481 break; 482 case PRID_IMP_RM9000: 483 c->cputype = CPU_RM9000; 484 c->isa_level = MIPS_CPU_ISA_IV; 485 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR | 486 MIPS_CPU_LLSC; 487 /* 488 * Bit 29 in the info register of the RM9000 489 * indicates if the TLB has 48 or 64 entries. 490 * 491 * 29 1 => 64 entry JTLB 492 * 0 => 48 entry JTLB 493 */ 494 c->tlbsize = (read_c0_info() & (1 << 29)) ? 64 : 48; 495 break; 496 case PRID_IMP_R8000: 497 c->cputype = CPU_R8000; 498 c->isa_level = MIPS_CPU_ISA_IV; 499 c->options = MIPS_CPU_TLB | MIPS_CPU_4KEX | 500 MIPS_CPU_FPU | MIPS_CPU_32FPR | 501 MIPS_CPU_LLSC; 502 c->tlbsize = 384; /* has weird TLB: 3-way x 128 */ 503 break; 504 case PRID_IMP_R10000: 505 c->cputype = CPU_R10000; 506 c->isa_level = MIPS_CPU_ISA_IV; 507 c->options = MIPS_CPU_TLB | MIPS_CPU_4K_CACHE | MIPS_CPU_4KEX | 508 MIPS_CPU_FPU | MIPS_CPU_32FPR | 509 MIPS_CPU_COUNTER | MIPS_CPU_WATCH | 510 MIPS_CPU_LLSC; 511 c->tlbsize = 64; 512 break; 513 case PRID_IMP_R12000: 514 c->cputype = CPU_R12000; 515 c->isa_level = MIPS_CPU_ISA_IV; 516 c->options = MIPS_CPU_TLB | MIPS_CPU_4K_CACHE | MIPS_CPU_4KEX | 517 MIPS_CPU_FPU | MIPS_CPU_32FPR | 518 MIPS_CPU_COUNTER | MIPS_CPU_WATCH | 519 MIPS_CPU_LLSC; 520 c->tlbsize = 64; 521 break; 522 case PRID_IMP_R14000: 523 c->cputype = CPU_R14000; 524 c->isa_level = MIPS_CPU_ISA_IV; 525 c->options = MIPS_CPU_TLB | MIPS_CPU_4K_CACHE | MIPS_CPU_4KEX | 526 MIPS_CPU_FPU | MIPS_CPU_32FPR | 527 MIPS_CPU_COUNTER | MIPS_CPU_WATCH | 528 MIPS_CPU_LLSC; 529 c->tlbsize = 64; 530 break; 531 case PRID_IMP_LOONGSON2: 532 c->cputype = CPU_LOONGSON2; 533 c->isa_level = MIPS_CPU_ISA_III; 534 c->options = R4K_OPTS | 535 MIPS_CPU_FPU | MIPS_CPU_LLSC | 536 MIPS_CPU_32FPR; 537 c->tlbsize = 64; 538 break; 539 } 540 } 541 542 static char unknown_isa[] __cpuinitdata = KERN_ERR \ 543 "Unsupported ISA type, c0.config0: %d."; 544 545 static inline unsigned int decode_config0(struct cpuinfo_mips *c) 546 { 547 unsigned int config0; 548 int isa; 549 550 config0 = read_c0_config(); 551 552 if (((config0 & MIPS_CONF_MT) >> 7) == 1) 553 c->options |= MIPS_CPU_TLB; 554 isa = (config0 & MIPS_CONF_AT) >> 13; 555 switch (isa) { 556 case 0: 557 switch ((config0 & MIPS_CONF_AR) >> 10) { 558 case 0: 559 c->isa_level = MIPS_CPU_ISA_M32R1; 560 break; 561 case 1: 562 c->isa_level = MIPS_CPU_ISA_M32R2; 563 break; 564 default: 565 goto unknown; 566 } 567 break; 568 case 2: 569 switch ((config0 & MIPS_CONF_AR) >> 10) { 570 case 0: 571 c->isa_level = MIPS_CPU_ISA_M64R1; 572 break; 573 case 1: 574 c->isa_level = MIPS_CPU_ISA_M64R2; 575 break; 576 default: 577 goto unknown; 578 } 579 break; 580 default: 581 goto unknown; 582 } 583 584 return config0 & MIPS_CONF_M; 585 586 unknown: 587 panic(unknown_isa, config0); 588 } 589 590 static inline unsigned int decode_config1(struct cpuinfo_mips *c) 591 { 592 unsigned int config1; 593 594 config1 = read_c0_config1(); 595 596 if (config1 & MIPS_CONF1_MD) 597 c->ases |= MIPS_ASE_MDMX; 598 if (config1 & MIPS_CONF1_WR) 599 c->options |= MIPS_CPU_WATCH; 600 if (config1 & MIPS_CONF1_CA) 601 c->ases |= MIPS_ASE_MIPS16; 602 if (config1 & MIPS_CONF1_EP) 603 c->options |= MIPS_CPU_EJTAG; 604 if (config1 & MIPS_CONF1_FP) { 605 c->options |= MIPS_CPU_FPU; 606 c->options |= MIPS_CPU_32FPR; 607 } 608 if (cpu_has_tlb) 609 c->tlbsize = ((config1 & MIPS_CONF1_TLBS) >> 25) + 1; 610 611 return config1 & MIPS_CONF_M; 612 } 613 614 static inline unsigned int decode_config2(struct cpuinfo_mips *c) 615 { 616 unsigned int config2; 617 618 config2 = read_c0_config2(); 619 620 if (config2 & MIPS_CONF2_SL) 621 c->scache.flags &= ~MIPS_CACHE_NOT_PRESENT; 622 623 return config2 & MIPS_CONF_M; 624 } 625 626 static inline unsigned int decode_config3(struct cpuinfo_mips *c) 627 { 628 unsigned int config3; 629 630 config3 = read_c0_config3(); 631 632 if (config3 & MIPS_CONF3_SM) 633 c->ases |= MIPS_ASE_SMARTMIPS; 634 if (config3 & MIPS_CONF3_DSP) 635 c->ases |= MIPS_ASE_DSP; 636 if (config3 & MIPS_CONF3_VINT) 637 c->options |= MIPS_CPU_VINT; 638 if (config3 & MIPS_CONF3_VEIC) 639 c->options |= MIPS_CPU_VEIC; 640 if (config3 & MIPS_CONF3_MT) 641 c->ases |= MIPS_ASE_MIPSMT; 642 if (config3 & MIPS_CONF3_ULRI) 643 c->options |= MIPS_CPU_ULRI; 644 645 return config3 & MIPS_CONF_M; 646 } 647 648 static void __cpuinit decode_configs(struct cpuinfo_mips *c) 649 { 650 /* MIPS32 or MIPS64 compliant CPU. */ 651 c->options = MIPS_CPU_4KEX | MIPS_CPU_4K_CACHE | MIPS_CPU_COUNTER | 652 MIPS_CPU_DIVEC | MIPS_CPU_LLSC | MIPS_CPU_MCHECK; 653 654 c->scache.flags = MIPS_CACHE_NOT_PRESENT; 655 656 /* Read Config registers. */ 657 if (!decode_config0(c)) 658 return; /* actually worth a panic() */ 659 if (!decode_config1(c)) 660 return; 661 if (!decode_config2(c)) 662 return; 663 if (!decode_config3(c)) 664 return; 665 } 666 667 #ifdef CONFIG_CPU_MIPSR2 668 extern void spram_config(void); 669 #else 670 static inline void spram_config(void) {} 671 #endif 672 673 static inline void cpu_probe_mips(struct cpuinfo_mips *c) 674 { 675 decode_configs(c); 676 switch (c->processor_id & 0xff00) { 677 case PRID_IMP_4KC: 678 c->cputype = CPU_4KC; 679 break; 680 case PRID_IMP_4KEC: 681 c->cputype = CPU_4KEC; 682 break; 683 case PRID_IMP_4KECR2: 684 c->cputype = CPU_4KEC; 685 break; 686 case PRID_IMP_4KSC: 687 case PRID_IMP_4KSD: 688 c->cputype = CPU_4KSC; 689 break; 690 case PRID_IMP_5KC: 691 c->cputype = CPU_5KC; 692 break; 693 case PRID_IMP_20KC: 694 c->cputype = CPU_20KC; 695 break; 696 case PRID_IMP_24K: 697 case PRID_IMP_24KE: 698 c->cputype = CPU_24K; 699 break; 700 case PRID_IMP_25KF: 701 c->cputype = CPU_25KF; 702 break; 703 case PRID_IMP_34K: 704 c->cputype = CPU_34K; 705 break; 706 case PRID_IMP_74K: 707 c->cputype = CPU_74K; 708 break; 709 case PRID_IMP_1004K: 710 c->cputype = CPU_1004K; 711 break; 712 } 713 714 spram_config(); 715 } 716 717 static inline void cpu_probe_alchemy(struct cpuinfo_mips *c) 718 { 719 decode_configs(c); 720 switch (c->processor_id & 0xff00) { 721 case PRID_IMP_AU1_REV1: 722 case PRID_IMP_AU1_REV2: 723 switch ((c->processor_id >> 24) & 0xff) { 724 case 0: 725 c->cputype = CPU_AU1000; 726 break; 727 case 1: 728 c->cputype = CPU_AU1500; 729 break; 730 case 2: 731 c->cputype = CPU_AU1100; 732 break; 733 case 3: 734 c->cputype = CPU_AU1550; 735 break; 736 case 4: 737 c->cputype = CPU_AU1200; 738 if (2 == (c->processor_id & 0xff)) 739 c->cputype = CPU_AU1250; 740 break; 741 case 5: 742 c->cputype = CPU_AU1210; 743 break; 744 default: 745 panic("Unknown Au Core!"); 746 break; 747 } 748 break; 749 } 750 } 751 752 static inline void cpu_probe_sibyte(struct cpuinfo_mips *c) 753 { 754 decode_configs(c); 755 756 switch (c->processor_id & 0xff00) { 757 case PRID_IMP_SB1: 758 c->cputype = CPU_SB1; 759 /* FPU in pass1 is known to have issues. */ 760 if ((c->processor_id & 0xff) < 0x02) 761 c->options &= ~(MIPS_CPU_FPU | MIPS_CPU_32FPR); 762 break; 763 case PRID_IMP_SB1A: 764 c->cputype = CPU_SB1A; 765 break; 766 } 767 } 768 769 static inline void cpu_probe_sandcraft(struct cpuinfo_mips *c) 770 { 771 decode_configs(c); 772 switch (c->processor_id & 0xff00) { 773 case PRID_IMP_SR71000: 774 c->cputype = CPU_SR71000; 775 c->scache.ways = 8; 776 c->tlbsize = 64; 777 break; 778 } 779 } 780 781 static inline void cpu_probe_nxp(struct cpuinfo_mips *c) 782 { 783 decode_configs(c); 784 switch (c->processor_id & 0xff00) { 785 case PRID_IMP_PR4450: 786 c->cputype = CPU_PR4450; 787 c->isa_level = MIPS_CPU_ISA_M32R1; 788 break; 789 default: 790 panic("Unknown NXP Core!"); /* REVISIT: die? */ 791 break; 792 } 793 } 794 795 796 static inline void cpu_probe_broadcom(struct cpuinfo_mips *c) 797 { 798 decode_configs(c); 799 switch (c->processor_id & 0xff00) { 800 case PRID_IMP_BCM3302: 801 c->cputype = CPU_BCM3302; 802 break; 803 case PRID_IMP_BCM4710: 804 c->cputype = CPU_BCM4710; 805 break; 806 default: 807 c->cputype = CPU_UNKNOWN; 808 break; 809 } 810 } 811 812 const char *__cpu_name[NR_CPUS]; 813 814 /* 815 * Name a CPU 816 */ 817 static __cpuinit const char *cpu_to_name(struct cpuinfo_mips *c) 818 { 819 const char *name = NULL; 820 821 switch (c->cputype) { 822 case CPU_UNKNOWN: name = "unknown"; break; 823 case CPU_R2000: name = "R2000"; break; 824 case CPU_R3000: name = "R3000"; break; 825 case CPU_R3000A: name = "R3000A"; break; 826 case CPU_R3041: name = "R3041"; break; 827 case CPU_R3051: name = "R3051"; break; 828 case CPU_R3052: name = "R3052"; break; 829 case CPU_R3081: name = "R3081"; break; 830 case CPU_R3081E: name = "R3081E"; break; 831 case CPU_R4000PC: name = "R4000PC"; break; 832 case CPU_R4000SC: name = "R4000SC"; break; 833 case CPU_R4000MC: name = "R4000MC"; break; 834 case CPU_R4200: name = "R4200"; break; 835 case CPU_R4400PC: name = "R4400PC"; break; 836 case CPU_R4400SC: name = "R4400SC"; break; 837 case CPU_R4400MC: name = "R4400MC"; break; 838 case CPU_R4600: name = "R4600"; break; 839 case CPU_R6000: name = "R6000"; break; 840 case CPU_R6000A: name = "R6000A"; break; 841 case CPU_R8000: name = "R8000"; break; 842 case CPU_R10000: name = "R10000"; break; 843 case CPU_R12000: name = "R12000"; break; 844 case CPU_R14000: name = "R14000"; break; 845 case CPU_R4300: name = "R4300"; break; 846 case CPU_R4650: name = "R4650"; break; 847 case CPU_R4700: name = "R4700"; break; 848 case CPU_R5000: name = "R5000"; break; 849 case CPU_R5000A: name = "R5000A"; break; 850 case CPU_R4640: name = "R4640"; break; 851 case CPU_NEVADA: name = "Nevada"; break; 852 case CPU_RM7000: name = "RM7000"; break; 853 case CPU_RM9000: name = "RM9000"; break; 854 case CPU_R5432: name = "R5432"; break; 855 case CPU_4KC: name = "MIPS 4Kc"; break; 856 case CPU_5KC: name = "MIPS 5Kc"; break; 857 case CPU_R4310: name = "R4310"; break; 858 case CPU_SB1: name = "SiByte SB1"; break; 859 case CPU_SB1A: name = "SiByte SB1A"; break; 860 case CPU_TX3912: name = "TX3912"; break; 861 case CPU_TX3922: name = "TX3922"; break; 862 case CPU_TX3927: name = "TX3927"; break; 863 case CPU_AU1000: name = "Au1000"; break; 864 case CPU_AU1500: name = "Au1500"; break; 865 case CPU_AU1100: name = "Au1100"; break; 866 case CPU_AU1550: name = "Au1550"; break; 867 case CPU_AU1200: name = "Au1200"; break; 868 case CPU_AU1210: name = "Au1210"; break; 869 case CPU_AU1250: name = "Au1250"; break; 870 case CPU_4KEC: name = "MIPS 4KEc"; break; 871 case CPU_4KSC: name = "MIPS 4KSc"; break; 872 case CPU_VR41XX: name = "NEC Vr41xx"; break; 873 case CPU_R5500: name = "R5500"; break; 874 case CPU_TX49XX: name = "TX49xx"; break; 875 case CPU_20KC: name = "MIPS 20Kc"; break; 876 case CPU_24K: name = "MIPS 24K"; break; 877 case CPU_25KF: name = "MIPS 25Kf"; break; 878 case CPU_34K: name = "MIPS 34K"; break; 879 case CPU_1004K: name = "MIPS 1004K"; break; 880 case CPU_74K: name = "MIPS 74K"; break; 881 case CPU_VR4111: name = "NEC VR4111"; break; 882 case CPU_VR4121: name = "NEC VR4121"; break; 883 case CPU_VR4122: name = "NEC VR4122"; break; 884 case CPU_VR4131: name = "NEC VR4131"; break; 885 case CPU_VR4133: name = "NEC VR4133"; break; 886 case CPU_VR4181: name = "NEC VR4181"; break; 887 case CPU_VR4181A: name = "NEC VR4181A"; break; 888 case CPU_SR71000: name = "Sandcraft SR71000"; break; 889 case CPU_BCM3302: name = "Broadcom BCM3302"; break; 890 case CPU_BCM4710: name = "Broadcom BCM4710"; break; 891 case CPU_PR4450: name = "Philips PR4450"; break; 892 case CPU_LOONGSON2: name = "ICT Loongson-2"; break; 893 default: 894 BUG(); 895 } 896 897 return name; 898 } 899 900 __cpuinit void cpu_probe(void) 901 { 902 struct cpuinfo_mips *c = ¤t_cpu_data; 903 unsigned int cpu = smp_processor_id(); 904 905 c->processor_id = PRID_IMP_UNKNOWN; 906 c->fpu_id = FPIR_IMP_NONE; 907 c->cputype = CPU_UNKNOWN; 908 909 c->processor_id = read_c0_prid(); 910 switch (c->processor_id & 0xff0000) { 911 case PRID_COMP_LEGACY: 912 cpu_probe_legacy(c); 913 break; 914 case PRID_COMP_MIPS: 915 cpu_probe_mips(c); 916 break; 917 case PRID_COMP_ALCHEMY: 918 cpu_probe_alchemy(c); 919 break; 920 case PRID_COMP_SIBYTE: 921 cpu_probe_sibyte(c); 922 break; 923 case PRID_COMP_BROADCOM: 924 cpu_probe_broadcom(c); 925 break; 926 case PRID_COMP_SANDCRAFT: 927 cpu_probe_sandcraft(c); 928 break; 929 case PRID_COMP_NXP: 930 cpu_probe_nxp(c); 931 break; 932 default: 933 c->cputype = CPU_UNKNOWN; 934 } 935 936 /* 937 * Platform code can force the cpu type to optimize code 938 * generation. In that case be sure the cpu type is correctly 939 * manually setup otherwise it could trigger some nasty bugs. 940 */ 941 BUG_ON(current_cpu_type() != c->cputype); 942 943 if (c->options & MIPS_CPU_FPU) { 944 c->fpu_id = cpu_get_fpu_id(); 945 946 if (c->isa_level == MIPS_CPU_ISA_M32R1 || 947 c->isa_level == MIPS_CPU_ISA_M32R2 || 948 c->isa_level == MIPS_CPU_ISA_M64R1 || 949 c->isa_level == MIPS_CPU_ISA_M64R2) { 950 if (c->fpu_id & MIPS_FPIR_3D) 951 c->ases |= MIPS_ASE_MIPS3D; 952 } 953 } 954 955 __cpu_name[cpu] = cpu_to_name(c); 956 957 if (cpu_has_mips_r2) 958 c->srsets = ((read_c0_srsctl() >> 26) & 0x0f) + 1; 959 else 960 c->srsets = 1; 961 } 962 963 __cpuinit void cpu_report(void) 964 { 965 struct cpuinfo_mips *c = ¤t_cpu_data; 966 967 printk(KERN_INFO "CPU revision is: %08x (%s)\n", 968 c->processor_id, cpu_name_string()); 969 if (c->options & MIPS_CPU_FPU) 970 printk(KERN_INFO "FPU revision is: %08x\n", c->fpu_id); 971 } 972