1 /* 2 * Processor capabilities determination functions. 3 * 4 * Copyright (C) xxxx the Anonymous 5 * Copyright (C) 1994 - 2006 Ralf Baechle 6 * Copyright (C) 2003, 2004 Maciej W. Rozycki 7 * Copyright (C) 2001, 2004 MIPS Inc. 8 * 9 * This program is free software; you can redistribute it and/or 10 * modify it under the terms of the GNU General Public License 11 * as published by the Free Software Foundation; either version 12 * 2 of the License, or (at your option) any later version. 13 */ 14 #include <linux/init.h> 15 #include <linux/kernel.h> 16 #include <linux/ptrace.h> 17 #include <linux/stddef.h> 18 19 #include <asm/bugs.h> 20 #include <asm/cpu.h> 21 #include <asm/fpu.h> 22 #include <asm/mipsregs.h> 23 #include <asm/system.h> 24 25 /* 26 * Not all of the MIPS CPUs have the "wait" instruction available. Moreover, 27 * the implementation of the "wait" feature differs between CPU families. This 28 * points to the function that implements CPU specific wait. 29 * The wait instruction stops the pipeline and reduces the power consumption of 30 * the CPU very much. 31 */ 32 void (*cpu_wait)(void) = NULL; 33 34 static void r3081_wait(void) 35 { 36 unsigned long cfg = read_c0_conf(); 37 write_c0_conf(cfg | R30XX_CONF_HALT); 38 } 39 40 static void r39xx_wait(void) 41 { 42 local_irq_disable(); 43 if (!need_resched()) 44 write_c0_conf(read_c0_conf() | TX39_CONF_HALT); 45 local_irq_enable(); 46 } 47 48 /* 49 * There is a race when WAIT instruction executed with interrupt 50 * enabled. 51 * But it is implementation-dependent wheter the pipelie restarts when 52 * a non-enabled interrupt is requested. 53 */ 54 static void r4k_wait(void) 55 { 56 __asm__(" .set mips3 \n" 57 " wait \n" 58 " .set mips0 \n"); 59 } 60 61 /* 62 * This variant is preferable as it allows testing need_resched and going to 63 * sleep depending on the outcome atomically. Unfortunately the "It is 64 * implementation-dependent whether the pipeline restarts when a non-enabled 65 * interrupt is requested" restriction in the MIPS32/MIPS64 architecture makes 66 * using this version a gamble. 67 */ 68 static void r4k_wait_irqoff(void) 69 { 70 local_irq_disable(); 71 if (!need_resched()) 72 __asm__(" .set mips3 \n" 73 " wait \n" 74 " .set mips0 \n"); 75 local_irq_enable(); 76 } 77 78 /* The Au1xxx wait is available only if using 32khz counter or 79 * external timer source, but specifically not CP0 Counter. */ 80 int allow_au1k_wait; 81 82 static void au1k_wait(void) 83 { 84 /* using the wait instruction makes CP0 counter unusable */ 85 __asm__(" .set mips3 \n" 86 " cache 0x14, 0(%0) \n" 87 " cache 0x14, 32(%0) \n" 88 " sync \n" 89 " nop \n" 90 " wait \n" 91 " nop \n" 92 " nop \n" 93 " nop \n" 94 " nop \n" 95 " .set mips0 \n" 96 : : "r" (au1k_wait)); 97 } 98 99 static int __initdata nowait = 0; 100 101 static int __init wait_disable(char *s) 102 { 103 nowait = 1; 104 105 return 1; 106 } 107 108 __setup("nowait", wait_disable); 109 110 static inline void check_wait(void) 111 { 112 struct cpuinfo_mips *c = ¤t_cpu_data; 113 114 if (nowait) { 115 printk("Wait instruction disabled.\n"); 116 return; 117 } 118 119 switch (c->cputype) { 120 case CPU_R3081: 121 case CPU_R3081E: 122 cpu_wait = r3081_wait; 123 break; 124 case CPU_TX3927: 125 cpu_wait = r39xx_wait; 126 break; 127 case CPU_R4200: 128 /* case CPU_R4300: */ 129 case CPU_R4600: 130 case CPU_R4640: 131 case CPU_R4650: 132 case CPU_R4700: 133 case CPU_R5000: 134 case CPU_NEVADA: 135 case CPU_RM7000: 136 case CPU_4KC: 137 case CPU_4KEC: 138 case CPU_4KSC: 139 case CPU_5KC: 140 case CPU_25KF: 141 case CPU_PR4450: 142 cpu_wait = r4k_wait; 143 break; 144 145 case CPU_24K: 146 case CPU_34K: 147 cpu_wait = r4k_wait; 148 if (read_c0_config7() & MIPS_CONF7_WII) 149 cpu_wait = r4k_wait_irqoff; 150 break; 151 152 case CPU_74K: 153 cpu_wait = r4k_wait; 154 if ((c->processor_id & 0xff) >= PRID_REV_ENCODE_332(2, 1, 0)) 155 cpu_wait = r4k_wait_irqoff; 156 break; 157 158 case CPU_TX49XX: 159 cpu_wait = r4k_wait_irqoff; 160 break; 161 case CPU_AU1000: 162 case CPU_AU1100: 163 case CPU_AU1500: 164 case CPU_AU1550: 165 case CPU_AU1200: 166 if (allow_au1k_wait) 167 cpu_wait = au1k_wait; 168 break; 169 case CPU_20KC: 170 /* 171 * WAIT on Rev1.0 has E1, E2, E3 and E16. 172 * WAIT on Rev2.0 and Rev3.0 has E16. 173 * Rev3.1 WAIT is nop, why bother 174 */ 175 if ((c->processor_id & 0xff) <= 0x64) 176 break; 177 178 cpu_wait = r4k_wait; 179 break; 180 case CPU_RM9000: 181 if ((c->processor_id & 0x00ff) >= 0x40) 182 cpu_wait = r4k_wait; 183 break; 184 default: 185 break; 186 } 187 } 188 189 void __init check_bugs32(void) 190 { 191 check_wait(); 192 } 193 194 /* 195 * Probe whether cpu has config register by trying to play with 196 * alternate cache bit and see whether it matters. 197 * It's used by cpu_probe to distinguish between R3000A and R3081. 198 */ 199 static inline int cpu_has_confreg(void) 200 { 201 #ifdef CONFIG_CPU_R3000 202 extern unsigned long r3k_cache_size(unsigned long); 203 unsigned long size1, size2; 204 unsigned long cfg = read_c0_conf(); 205 206 size1 = r3k_cache_size(ST0_ISC); 207 write_c0_conf(cfg ^ R30XX_CONF_AC); 208 size2 = r3k_cache_size(ST0_ISC); 209 write_c0_conf(cfg); 210 return size1 != size2; 211 #else 212 return 0; 213 #endif 214 } 215 216 /* 217 * Get the FPU Implementation/Revision. 218 */ 219 static inline unsigned long cpu_get_fpu_id(void) 220 { 221 unsigned long tmp, fpu_id; 222 223 tmp = read_c0_status(); 224 __enable_fpu(); 225 fpu_id = read_32bit_cp1_register(CP1_REVISION); 226 write_c0_status(tmp); 227 return fpu_id; 228 } 229 230 /* 231 * Check the CPU has an FPU the official way. 232 */ 233 static inline int __cpu_has_fpu(void) 234 { 235 return ((cpu_get_fpu_id() & 0xff00) != FPIR_IMP_NONE); 236 } 237 238 #define R4K_OPTS (MIPS_CPU_TLB | MIPS_CPU_4KEX | MIPS_CPU_4K_CACHE \ 239 | MIPS_CPU_COUNTER) 240 241 static inline void cpu_probe_legacy(struct cpuinfo_mips *c) 242 { 243 switch (c->processor_id & 0xff00) { 244 case PRID_IMP_R2000: 245 c->cputype = CPU_R2000; 246 c->isa_level = MIPS_CPU_ISA_I; 247 c->options = MIPS_CPU_TLB | MIPS_CPU_3K_CACHE | 248 MIPS_CPU_NOFPUEX; 249 if (__cpu_has_fpu()) 250 c->options |= MIPS_CPU_FPU; 251 c->tlbsize = 64; 252 break; 253 case PRID_IMP_R3000: 254 if ((c->processor_id & 0xff) == PRID_REV_R3000A) 255 if (cpu_has_confreg()) 256 c->cputype = CPU_R3081E; 257 else 258 c->cputype = CPU_R3000A; 259 else 260 c->cputype = CPU_R3000; 261 c->isa_level = MIPS_CPU_ISA_I; 262 c->options = MIPS_CPU_TLB | MIPS_CPU_3K_CACHE | 263 MIPS_CPU_NOFPUEX; 264 if (__cpu_has_fpu()) 265 c->options |= MIPS_CPU_FPU; 266 c->tlbsize = 64; 267 break; 268 case PRID_IMP_R4000: 269 if (read_c0_config() & CONF_SC) { 270 if ((c->processor_id & 0xff) >= PRID_REV_R4400) 271 c->cputype = CPU_R4400PC; 272 else 273 c->cputype = CPU_R4000PC; 274 } else { 275 if ((c->processor_id & 0xff) >= PRID_REV_R4400) 276 c->cputype = CPU_R4400SC; 277 else 278 c->cputype = CPU_R4000SC; 279 } 280 281 c->isa_level = MIPS_CPU_ISA_III; 282 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR | 283 MIPS_CPU_WATCH | MIPS_CPU_VCE | 284 MIPS_CPU_LLSC; 285 c->tlbsize = 48; 286 break; 287 case PRID_IMP_VR41XX: 288 switch (c->processor_id & 0xf0) { 289 case PRID_REV_VR4111: 290 c->cputype = CPU_VR4111; 291 break; 292 case PRID_REV_VR4121: 293 c->cputype = CPU_VR4121; 294 break; 295 case PRID_REV_VR4122: 296 if ((c->processor_id & 0xf) < 0x3) 297 c->cputype = CPU_VR4122; 298 else 299 c->cputype = CPU_VR4181A; 300 break; 301 case PRID_REV_VR4130: 302 if ((c->processor_id & 0xf) < 0x4) 303 c->cputype = CPU_VR4131; 304 else 305 c->cputype = CPU_VR4133; 306 break; 307 default: 308 printk(KERN_INFO "Unexpected CPU of NEC VR4100 series\n"); 309 c->cputype = CPU_VR41XX; 310 break; 311 } 312 c->isa_level = MIPS_CPU_ISA_III; 313 c->options = R4K_OPTS; 314 c->tlbsize = 32; 315 break; 316 case PRID_IMP_R4300: 317 c->cputype = CPU_R4300; 318 c->isa_level = MIPS_CPU_ISA_III; 319 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR | 320 MIPS_CPU_LLSC; 321 c->tlbsize = 32; 322 break; 323 case PRID_IMP_R4600: 324 c->cputype = CPU_R4600; 325 c->isa_level = MIPS_CPU_ISA_III; 326 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR | 327 MIPS_CPU_LLSC; 328 c->tlbsize = 48; 329 break; 330 #if 0 331 case PRID_IMP_R4650: 332 /* 333 * This processor doesn't have an MMU, so it's not 334 * "real easy" to run Linux on it. It is left purely 335 * for documentation. Commented out because it shares 336 * it's c0_prid id number with the TX3900. 337 */ 338 c->cputype = CPU_R4650; 339 c->isa_level = MIPS_CPU_ISA_III; 340 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_LLSC; 341 c->tlbsize = 48; 342 break; 343 #endif 344 case PRID_IMP_TX39: 345 c->isa_level = MIPS_CPU_ISA_I; 346 c->options = MIPS_CPU_TLB | MIPS_CPU_TX39_CACHE; 347 348 if ((c->processor_id & 0xf0) == (PRID_REV_TX3927 & 0xf0)) { 349 c->cputype = CPU_TX3927; 350 c->tlbsize = 64; 351 } else { 352 switch (c->processor_id & 0xff) { 353 case PRID_REV_TX3912: 354 c->cputype = CPU_TX3912; 355 c->tlbsize = 32; 356 break; 357 case PRID_REV_TX3922: 358 c->cputype = CPU_TX3922; 359 c->tlbsize = 64; 360 break; 361 default: 362 c->cputype = CPU_UNKNOWN; 363 break; 364 } 365 } 366 break; 367 case PRID_IMP_R4700: 368 c->cputype = CPU_R4700; 369 c->isa_level = MIPS_CPU_ISA_III; 370 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR | 371 MIPS_CPU_LLSC; 372 c->tlbsize = 48; 373 break; 374 case PRID_IMP_TX49: 375 c->cputype = CPU_TX49XX; 376 c->isa_level = MIPS_CPU_ISA_III; 377 c->options = R4K_OPTS | MIPS_CPU_LLSC; 378 if (!(c->processor_id & 0x08)) 379 c->options |= MIPS_CPU_FPU | MIPS_CPU_32FPR; 380 c->tlbsize = 48; 381 break; 382 case PRID_IMP_R5000: 383 c->cputype = CPU_R5000; 384 c->isa_level = MIPS_CPU_ISA_IV; 385 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR | 386 MIPS_CPU_LLSC; 387 c->tlbsize = 48; 388 break; 389 case PRID_IMP_R5432: 390 c->cputype = CPU_R5432; 391 c->isa_level = MIPS_CPU_ISA_IV; 392 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR | 393 MIPS_CPU_WATCH | MIPS_CPU_LLSC; 394 c->tlbsize = 48; 395 break; 396 case PRID_IMP_R5500: 397 c->cputype = CPU_R5500; 398 c->isa_level = MIPS_CPU_ISA_IV; 399 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR | 400 MIPS_CPU_WATCH | MIPS_CPU_LLSC; 401 c->tlbsize = 48; 402 break; 403 case PRID_IMP_NEVADA: 404 c->cputype = CPU_NEVADA; 405 c->isa_level = MIPS_CPU_ISA_IV; 406 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR | 407 MIPS_CPU_DIVEC | MIPS_CPU_LLSC; 408 c->tlbsize = 48; 409 break; 410 case PRID_IMP_R6000: 411 c->cputype = CPU_R6000; 412 c->isa_level = MIPS_CPU_ISA_II; 413 c->options = MIPS_CPU_TLB | MIPS_CPU_FPU | 414 MIPS_CPU_LLSC; 415 c->tlbsize = 32; 416 break; 417 case PRID_IMP_R6000A: 418 c->cputype = CPU_R6000A; 419 c->isa_level = MIPS_CPU_ISA_II; 420 c->options = MIPS_CPU_TLB | MIPS_CPU_FPU | 421 MIPS_CPU_LLSC; 422 c->tlbsize = 32; 423 break; 424 case PRID_IMP_RM7000: 425 c->cputype = CPU_RM7000; 426 c->isa_level = MIPS_CPU_ISA_IV; 427 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR | 428 MIPS_CPU_LLSC; 429 /* 430 * Undocumented RM7000: Bit 29 in the info register of 431 * the RM7000 v2.0 indicates if the TLB has 48 or 64 432 * entries. 433 * 434 * 29 1 => 64 entry JTLB 435 * 0 => 48 entry JTLB 436 */ 437 c->tlbsize = (read_c0_info() & (1 << 29)) ? 64 : 48; 438 break; 439 case PRID_IMP_RM9000: 440 c->cputype = CPU_RM9000; 441 c->isa_level = MIPS_CPU_ISA_IV; 442 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR | 443 MIPS_CPU_LLSC; 444 /* 445 * Bit 29 in the info register of the RM9000 446 * indicates if the TLB has 48 or 64 entries. 447 * 448 * 29 1 => 64 entry JTLB 449 * 0 => 48 entry JTLB 450 */ 451 c->tlbsize = (read_c0_info() & (1 << 29)) ? 64 : 48; 452 break; 453 case PRID_IMP_R8000: 454 c->cputype = CPU_R8000; 455 c->isa_level = MIPS_CPU_ISA_IV; 456 c->options = MIPS_CPU_TLB | MIPS_CPU_4KEX | 457 MIPS_CPU_FPU | MIPS_CPU_32FPR | 458 MIPS_CPU_LLSC; 459 c->tlbsize = 384; /* has weird TLB: 3-way x 128 */ 460 break; 461 case PRID_IMP_R10000: 462 c->cputype = CPU_R10000; 463 c->isa_level = MIPS_CPU_ISA_IV; 464 c->options = MIPS_CPU_TLB | MIPS_CPU_4K_CACHE | MIPS_CPU_4KEX | 465 MIPS_CPU_FPU | MIPS_CPU_32FPR | 466 MIPS_CPU_COUNTER | MIPS_CPU_WATCH | 467 MIPS_CPU_LLSC; 468 c->tlbsize = 64; 469 break; 470 case PRID_IMP_R12000: 471 c->cputype = CPU_R12000; 472 c->isa_level = MIPS_CPU_ISA_IV; 473 c->options = MIPS_CPU_TLB | MIPS_CPU_4K_CACHE | MIPS_CPU_4KEX | 474 MIPS_CPU_FPU | MIPS_CPU_32FPR | 475 MIPS_CPU_COUNTER | MIPS_CPU_WATCH | 476 MIPS_CPU_LLSC; 477 c->tlbsize = 64; 478 break; 479 case PRID_IMP_R14000: 480 c->cputype = CPU_R14000; 481 c->isa_level = MIPS_CPU_ISA_IV; 482 c->options = MIPS_CPU_TLB | MIPS_CPU_4K_CACHE | MIPS_CPU_4KEX | 483 MIPS_CPU_FPU | MIPS_CPU_32FPR | 484 MIPS_CPU_COUNTER | MIPS_CPU_WATCH | 485 MIPS_CPU_LLSC; 486 c->tlbsize = 64; 487 break; 488 } 489 } 490 491 static char unknown_isa[] __initdata = KERN_ERR \ 492 "Unsupported ISA type, c0.config0: %d."; 493 494 static inline unsigned int decode_config0(struct cpuinfo_mips *c) 495 { 496 unsigned int config0; 497 int isa; 498 499 config0 = read_c0_config(); 500 501 if (((config0 & MIPS_CONF_MT) >> 7) == 1) 502 c->options |= MIPS_CPU_TLB; 503 isa = (config0 & MIPS_CONF_AT) >> 13; 504 switch (isa) { 505 case 0: 506 switch ((config0 & MIPS_CONF_AR) >> 10) { 507 case 0: 508 c->isa_level = MIPS_CPU_ISA_M32R1; 509 break; 510 case 1: 511 c->isa_level = MIPS_CPU_ISA_M32R2; 512 break; 513 default: 514 goto unknown; 515 } 516 break; 517 case 2: 518 switch ((config0 & MIPS_CONF_AR) >> 10) { 519 case 0: 520 c->isa_level = MIPS_CPU_ISA_M64R1; 521 break; 522 case 1: 523 c->isa_level = MIPS_CPU_ISA_M64R2; 524 break; 525 default: 526 goto unknown; 527 } 528 break; 529 default: 530 goto unknown; 531 } 532 533 return config0 & MIPS_CONF_M; 534 535 unknown: 536 panic(unknown_isa, config0); 537 } 538 539 static inline unsigned int decode_config1(struct cpuinfo_mips *c) 540 { 541 unsigned int config1; 542 543 config1 = read_c0_config1(); 544 545 if (config1 & MIPS_CONF1_MD) 546 c->ases |= MIPS_ASE_MDMX; 547 if (config1 & MIPS_CONF1_WR) 548 c->options |= MIPS_CPU_WATCH; 549 if (config1 & MIPS_CONF1_CA) 550 c->ases |= MIPS_ASE_MIPS16; 551 if (config1 & MIPS_CONF1_EP) 552 c->options |= MIPS_CPU_EJTAG; 553 if (config1 & MIPS_CONF1_FP) { 554 c->options |= MIPS_CPU_FPU; 555 c->options |= MIPS_CPU_32FPR; 556 } 557 if (cpu_has_tlb) 558 c->tlbsize = ((config1 & MIPS_CONF1_TLBS) >> 25) + 1; 559 560 return config1 & MIPS_CONF_M; 561 } 562 563 static inline unsigned int decode_config2(struct cpuinfo_mips *c) 564 { 565 unsigned int config2; 566 567 config2 = read_c0_config2(); 568 569 if (config2 & MIPS_CONF2_SL) 570 c->scache.flags &= ~MIPS_CACHE_NOT_PRESENT; 571 572 return config2 & MIPS_CONF_M; 573 } 574 575 static inline unsigned int decode_config3(struct cpuinfo_mips *c) 576 { 577 unsigned int config3; 578 579 config3 = read_c0_config3(); 580 581 if (config3 & MIPS_CONF3_SM) 582 c->ases |= MIPS_ASE_SMARTMIPS; 583 if (config3 & MIPS_CONF3_DSP) 584 c->ases |= MIPS_ASE_DSP; 585 if (config3 & MIPS_CONF3_VINT) 586 c->options |= MIPS_CPU_VINT; 587 if (config3 & MIPS_CONF3_VEIC) 588 c->options |= MIPS_CPU_VEIC; 589 if (config3 & MIPS_CONF3_MT) 590 c->ases |= MIPS_ASE_MIPSMT; 591 592 return config3 & MIPS_CONF_M; 593 } 594 595 static void __init decode_configs(struct cpuinfo_mips *c) 596 { 597 /* MIPS32 or MIPS64 compliant CPU. */ 598 c->options = MIPS_CPU_4KEX | MIPS_CPU_4K_CACHE | MIPS_CPU_COUNTER | 599 MIPS_CPU_DIVEC | MIPS_CPU_LLSC | MIPS_CPU_MCHECK; 600 601 c->scache.flags = MIPS_CACHE_NOT_PRESENT; 602 603 /* Read Config registers. */ 604 if (!decode_config0(c)) 605 return; /* actually worth a panic() */ 606 if (!decode_config1(c)) 607 return; 608 if (!decode_config2(c)) 609 return; 610 if (!decode_config3(c)) 611 return; 612 } 613 614 static inline void cpu_probe_mips(struct cpuinfo_mips *c) 615 { 616 decode_configs(c); 617 switch (c->processor_id & 0xff00) { 618 case PRID_IMP_4KC: 619 c->cputype = CPU_4KC; 620 break; 621 case PRID_IMP_4KEC: 622 c->cputype = CPU_4KEC; 623 break; 624 case PRID_IMP_4KECR2: 625 c->cputype = CPU_4KEC; 626 break; 627 case PRID_IMP_4KSC: 628 case PRID_IMP_4KSD: 629 c->cputype = CPU_4KSC; 630 break; 631 case PRID_IMP_5KC: 632 c->cputype = CPU_5KC; 633 break; 634 case PRID_IMP_20KC: 635 c->cputype = CPU_20KC; 636 break; 637 case PRID_IMP_24K: 638 case PRID_IMP_24KE: 639 c->cputype = CPU_24K; 640 break; 641 case PRID_IMP_25KF: 642 c->cputype = CPU_25KF; 643 break; 644 case PRID_IMP_34K: 645 c->cputype = CPU_34K; 646 break; 647 case PRID_IMP_74K: 648 c->cputype = CPU_74K; 649 break; 650 } 651 } 652 653 static inline void cpu_probe_alchemy(struct cpuinfo_mips *c) 654 { 655 decode_configs(c); 656 switch (c->processor_id & 0xff00) { 657 case PRID_IMP_AU1_REV1: 658 case PRID_IMP_AU1_REV2: 659 switch ((c->processor_id >> 24) & 0xff) { 660 case 0: 661 c->cputype = CPU_AU1000; 662 break; 663 case 1: 664 c->cputype = CPU_AU1500; 665 break; 666 case 2: 667 c->cputype = CPU_AU1100; 668 break; 669 case 3: 670 c->cputype = CPU_AU1550; 671 break; 672 case 4: 673 c->cputype = CPU_AU1200; 674 break; 675 default: 676 panic("Unknown Au Core!"); 677 break; 678 } 679 break; 680 } 681 } 682 683 static inline void cpu_probe_sibyte(struct cpuinfo_mips *c) 684 { 685 decode_configs(c); 686 687 /* 688 * For historical reasons the SB1 comes with it's own variant of 689 * cache code which eventually will be folded into c-r4k.c. Until 690 * then we pretend it's got it's own cache architecture. 691 */ 692 c->options &= ~MIPS_CPU_4K_CACHE; 693 c->options |= MIPS_CPU_SB1_CACHE; 694 695 switch (c->processor_id & 0xff00) { 696 case PRID_IMP_SB1: 697 c->cputype = CPU_SB1; 698 /* FPU in pass1 is known to have issues. */ 699 if ((c->processor_id & 0xff) < 0x02) 700 c->options &= ~(MIPS_CPU_FPU | MIPS_CPU_32FPR); 701 break; 702 case PRID_IMP_SB1A: 703 c->cputype = CPU_SB1A; 704 break; 705 } 706 } 707 708 static inline void cpu_probe_sandcraft(struct cpuinfo_mips *c) 709 { 710 decode_configs(c); 711 switch (c->processor_id & 0xff00) { 712 case PRID_IMP_SR71000: 713 c->cputype = CPU_SR71000; 714 c->scache.ways = 8; 715 c->tlbsize = 64; 716 break; 717 } 718 } 719 720 static inline void cpu_probe_philips(struct cpuinfo_mips *c) 721 { 722 decode_configs(c); 723 switch (c->processor_id & 0xff00) { 724 case PRID_IMP_PR4450: 725 c->cputype = CPU_PR4450; 726 c->isa_level = MIPS_CPU_ISA_M32R1; 727 break; 728 default: 729 panic("Unknown Philips Core!"); /* REVISIT: die? */ 730 break; 731 } 732 } 733 734 735 __init void cpu_probe(void) 736 { 737 struct cpuinfo_mips *c = ¤t_cpu_data; 738 739 c->processor_id = PRID_IMP_UNKNOWN; 740 c->fpu_id = FPIR_IMP_NONE; 741 c->cputype = CPU_UNKNOWN; 742 743 c->processor_id = read_c0_prid(); 744 switch (c->processor_id & 0xff0000) { 745 case PRID_COMP_LEGACY: 746 cpu_probe_legacy(c); 747 break; 748 case PRID_COMP_MIPS: 749 cpu_probe_mips(c); 750 break; 751 case PRID_COMP_ALCHEMY: 752 cpu_probe_alchemy(c); 753 break; 754 case PRID_COMP_SIBYTE: 755 cpu_probe_sibyte(c); 756 break; 757 case PRID_COMP_SANDCRAFT: 758 cpu_probe_sandcraft(c); 759 break; 760 case PRID_COMP_PHILIPS: 761 cpu_probe_philips(c); 762 break; 763 default: 764 c->cputype = CPU_UNKNOWN; 765 } 766 if (c->options & MIPS_CPU_FPU) { 767 c->fpu_id = cpu_get_fpu_id(); 768 769 if (c->isa_level == MIPS_CPU_ISA_M32R1 || 770 c->isa_level == MIPS_CPU_ISA_M32R2 || 771 c->isa_level == MIPS_CPU_ISA_M64R1 || 772 c->isa_level == MIPS_CPU_ISA_M64R2) { 773 if (c->fpu_id & MIPS_FPIR_3D) 774 c->ases |= MIPS_ASE_MIPS3D; 775 } 776 } 777 } 778 779 __init void cpu_report(void) 780 { 781 struct cpuinfo_mips *c = ¤t_cpu_data; 782 783 printk("CPU revision is: %08x\n", c->processor_id); 784 if (c->options & MIPS_CPU_FPU) 785 printk("FPU revision is: %08x\n", c->fpu_id); 786 } 787