1 /* 2 * Processor capabilities determination functions. 3 * 4 * Copyright (C) xxxx the Anonymous 5 * Copyright (C) 1994 - 2006 Ralf Baechle 6 * Copyright (C) 2003, 2004 Maciej W. Rozycki 7 * Copyright (C) 2001, 2004 MIPS Inc. 8 * 9 * This program is free software; you can redistribute it and/or 10 * modify it under the terms of the GNU General Public License 11 * as published by the Free Software Foundation; either version 12 * 2 of the License, or (at your option) any later version. 13 */ 14 #include <linux/init.h> 15 #include <linux/kernel.h> 16 #include <linux/ptrace.h> 17 #include <linux/stddef.h> 18 19 #include <asm/bugs.h> 20 #include <asm/cpu.h> 21 #include <asm/fpu.h> 22 #include <asm/mipsregs.h> 23 #include <asm/system.h> 24 #include <asm/watch.h> 25 26 /* 27 * Not all of the MIPS CPUs have the "wait" instruction available. Moreover, 28 * the implementation of the "wait" feature differs between CPU families. This 29 * points to the function that implements CPU specific wait. 30 * The wait instruction stops the pipeline and reduces the power consumption of 31 * the CPU very much. 32 */ 33 void (*cpu_wait)(void) = NULL; 34 35 static void r3081_wait(void) 36 { 37 unsigned long cfg = read_c0_conf(); 38 write_c0_conf(cfg | R30XX_CONF_HALT); 39 } 40 41 static void r39xx_wait(void) 42 { 43 local_irq_disable(); 44 if (!need_resched()) 45 write_c0_conf(read_c0_conf() | TX39_CONF_HALT); 46 local_irq_enable(); 47 } 48 49 extern void r4k_wait(void); 50 51 /* 52 * This variant is preferable as it allows testing need_resched and going to 53 * sleep depending on the outcome atomically. Unfortunately the "It is 54 * implementation-dependent whether the pipeline restarts when a non-enabled 55 * interrupt is requested" restriction in the MIPS32/MIPS64 architecture makes 56 * using this version a gamble. 57 */ 58 void r4k_wait_irqoff(void) 59 { 60 local_irq_disable(); 61 if (!need_resched()) 62 __asm__(" .set push \n" 63 " .set mips3 \n" 64 " wait \n" 65 " .set pop \n"); 66 local_irq_enable(); 67 __asm__(" .globl __pastwait \n" 68 "__pastwait: \n"); 69 return; 70 } 71 72 /* 73 * The RM7000 variant has to handle erratum 38. The workaround is to not 74 * have any pending stores when the WAIT instruction is executed. 75 */ 76 static void rm7k_wait_irqoff(void) 77 { 78 local_irq_disable(); 79 if (!need_resched()) 80 __asm__( 81 " .set push \n" 82 " .set mips3 \n" 83 " .set noat \n" 84 " mfc0 $1, $12 \n" 85 " sync \n" 86 " mtc0 $1, $12 # stalls until W stage \n" 87 " wait \n" 88 " mtc0 $1, $12 # stalls until W stage \n" 89 " .set pop \n"); 90 local_irq_enable(); 91 } 92 93 /* The Au1xxx wait is available only if using 32khz counter or 94 * external timer source, but specifically not CP0 Counter. */ 95 int allow_au1k_wait; 96 97 static void au1k_wait(void) 98 { 99 if (!allow_au1k_wait) 100 return; 101 102 /* using the wait instruction makes CP0 counter unusable */ 103 __asm__(" .set mips3 \n" 104 " cache 0x14, 0(%0) \n" 105 " cache 0x14, 32(%0) \n" 106 " sync \n" 107 " nop \n" 108 " wait \n" 109 " nop \n" 110 " nop \n" 111 " nop \n" 112 " nop \n" 113 " .set mips0 \n" 114 : : "r" (au1k_wait)); 115 } 116 117 static int __initdata nowait = 0; 118 119 static int __init wait_disable(char *s) 120 { 121 nowait = 1; 122 123 return 1; 124 } 125 126 __setup("nowait", wait_disable); 127 128 void __init check_wait(void) 129 { 130 struct cpuinfo_mips *c = ¤t_cpu_data; 131 132 if (nowait) { 133 printk("Wait instruction disabled.\n"); 134 return; 135 } 136 137 switch (c->cputype) { 138 case CPU_R3081: 139 case CPU_R3081E: 140 cpu_wait = r3081_wait; 141 break; 142 case CPU_TX3927: 143 cpu_wait = r39xx_wait; 144 break; 145 case CPU_R4200: 146 /* case CPU_R4300: */ 147 case CPU_R4600: 148 case CPU_R4640: 149 case CPU_R4650: 150 case CPU_R4700: 151 case CPU_R5000: 152 case CPU_NEVADA: 153 case CPU_4KC: 154 case CPU_4KEC: 155 case CPU_4KSC: 156 case CPU_5KC: 157 case CPU_25KF: 158 case CPU_PR4450: 159 case CPU_BCM3302: 160 case CPU_CAVIUM_OCTEON: 161 cpu_wait = r4k_wait; 162 break; 163 164 case CPU_RM7000: 165 cpu_wait = rm7k_wait_irqoff; 166 break; 167 168 case CPU_24K: 169 case CPU_34K: 170 case CPU_1004K: 171 cpu_wait = r4k_wait; 172 if (read_c0_config7() & MIPS_CONF7_WII) 173 cpu_wait = r4k_wait_irqoff; 174 break; 175 176 case CPU_74K: 177 cpu_wait = r4k_wait; 178 if ((c->processor_id & 0xff) >= PRID_REV_ENCODE_332(2, 1, 0)) 179 cpu_wait = r4k_wait_irqoff; 180 break; 181 182 case CPU_TX49XX: 183 cpu_wait = r4k_wait_irqoff; 184 break; 185 case CPU_AU1000: 186 case CPU_AU1100: 187 case CPU_AU1500: 188 case CPU_AU1550: 189 case CPU_AU1200: 190 case CPU_AU1210: 191 case CPU_AU1250: 192 cpu_wait = au1k_wait; 193 break; 194 case CPU_20KC: 195 /* 196 * WAIT on Rev1.0 has E1, E2, E3 and E16. 197 * WAIT on Rev2.0 and Rev3.0 has E16. 198 * Rev3.1 WAIT is nop, why bother 199 */ 200 if ((c->processor_id & 0xff) <= 0x64) 201 break; 202 203 /* 204 * Another rev is incremeting c0_count at a reduced clock 205 * rate while in WAIT mode. So we basically have the choice 206 * between using the cp0 timer as clocksource or avoiding 207 * the WAIT instruction. Until more details are known, 208 * disable the use of WAIT for 20Kc entirely. 209 cpu_wait = r4k_wait; 210 */ 211 break; 212 case CPU_RM9000: 213 if ((c->processor_id & 0x00ff) >= 0x40) 214 cpu_wait = r4k_wait; 215 break; 216 default: 217 break; 218 } 219 } 220 221 static inline void check_errata(void) 222 { 223 struct cpuinfo_mips *c = ¤t_cpu_data; 224 225 switch (c->cputype) { 226 case CPU_34K: 227 /* 228 * Erratum "RPS May Cause Incorrect Instruction Execution" 229 * This code only handles VPE0, any SMP/SMTC/RTOS code 230 * making use of VPE1 will be responsable for that VPE. 231 */ 232 if ((c->processor_id & PRID_REV_MASK) <= PRID_REV_34K_V1_0_2) 233 write_c0_config7(read_c0_config7() | MIPS_CONF7_RPS); 234 break; 235 default: 236 break; 237 } 238 } 239 240 void __init check_bugs32(void) 241 { 242 check_errata(); 243 } 244 245 /* 246 * Probe whether cpu has config register by trying to play with 247 * alternate cache bit and see whether it matters. 248 * It's used by cpu_probe to distinguish between R3000A and R3081. 249 */ 250 static inline int cpu_has_confreg(void) 251 { 252 #ifdef CONFIG_CPU_R3000 253 extern unsigned long r3k_cache_size(unsigned long); 254 unsigned long size1, size2; 255 unsigned long cfg = read_c0_conf(); 256 257 size1 = r3k_cache_size(ST0_ISC); 258 write_c0_conf(cfg ^ R30XX_CONF_AC); 259 size2 = r3k_cache_size(ST0_ISC); 260 write_c0_conf(cfg); 261 return size1 != size2; 262 #else 263 return 0; 264 #endif 265 } 266 267 /* 268 * Get the FPU Implementation/Revision. 269 */ 270 static inline unsigned long cpu_get_fpu_id(void) 271 { 272 unsigned long tmp, fpu_id; 273 274 tmp = read_c0_status(); 275 __enable_fpu(); 276 fpu_id = read_32bit_cp1_register(CP1_REVISION); 277 write_c0_status(tmp); 278 return fpu_id; 279 } 280 281 /* 282 * Check the CPU has an FPU the official way. 283 */ 284 static inline int __cpu_has_fpu(void) 285 { 286 return ((cpu_get_fpu_id() & 0xff00) != FPIR_IMP_NONE); 287 } 288 289 #define R4K_OPTS (MIPS_CPU_TLB | MIPS_CPU_4KEX | MIPS_CPU_4K_CACHE \ 290 | MIPS_CPU_COUNTER) 291 292 static inline void cpu_probe_legacy(struct cpuinfo_mips *c, unsigned int cpu) 293 { 294 switch (c->processor_id & 0xff00) { 295 case PRID_IMP_R2000: 296 c->cputype = CPU_R2000; 297 __cpu_name[cpu] = "R2000"; 298 c->isa_level = MIPS_CPU_ISA_I; 299 c->options = MIPS_CPU_TLB | MIPS_CPU_3K_CACHE | 300 MIPS_CPU_NOFPUEX; 301 if (__cpu_has_fpu()) 302 c->options |= MIPS_CPU_FPU; 303 c->tlbsize = 64; 304 break; 305 case PRID_IMP_R3000: 306 if ((c->processor_id & 0xff) == PRID_REV_R3000A) { 307 if (cpu_has_confreg()) { 308 c->cputype = CPU_R3081E; 309 __cpu_name[cpu] = "R3081"; 310 } else { 311 c->cputype = CPU_R3000A; 312 __cpu_name[cpu] = "R3000A"; 313 } 314 break; 315 } else { 316 c->cputype = CPU_R3000; 317 __cpu_name[cpu] = "R3000"; 318 } 319 c->isa_level = MIPS_CPU_ISA_I; 320 c->options = MIPS_CPU_TLB | MIPS_CPU_3K_CACHE | 321 MIPS_CPU_NOFPUEX; 322 if (__cpu_has_fpu()) 323 c->options |= MIPS_CPU_FPU; 324 c->tlbsize = 64; 325 break; 326 case PRID_IMP_R4000: 327 if (read_c0_config() & CONF_SC) { 328 if ((c->processor_id & 0xff) >= PRID_REV_R4400) { 329 c->cputype = CPU_R4400PC; 330 __cpu_name[cpu] = "R4400PC"; 331 } else { 332 c->cputype = CPU_R4000PC; 333 __cpu_name[cpu] = "R4000PC"; 334 } 335 } else { 336 if ((c->processor_id & 0xff) >= PRID_REV_R4400) { 337 c->cputype = CPU_R4400SC; 338 __cpu_name[cpu] = "R4400SC"; 339 } else { 340 c->cputype = CPU_R4000SC; 341 __cpu_name[cpu] = "R4000SC"; 342 } 343 } 344 345 c->isa_level = MIPS_CPU_ISA_III; 346 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR | 347 MIPS_CPU_WATCH | MIPS_CPU_VCE | 348 MIPS_CPU_LLSC; 349 c->tlbsize = 48; 350 break; 351 case PRID_IMP_VR41XX: 352 switch (c->processor_id & 0xf0) { 353 case PRID_REV_VR4111: 354 c->cputype = CPU_VR4111; 355 __cpu_name[cpu] = "NEC VR4111"; 356 break; 357 case PRID_REV_VR4121: 358 c->cputype = CPU_VR4121; 359 __cpu_name[cpu] = "NEC VR4121"; 360 break; 361 case PRID_REV_VR4122: 362 if ((c->processor_id & 0xf) < 0x3) { 363 c->cputype = CPU_VR4122; 364 __cpu_name[cpu] = "NEC VR4122"; 365 } else { 366 c->cputype = CPU_VR4181A; 367 __cpu_name[cpu] = "NEC VR4181A"; 368 } 369 break; 370 case PRID_REV_VR4130: 371 if ((c->processor_id & 0xf) < 0x4) { 372 c->cputype = CPU_VR4131; 373 __cpu_name[cpu] = "NEC VR4131"; 374 } else { 375 c->cputype = CPU_VR4133; 376 __cpu_name[cpu] = "NEC VR4133"; 377 } 378 break; 379 default: 380 printk(KERN_INFO "Unexpected CPU of NEC VR4100 series\n"); 381 c->cputype = CPU_VR41XX; 382 __cpu_name[cpu] = "NEC Vr41xx"; 383 break; 384 } 385 c->isa_level = MIPS_CPU_ISA_III; 386 c->options = R4K_OPTS; 387 c->tlbsize = 32; 388 break; 389 case PRID_IMP_R4300: 390 c->cputype = CPU_R4300; 391 __cpu_name[cpu] = "R4300"; 392 c->isa_level = MIPS_CPU_ISA_III; 393 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR | 394 MIPS_CPU_LLSC; 395 c->tlbsize = 32; 396 break; 397 case PRID_IMP_R4600: 398 c->cputype = CPU_R4600; 399 __cpu_name[cpu] = "R4600"; 400 c->isa_level = MIPS_CPU_ISA_III; 401 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR | 402 MIPS_CPU_LLSC; 403 c->tlbsize = 48; 404 break; 405 #if 0 406 case PRID_IMP_R4650: 407 /* 408 * This processor doesn't have an MMU, so it's not 409 * "real easy" to run Linux on it. It is left purely 410 * for documentation. Commented out because it shares 411 * it's c0_prid id number with the TX3900. 412 */ 413 c->cputype = CPU_R4650; 414 __cpu_name[cpu] = "R4650"; 415 c->isa_level = MIPS_CPU_ISA_III; 416 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_LLSC; 417 c->tlbsize = 48; 418 break; 419 #endif 420 case PRID_IMP_TX39: 421 c->isa_level = MIPS_CPU_ISA_I; 422 c->options = MIPS_CPU_TLB | MIPS_CPU_TX39_CACHE; 423 424 if ((c->processor_id & 0xf0) == (PRID_REV_TX3927 & 0xf0)) { 425 c->cputype = CPU_TX3927; 426 __cpu_name[cpu] = "TX3927"; 427 c->tlbsize = 64; 428 } else { 429 switch (c->processor_id & 0xff) { 430 case PRID_REV_TX3912: 431 c->cputype = CPU_TX3912; 432 __cpu_name[cpu] = "TX3912"; 433 c->tlbsize = 32; 434 break; 435 case PRID_REV_TX3922: 436 c->cputype = CPU_TX3922; 437 __cpu_name[cpu] = "TX3922"; 438 c->tlbsize = 64; 439 break; 440 } 441 } 442 break; 443 case PRID_IMP_R4700: 444 c->cputype = CPU_R4700; 445 __cpu_name[cpu] = "R4700"; 446 c->isa_level = MIPS_CPU_ISA_III; 447 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR | 448 MIPS_CPU_LLSC; 449 c->tlbsize = 48; 450 break; 451 case PRID_IMP_TX49: 452 c->cputype = CPU_TX49XX; 453 __cpu_name[cpu] = "R49XX"; 454 c->isa_level = MIPS_CPU_ISA_III; 455 c->options = R4K_OPTS | MIPS_CPU_LLSC; 456 if (!(c->processor_id & 0x08)) 457 c->options |= MIPS_CPU_FPU | MIPS_CPU_32FPR; 458 c->tlbsize = 48; 459 break; 460 case PRID_IMP_R5000: 461 c->cputype = CPU_R5000; 462 __cpu_name[cpu] = "R5000"; 463 c->isa_level = MIPS_CPU_ISA_IV; 464 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR | 465 MIPS_CPU_LLSC; 466 c->tlbsize = 48; 467 break; 468 case PRID_IMP_R5432: 469 c->cputype = CPU_R5432; 470 __cpu_name[cpu] = "R5432"; 471 c->isa_level = MIPS_CPU_ISA_IV; 472 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR | 473 MIPS_CPU_WATCH | MIPS_CPU_LLSC; 474 c->tlbsize = 48; 475 break; 476 case PRID_IMP_R5500: 477 c->cputype = CPU_R5500; 478 __cpu_name[cpu] = "R5500"; 479 c->isa_level = MIPS_CPU_ISA_IV; 480 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR | 481 MIPS_CPU_WATCH | MIPS_CPU_LLSC; 482 c->tlbsize = 48; 483 break; 484 case PRID_IMP_NEVADA: 485 c->cputype = CPU_NEVADA; 486 __cpu_name[cpu] = "Nevada"; 487 c->isa_level = MIPS_CPU_ISA_IV; 488 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR | 489 MIPS_CPU_DIVEC | MIPS_CPU_LLSC; 490 c->tlbsize = 48; 491 break; 492 case PRID_IMP_R6000: 493 c->cputype = CPU_R6000; 494 __cpu_name[cpu] = "R6000"; 495 c->isa_level = MIPS_CPU_ISA_II; 496 c->options = MIPS_CPU_TLB | MIPS_CPU_FPU | 497 MIPS_CPU_LLSC; 498 c->tlbsize = 32; 499 break; 500 case PRID_IMP_R6000A: 501 c->cputype = CPU_R6000A; 502 __cpu_name[cpu] = "R6000A"; 503 c->isa_level = MIPS_CPU_ISA_II; 504 c->options = MIPS_CPU_TLB | MIPS_CPU_FPU | 505 MIPS_CPU_LLSC; 506 c->tlbsize = 32; 507 break; 508 case PRID_IMP_RM7000: 509 c->cputype = CPU_RM7000; 510 __cpu_name[cpu] = "RM7000"; 511 c->isa_level = MIPS_CPU_ISA_IV; 512 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR | 513 MIPS_CPU_LLSC; 514 /* 515 * Undocumented RM7000: Bit 29 in the info register of 516 * the RM7000 v2.0 indicates if the TLB has 48 or 64 517 * entries. 518 * 519 * 29 1 => 64 entry JTLB 520 * 0 => 48 entry JTLB 521 */ 522 c->tlbsize = (read_c0_info() & (1 << 29)) ? 64 : 48; 523 break; 524 case PRID_IMP_RM9000: 525 c->cputype = CPU_RM9000; 526 __cpu_name[cpu] = "RM9000"; 527 c->isa_level = MIPS_CPU_ISA_IV; 528 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR | 529 MIPS_CPU_LLSC; 530 /* 531 * Bit 29 in the info register of the RM9000 532 * indicates if the TLB has 48 or 64 entries. 533 * 534 * 29 1 => 64 entry JTLB 535 * 0 => 48 entry JTLB 536 */ 537 c->tlbsize = (read_c0_info() & (1 << 29)) ? 64 : 48; 538 break; 539 case PRID_IMP_R8000: 540 c->cputype = CPU_R8000; 541 __cpu_name[cpu] = "RM8000"; 542 c->isa_level = MIPS_CPU_ISA_IV; 543 c->options = MIPS_CPU_TLB | MIPS_CPU_4KEX | 544 MIPS_CPU_FPU | MIPS_CPU_32FPR | 545 MIPS_CPU_LLSC; 546 c->tlbsize = 384; /* has weird TLB: 3-way x 128 */ 547 break; 548 case PRID_IMP_R10000: 549 c->cputype = CPU_R10000; 550 __cpu_name[cpu] = "R10000"; 551 c->isa_level = MIPS_CPU_ISA_IV; 552 c->options = MIPS_CPU_TLB | MIPS_CPU_4K_CACHE | MIPS_CPU_4KEX | 553 MIPS_CPU_FPU | MIPS_CPU_32FPR | 554 MIPS_CPU_COUNTER | MIPS_CPU_WATCH | 555 MIPS_CPU_LLSC; 556 c->tlbsize = 64; 557 break; 558 case PRID_IMP_R12000: 559 c->cputype = CPU_R12000; 560 __cpu_name[cpu] = "R12000"; 561 c->isa_level = MIPS_CPU_ISA_IV; 562 c->options = MIPS_CPU_TLB | MIPS_CPU_4K_CACHE | MIPS_CPU_4KEX | 563 MIPS_CPU_FPU | MIPS_CPU_32FPR | 564 MIPS_CPU_COUNTER | MIPS_CPU_WATCH | 565 MIPS_CPU_LLSC; 566 c->tlbsize = 64; 567 break; 568 case PRID_IMP_R14000: 569 c->cputype = CPU_R14000; 570 __cpu_name[cpu] = "R14000"; 571 c->isa_level = MIPS_CPU_ISA_IV; 572 c->options = MIPS_CPU_TLB | MIPS_CPU_4K_CACHE | MIPS_CPU_4KEX | 573 MIPS_CPU_FPU | MIPS_CPU_32FPR | 574 MIPS_CPU_COUNTER | MIPS_CPU_WATCH | 575 MIPS_CPU_LLSC; 576 c->tlbsize = 64; 577 break; 578 case PRID_IMP_LOONGSON2: 579 c->cputype = CPU_LOONGSON2; 580 __cpu_name[cpu] = "ICT Loongson-2"; 581 c->isa_level = MIPS_CPU_ISA_III; 582 c->options = R4K_OPTS | 583 MIPS_CPU_FPU | MIPS_CPU_LLSC | 584 MIPS_CPU_32FPR; 585 c->tlbsize = 64; 586 break; 587 } 588 } 589 590 static char unknown_isa[] __cpuinitdata = KERN_ERR \ 591 "Unsupported ISA type, c0.config0: %d."; 592 593 static inline unsigned int decode_config0(struct cpuinfo_mips *c) 594 { 595 unsigned int config0; 596 int isa; 597 598 config0 = read_c0_config(); 599 600 if (((config0 & MIPS_CONF_MT) >> 7) == 1) 601 c->options |= MIPS_CPU_TLB; 602 isa = (config0 & MIPS_CONF_AT) >> 13; 603 switch (isa) { 604 case 0: 605 switch ((config0 & MIPS_CONF_AR) >> 10) { 606 case 0: 607 c->isa_level = MIPS_CPU_ISA_M32R1; 608 break; 609 case 1: 610 c->isa_level = MIPS_CPU_ISA_M32R2; 611 break; 612 default: 613 goto unknown; 614 } 615 break; 616 case 2: 617 switch ((config0 & MIPS_CONF_AR) >> 10) { 618 case 0: 619 c->isa_level = MIPS_CPU_ISA_M64R1; 620 break; 621 case 1: 622 c->isa_level = MIPS_CPU_ISA_M64R2; 623 break; 624 default: 625 goto unknown; 626 } 627 break; 628 default: 629 goto unknown; 630 } 631 632 return config0 & MIPS_CONF_M; 633 634 unknown: 635 panic(unknown_isa, config0); 636 } 637 638 static inline unsigned int decode_config1(struct cpuinfo_mips *c) 639 { 640 unsigned int config1; 641 642 config1 = read_c0_config1(); 643 644 if (config1 & MIPS_CONF1_MD) 645 c->ases |= MIPS_ASE_MDMX; 646 if (config1 & MIPS_CONF1_WR) 647 c->options |= MIPS_CPU_WATCH; 648 if (config1 & MIPS_CONF1_CA) 649 c->ases |= MIPS_ASE_MIPS16; 650 if (config1 & MIPS_CONF1_EP) 651 c->options |= MIPS_CPU_EJTAG; 652 if (config1 & MIPS_CONF1_FP) { 653 c->options |= MIPS_CPU_FPU; 654 c->options |= MIPS_CPU_32FPR; 655 } 656 if (cpu_has_tlb) 657 c->tlbsize = ((config1 & MIPS_CONF1_TLBS) >> 25) + 1; 658 659 return config1 & MIPS_CONF_M; 660 } 661 662 static inline unsigned int decode_config2(struct cpuinfo_mips *c) 663 { 664 unsigned int config2; 665 666 config2 = read_c0_config2(); 667 668 if (config2 & MIPS_CONF2_SL) 669 c->scache.flags &= ~MIPS_CACHE_NOT_PRESENT; 670 671 return config2 & MIPS_CONF_M; 672 } 673 674 static inline unsigned int decode_config3(struct cpuinfo_mips *c) 675 { 676 unsigned int config3; 677 678 config3 = read_c0_config3(); 679 680 if (config3 & MIPS_CONF3_SM) 681 c->ases |= MIPS_ASE_SMARTMIPS; 682 if (config3 & MIPS_CONF3_DSP) 683 c->ases |= MIPS_ASE_DSP; 684 if (config3 & MIPS_CONF3_VINT) 685 c->options |= MIPS_CPU_VINT; 686 if (config3 & MIPS_CONF3_VEIC) 687 c->options |= MIPS_CPU_VEIC; 688 if (config3 & MIPS_CONF3_MT) 689 c->ases |= MIPS_ASE_MIPSMT; 690 if (config3 & MIPS_CONF3_ULRI) 691 c->options |= MIPS_CPU_ULRI; 692 693 return config3 & MIPS_CONF_M; 694 } 695 696 static void __cpuinit decode_configs(struct cpuinfo_mips *c) 697 { 698 int ok; 699 700 /* MIPS32 or MIPS64 compliant CPU. */ 701 c->options = MIPS_CPU_4KEX | MIPS_CPU_4K_CACHE | MIPS_CPU_COUNTER | 702 MIPS_CPU_DIVEC | MIPS_CPU_LLSC | MIPS_CPU_MCHECK; 703 704 c->scache.flags = MIPS_CACHE_NOT_PRESENT; 705 706 ok = decode_config0(c); /* Read Config registers. */ 707 BUG_ON(!ok); /* Arch spec violation! */ 708 if (ok) 709 ok = decode_config1(c); 710 if (ok) 711 ok = decode_config2(c); 712 if (ok) 713 ok = decode_config3(c); 714 715 mips_probe_watch_registers(c); 716 } 717 718 #ifdef CONFIG_CPU_MIPSR2 719 extern void spram_config(void); 720 #else 721 static inline void spram_config(void) {} 722 #endif 723 724 static inline void cpu_probe_mips(struct cpuinfo_mips *c, unsigned int cpu) 725 { 726 decode_configs(c); 727 switch (c->processor_id & 0xff00) { 728 case PRID_IMP_4KC: 729 c->cputype = CPU_4KC; 730 __cpu_name[cpu] = "MIPS 4Kc"; 731 break; 732 case PRID_IMP_4KEC: 733 c->cputype = CPU_4KEC; 734 __cpu_name[cpu] = "MIPS 4KEc"; 735 break; 736 case PRID_IMP_4KECR2: 737 c->cputype = CPU_4KEC; 738 __cpu_name[cpu] = "MIPS 4KEc"; 739 break; 740 case PRID_IMP_4KSC: 741 case PRID_IMP_4KSD: 742 c->cputype = CPU_4KSC; 743 __cpu_name[cpu] = "MIPS 4KSc"; 744 break; 745 case PRID_IMP_5KC: 746 c->cputype = CPU_5KC; 747 __cpu_name[cpu] = "MIPS 5Kc"; 748 break; 749 case PRID_IMP_20KC: 750 c->cputype = CPU_20KC; 751 __cpu_name[cpu] = "MIPS 20Kc"; 752 break; 753 case PRID_IMP_24K: 754 case PRID_IMP_24KE: 755 c->cputype = CPU_24K; 756 __cpu_name[cpu] = "MIPS 24Kc"; 757 break; 758 case PRID_IMP_25KF: 759 c->cputype = CPU_25KF; 760 __cpu_name[cpu] = "MIPS 25Kc"; 761 break; 762 case PRID_IMP_34K: 763 c->cputype = CPU_34K; 764 __cpu_name[cpu] = "MIPS 34Kc"; 765 break; 766 case PRID_IMP_74K: 767 c->cputype = CPU_74K; 768 __cpu_name[cpu] = "MIPS 74Kc"; 769 break; 770 case PRID_IMP_1004K: 771 c->cputype = CPU_1004K; 772 __cpu_name[cpu] = "MIPS 1004Kc"; 773 break; 774 } 775 776 spram_config(); 777 } 778 779 static inline void cpu_probe_alchemy(struct cpuinfo_mips *c, unsigned int cpu) 780 { 781 decode_configs(c); 782 switch (c->processor_id & 0xff00) { 783 case PRID_IMP_AU1_REV1: 784 case PRID_IMP_AU1_REV2: 785 switch ((c->processor_id >> 24) & 0xff) { 786 case 0: 787 c->cputype = CPU_AU1000; 788 __cpu_name[cpu] = "Au1000"; 789 break; 790 case 1: 791 c->cputype = CPU_AU1500; 792 __cpu_name[cpu] = "Au1500"; 793 break; 794 case 2: 795 c->cputype = CPU_AU1100; 796 __cpu_name[cpu] = "Au1100"; 797 break; 798 case 3: 799 c->cputype = CPU_AU1550; 800 __cpu_name[cpu] = "Au1550"; 801 break; 802 case 4: 803 c->cputype = CPU_AU1200; 804 __cpu_name[cpu] = "Au1200"; 805 if ((c->processor_id & 0xff) == 2) { 806 c->cputype = CPU_AU1250; 807 __cpu_name[cpu] = "Au1250"; 808 } 809 break; 810 case 5: 811 c->cputype = CPU_AU1210; 812 __cpu_name[cpu] = "Au1210"; 813 break; 814 default: 815 panic("Unknown Au Core!"); 816 break; 817 } 818 break; 819 } 820 } 821 822 static inline void cpu_probe_sibyte(struct cpuinfo_mips *c, unsigned int cpu) 823 { 824 decode_configs(c); 825 826 switch (c->processor_id & 0xff00) { 827 case PRID_IMP_SB1: 828 c->cputype = CPU_SB1; 829 __cpu_name[cpu] = "SiByte SB1"; 830 /* FPU in pass1 is known to have issues. */ 831 if ((c->processor_id & 0xff) < 0x02) 832 c->options &= ~(MIPS_CPU_FPU | MIPS_CPU_32FPR); 833 break; 834 case PRID_IMP_SB1A: 835 c->cputype = CPU_SB1A; 836 __cpu_name[cpu] = "SiByte SB1A"; 837 break; 838 } 839 } 840 841 static inline void cpu_probe_sandcraft(struct cpuinfo_mips *c, unsigned int cpu) 842 { 843 decode_configs(c); 844 switch (c->processor_id & 0xff00) { 845 case PRID_IMP_SR71000: 846 c->cputype = CPU_SR71000; 847 __cpu_name[cpu] = "Sandcraft SR71000"; 848 c->scache.ways = 8; 849 c->tlbsize = 64; 850 break; 851 } 852 } 853 854 static inline void cpu_probe_nxp(struct cpuinfo_mips *c, unsigned int cpu) 855 { 856 decode_configs(c); 857 switch (c->processor_id & 0xff00) { 858 case PRID_IMP_PR4450: 859 c->cputype = CPU_PR4450; 860 __cpu_name[cpu] = "Philips PR4450"; 861 c->isa_level = MIPS_CPU_ISA_M32R1; 862 break; 863 } 864 } 865 866 static inline void cpu_probe_broadcom(struct cpuinfo_mips *c, unsigned int cpu) 867 { 868 decode_configs(c); 869 switch (c->processor_id & 0xff00) { 870 case PRID_IMP_BCM3302: 871 c->cputype = CPU_BCM3302; 872 __cpu_name[cpu] = "Broadcom BCM3302"; 873 break; 874 case PRID_IMP_BCM4710: 875 c->cputype = CPU_BCM4710; 876 __cpu_name[cpu] = "Broadcom BCM4710"; 877 break; 878 } 879 } 880 881 static inline void cpu_probe_cavium(struct cpuinfo_mips *c, unsigned int cpu) 882 { 883 decode_configs(c); 884 switch (c->processor_id & 0xff00) { 885 case PRID_IMP_CAVIUM_CN38XX: 886 case PRID_IMP_CAVIUM_CN31XX: 887 case PRID_IMP_CAVIUM_CN30XX: 888 case PRID_IMP_CAVIUM_CN58XX: 889 case PRID_IMP_CAVIUM_CN56XX: 890 case PRID_IMP_CAVIUM_CN50XX: 891 case PRID_IMP_CAVIUM_CN52XX: 892 c->cputype = CPU_CAVIUM_OCTEON; 893 __cpu_name[cpu] = "Cavium Octeon"; 894 break; 895 default: 896 printk(KERN_INFO "Unknown Octeon chip!\n"); 897 c->cputype = CPU_UNKNOWN; 898 break; 899 } 900 } 901 902 const char *__cpu_name[NR_CPUS]; 903 904 __cpuinit void cpu_probe(void) 905 { 906 struct cpuinfo_mips *c = ¤t_cpu_data; 907 unsigned int cpu = smp_processor_id(); 908 909 c->processor_id = PRID_IMP_UNKNOWN; 910 c->fpu_id = FPIR_IMP_NONE; 911 c->cputype = CPU_UNKNOWN; 912 913 c->processor_id = read_c0_prid(); 914 switch (c->processor_id & 0xff0000) { 915 case PRID_COMP_LEGACY: 916 cpu_probe_legacy(c, cpu); 917 break; 918 case PRID_COMP_MIPS: 919 cpu_probe_mips(c, cpu); 920 break; 921 case PRID_COMP_ALCHEMY: 922 cpu_probe_alchemy(c, cpu); 923 break; 924 case PRID_COMP_SIBYTE: 925 cpu_probe_sibyte(c, cpu); 926 break; 927 case PRID_COMP_BROADCOM: 928 cpu_probe_broadcom(c, cpu); 929 break; 930 case PRID_COMP_SANDCRAFT: 931 cpu_probe_sandcraft(c, cpu); 932 break; 933 case PRID_COMP_NXP: 934 cpu_probe_nxp(c, cpu); 935 break; 936 case PRID_COMP_CAVIUM: 937 cpu_probe_cavium(c, cpu); 938 break; 939 } 940 941 BUG_ON(!__cpu_name[cpu]); 942 BUG_ON(c->cputype == CPU_UNKNOWN); 943 944 /* 945 * Platform code can force the cpu type to optimize code 946 * generation. In that case be sure the cpu type is correctly 947 * manually setup otherwise it could trigger some nasty bugs. 948 */ 949 BUG_ON(current_cpu_type() != c->cputype); 950 951 if (c->options & MIPS_CPU_FPU) { 952 c->fpu_id = cpu_get_fpu_id(); 953 954 if (c->isa_level == MIPS_CPU_ISA_M32R1 || 955 c->isa_level == MIPS_CPU_ISA_M32R2 || 956 c->isa_level == MIPS_CPU_ISA_M64R1 || 957 c->isa_level == MIPS_CPU_ISA_M64R2) { 958 if (c->fpu_id & MIPS_FPIR_3D) 959 c->ases |= MIPS_ASE_MIPS3D; 960 } 961 } 962 963 if (cpu_has_mips_r2) 964 c->srsets = ((read_c0_srsctl() >> 26) & 0x0f) + 1; 965 else 966 c->srsets = 1; 967 } 968 969 __cpuinit void cpu_report(void) 970 { 971 struct cpuinfo_mips *c = ¤t_cpu_data; 972 973 printk(KERN_INFO "CPU revision is: %08x (%s)\n", 974 c->processor_id, cpu_name_string()); 975 if (c->options & MIPS_CPU_FPU) 976 printk(KERN_INFO "FPU revision is: %08x\n", c->fpu_id); 977 } 978