1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * Processor capabilities determination functions. 4 * 5 * Copyright (C) xxxx the Anonymous 6 * Copyright (C) 1994 - 2006 Ralf Baechle 7 * Copyright (C) 2003, 2004 Maciej W. Rozycki 8 * Copyright (C) 2001, 2004, 2011, 2012 MIPS Technologies, Inc. 9 */ 10 #include <linux/init.h> 11 #include <linux/kernel.h> 12 #include <linux/mmu_context.h> 13 #include <linux/ptrace.h> 14 #include <linux/smp.h> 15 #include <linux/stddef.h> 16 #include <linux/export.h> 17 18 #include <asm/bugs.h> 19 #include <asm/cpu.h> 20 #include <asm/cpu-features.h> 21 #include <asm/cpu-type.h> 22 #include <asm/fpu.h> 23 #include <asm/mipsregs.h> 24 #include <asm/mipsmtregs.h> 25 #include <asm/msa.h> 26 #include <asm/watch.h> 27 #include <asm/elf.h> 28 #include <asm/pgtable-bits.h> 29 #include <asm/spram.h> 30 #include <asm/traps.h> 31 #include <linux/uaccess.h> 32 33 #include "fpu-probe.h" 34 35 #include <asm/mach-loongson64/cpucfg-emul.h> 36 37 /* Hardware capabilities */ 38 unsigned int elf_hwcap __read_mostly; 39 EXPORT_SYMBOL_GPL(elf_hwcap); 40 41 static bool mmid_disabled_quirk; 42 43 static inline unsigned long cpu_get_msa_id(void) 44 { 45 unsigned long status, msa_id; 46 47 status = read_c0_status(); 48 __enable_fpu(FPU_64BIT); 49 enable_msa(); 50 msa_id = read_msa_ir(); 51 disable_msa(); 52 write_c0_status(status); 53 return msa_id; 54 } 55 56 static int mips_dsp_disabled; 57 58 static int __init dsp_disable(char *s) 59 { 60 cpu_data[0].ases &= ~(MIPS_ASE_DSP | MIPS_ASE_DSP2P); 61 mips_dsp_disabled = 1; 62 63 return 1; 64 } 65 66 __setup("nodsp", dsp_disable); 67 68 static int mips_htw_disabled; 69 70 static int __init htw_disable(char *s) 71 { 72 mips_htw_disabled = 1; 73 cpu_data[0].options &= ~MIPS_CPU_HTW; 74 write_c0_pwctl(read_c0_pwctl() & 75 ~(1 << MIPS_PWCTL_PWEN_SHIFT)); 76 77 return 1; 78 } 79 80 __setup("nohtw", htw_disable); 81 82 static int mips_ftlb_disabled; 83 static int mips_has_ftlb_configured; 84 85 enum ftlb_flags { 86 FTLB_EN = 1 << 0, 87 FTLB_SET_PROB = 1 << 1, 88 }; 89 90 static int set_ftlb_enable(struct cpuinfo_mips *c, enum ftlb_flags flags); 91 92 static int __init ftlb_disable(char *s) 93 { 94 unsigned int config4, mmuextdef; 95 96 /* 97 * If the core hasn't done any FTLB configuration, there is nothing 98 * for us to do here. 99 */ 100 if (!mips_has_ftlb_configured) 101 return 1; 102 103 /* Disable it in the boot cpu */ 104 if (set_ftlb_enable(&cpu_data[0], 0)) { 105 pr_warn("Can't turn FTLB off\n"); 106 return 1; 107 } 108 109 config4 = read_c0_config4(); 110 111 /* Check that FTLB has been disabled */ 112 mmuextdef = config4 & MIPS_CONF4_MMUEXTDEF; 113 /* MMUSIZEEXT == VTLB ON, FTLB OFF */ 114 if (mmuextdef == MIPS_CONF4_MMUEXTDEF_FTLBSIZEEXT) { 115 /* This should never happen */ 116 pr_warn("FTLB could not be disabled!\n"); 117 return 1; 118 } 119 120 mips_ftlb_disabled = 1; 121 mips_has_ftlb_configured = 0; 122 123 /* 124 * noftlb is mainly used for debug purposes so print 125 * an informative message instead of using pr_debug() 126 */ 127 pr_info("FTLB has been disabled\n"); 128 129 /* 130 * Some of these bits are duplicated in the decode_config4. 131 * MIPS_CONF4_MMUEXTDEF_MMUSIZEEXT is the only possible case 132 * once FTLB has been disabled so undo what decode_config4 did. 133 */ 134 cpu_data[0].tlbsize -= cpu_data[0].tlbsizeftlbways * 135 cpu_data[0].tlbsizeftlbsets; 136 cpu_data[0].tlbsizeftlbsets = 0; 137 cpu_data[0].tlbsizeftlbways = 0; 138 139 return 1; 140 } 141 142 __setup("noftlb", ftlb_disable); 143 144 /* 145 * Check if the CPU has per tc perf counters 146 */ 147 static inline void cpu_set_mt_per_tc_perf(struct cpuinfo_mips *c) 148 { 149 if (read_c0_config7() & MTI_CONF7_PTC) 150 c->options |= MIPS_CPU_MT_PER_TC_PERF_COUNTERS; 151 } 152 153 static inline void check_errata(void) 154 { 155 struct cpuinfo_mips *c = ¤t_cpu_data; 156 157 switch (current_cpu_type()) { 158 case CPU_34K: 159 /* 160 * Erratum "RPS May Cause Incorrect Instruction Execution" 161 * This code only handles VPE0, any SMP/RTOS code 162 * making use of VPE1 will be responsible for that VPE. 163 */ 164 if ((c->processor_id & PRID_REV_MASK) <= PRID_REV_34K_V1_0_2) 165 write_c0_config7(read_c0_config7() | MIPS_CONF7_RPS); 166 break; 167 default: 168 break; 169 } 170 } 171 172 void __init check_bugs32(void) 173 { 174 check_errata(); 175 } 176 177 /* 178 * Probe whether cpu has config register by trying to play with 179 * alternate cache bit and see whether it matters. 180 * It's used by cpu_probe to distinguish between R3000A and R3081. 181 */ 182 static inline int cpu_has_confreg(void) 183 { 184 #ifdef CONFIG_CPU_R3000 185 unsigned long size1, size2; 186 unsigned long cfg = read_c0_conf(); 187 188 size1 = r3k_cache_size(ST0_ISC); 189 write_c0_conf(cfg ^ R30XX_CONF_AC); 190 size2 = r3k_cache_size(ST0_ISC); 191 write_c0_conf(cfg); 192 return size1 != size2; 193 #else 194 return 0; 195 #endif 196 } 197 198 static inline void set_elf_platform(int cpu, const char *plat) 199 { 200 if (cpu == 0) 201 __elf_platform = plat; 202 } 203 204 static inline void set_elf_base_platform(const char *plat) 205 { 206 if (__elf_base_platform == NULL) { 207 __elf_base_platform = plat; 208 } 209 } 210 211 static inline void cpu_probe_vmbits(struct cpuinfo_mips *c) 212 { 213 int vmbits = 31; 214 215 if (cpu_has_64bits) { 216 write_c0_entryhi_64(0x3fffffffffffe000ULL); 217 back_to_back_c0_hazard(); 218 vmbits = fls64(read_c0_entryhi_64() & 0x3fffffffffffe000ULL); 219 } 220 c->vmbits = vmbits; 221 } 222 223 static void set_isa(struct cpuinfo_mips *c, unsigned int isa) 224 { 225 switch (isa) { 226 case MIPS_CPU_ISA_M64R5: 227 c->isa_level |= MIPS_CPU_ISA_M32R5 | MIPS_CPU_ISA_M64R5; 228 set_elf_base_platform("mips64r5"); 229 fallthrough; 230 case MIPS_CPU_ISA_M64R2: 231 c->isa_level |= MIPS_CPU_ISA_M32R2 | MIPS_CPU_ISA_M64R2; 232 set_elf_base_platform("mips64r2"); 233 fallthrough; 234 case MIPS_CPU_ISA_M64R1: 235 c->isa_level |= MIPS_CPU_ISA_M32R1 | MIPS_CPU_ISA_M64R1; 236 set_elf_base_platform("mips64"); 237 fallthrough; 238 case MIPS_CPU_ISA_V: 239 c->isa_level |= MIPS_CPU_ISA_V; 240 set_elf_base_platform("mips5"); 241 fallthrough; 242 case MIPS_CPU_ISA_IV: 243 c->isa_level |= MIPS_CPU_ISA_IV; 244 set_elf_base_platform("mips4"); 245 fallthrough; 246 case MIPS_CPU_ISA_III: 247 c->isa_level |= MIPS_CPU_ISA_II | MIPS_CPU_ISA_III; 248 set_elf_base_platform("mips3"); 249 break; 250 251 /* R6 incompatible with everything else */ 252 case MIPS_CPU_ISA_M64R6: 253 c->isa_level |= MIPS_CPU_ISA_M32R6 | MIPS_CPU_ISA_M64R6; 254 set_elf_base_platform("mips64r6"); 255 fallthrough; 256 case MIPS_CPU_ISA_M32R6: 257 c->isa_level |= MIPS_CPU_ISA_M32R6; 258 set_elf_base_platform("mips32r6"); 259 /* Break here so we don't add incompatible ISAs */ 260 break; 261 case MIPS_CPU_ISA_M32R5: 262 c->isa_level |= MIPS_CPU_ISA_M32R5; 263 set_elf_base_platform("mips32r5"); 264 fallthrough; 265 case MIPS_CPU_ISA_M32R2: 266 c->isa_level |= MIPS_CPU_ISA_M32R2; 267 set_elf_base_platform("mips32r2"); 268 fallthrough; 269 case MIPS_CPU_ISA_M32R1: 270 c->isa_level |= MIPS_CPU_ISA_M32R1; 271 set_elf_base_platform("mips32"); 272 fallthrough; 273 case MIPS_CPU_ISA_II: 274 c->isa_level |= MIPS_CPU_ISA_II; 275 set_elf_base_platform("mips2"); 276 break; 277 } 278 } 279 280 static char unknown_isa[] = KERN_ERR \ 281 "Unsupported ISA type, c0.config0: %d."; 282 283 static unsigned int calculate_ftlb_probability(struct cpuinfo_mips *c) 284 { 285 286 unsigned int probability = c->tlbsize / c->tlbsizevtlb; 287 288 /* 289 * 0 = All TLBWR instructions go to FTLB 290 * 1 = 15:1: For every 16 TBLWR instructions, 15 go to the 291 * FTLB and 1 goes to the VTLB. 292 * 2 = 7:1: As above with 7:1 ratio. 293 * 3 = 3:1: As above with 3:1 ratio. 294 * 295 * Use the linear midpoint as the probability threshold. 296 */ 297 if (probability >= 12) 298 return 1; 299 else if (probability >= 6) 300 return 2; 301 else 302 /* 303 * So FTLB is less than 4 times bigger than VTLB. 304 * A 3:1 ratio can still be useful though. 305 */ 306 return 3; 307 } 308 309 static int set_ftlb_enable(struct cpuinfo_mips *c, enum ftlb_flags flags) 310 { 311 unsigned int config; 312 313 /* It's implementation dependent how the FTLB can be enabled */ 314 switch (c->cputype) { 315 case CPU_PROAPTIV: 316 case CPU_P5600: 317 case CPU_P6600: 318 /* proAptiv & related cores use Config6 to enable the FTLB */ 319 config = read_c0_config6(); 320 321 if (flags & FTLB_EN) 322 config |= MTI_CONF6_FTLBEN; 323 else 324 config &= ~MTI_CONF6_FTLBEN; 325 326 if (flags & FTLB_SET_PROB) { 327 config &= ~(3 << MTI_CONF6_FTLBP_SHIFT); 328 config |= calculate_ftlb_probability(c) 329 << MTI_CONF6_FTLBP_SHIFT; 330 } 331 332 write_c0_config6(config); 333 back_to_back_c0_hazard(); 334 break; 335 case CPU_I6400: 336 case CPU_I6500: 337 /* There's no way to disable the FTLB */ 338 if (!(flags & FTLB_EN)) 339 return 1; 340 return 0; 341 case CPU_LOONGSON64: 342 /* Flush ITLB, DTLB, VTLB and FTLB */ 343 write_c0_diag(LOONGSON_DIAG_ITLB | LOONGSON_DIAG_DTLB | 344 LOONGSON_DIAG_VTLB | LOONGSON_DIAG_FTLB); 345 /* Loongson-3 cores use Config6 to enable the FTLB */ 346 config = read_c0_config6(); 347 if (flags & FTLB_EN) 348 /* Enable FTLB */ 349 write_c0_config6(config & ~LOONGSON_CONF6_FTLBDIS); 350 else 351 /* Disable FTLB */ 352 write_c0_config6(config | LOONGSON_CONF6_FTLBDIS); 353 break; 354 default: 355 return 1; 356 } 357 358 return 0; 359 } 360 361 static int mm_config(struct cpuinfo_mips *c) 362 { 363 unsigned int config0, update, mm; 364 365 config0 = read_c0_config(); 366 mm = config0 & MIPS_CONF_MM; 367 368 /* 369 * It's implementation dependent what type of write-merge is supported 370 * and whether it can be enabled/disabled. If it is settable lets make 371 * the merging allowed by default. Some platforms might have 372 * write-through caching unsupported. In this case just ignore the 373 * CP0.Config.MM bit field value. 374 */ 375 switch (c->cputype) { 376 case CPU_24K: 377 case CPU_34K: 378 case CPU_74K: 379 case CPU_P5600: 380 case CPU_P6600: 381 c->options |= MIPS_CPU_MM_FULL; 382 update = MIPS_CONF_MM_FULL; 383 break; 384 case CPU_1004K: 385 case CPU_1074K: 386 case CPU_INTERAPTIV: 387 case CPU_PROAPTIV: 388 mm = 0; 389 fallthrough; 390 default: 391 update = 0; 392 break; 393 } 394 395 if (update) { 396 config0 = (config0 & ~MIPS_CONF_MM) | update; 397 write_c0_config(config0); 398 } else if (mm == MIPS_CONF_MM_SYSAD) { 399 c->options |= MIPS_CPU_MM_SYSAD; 400 } else if (mm == MIPS_CONF_MM_FULL) { 401 c->options |= MIPS_CPU_MM_FULL; 402 } 403 404 return 0; 405 } 406 407 static inline unsigned int decode_config0(struct cpuinfo_mips *c) 408 { 409 unsigned int config0; 410 int isa, mt; 411 412 config0 = read_c0_config(); 413 414 /* 415 * Look for Standard TLB or Dual VTLB and FTLB 416 */ 417 mt = config0 & MIPS_CONF_MT; 418 if (mt == MIPS_CONF_MT_TLB) 419 c->options |= MIPS_CPU_TLB; 420 else if (mt == MIPS_CONF_MT_FTLB) 421 c->options |= MIPS_CPU_TLB | MIPS_CPU_FTLB; 422 423 isa = (config0 & MIPS_CONF_AT) >> 13; 424 switch (isa) { 425 case 0: 426 switch ((config0 & MIPS_CONF_AR) >> 10) { 427 case 0: 428 set_isa(c, MIPS_CPU_ISA_M32R1); 429 break; 430 case 1: 431 set_isa(c, MIPS_CPU_ISA_M32R2); 432 break; 433 case 2: 434 set_isa(c, MIPS_CPU_ISA_M32R6); 435 break; 436 default: 437 goto unknown; 438 } 439 break; 440 case 2: 441 switch ((config0 & MIPS_CONF_AR) >> 10) { 442 case 0: 443 set_isa(c, MIPS_CPU_ISA_M64R1); 444 break; 445 case 1: 446 set_isa(c, MIPS_CPU_ISA_M64R2); 447 break; 448 case 2: 449 set_isa(c, MIPS_CPU_ISA_M64R6); 450 break; 451 default: 452 goto unknown; 453 } 454 break; 455 default: 456 goto unknown; 457 } 458 459 return config0 & MIPS_CONF_M; 460 461 unknown: 462 panic(unknown_isa, config0); 463 } 464 465 static inline unsigned int decode_config1(struct cpuinfo_mips *c) 466 { 467 unsigned int config1; 468 469 config1 = read_c0_config1(); 470 471 if (config1 & MIPS_CONF1_MD) 472 c->ases |= MIPS_ASE_MDMX; 473 if (config1 & MIPS_CONF1_PC) 474 c->options |= MIPS_CPU_PERF; 475 if (config1 & MIPS_CONF1_WR) 476 c->options |= MIPS_CPU_WATCH; 477 if (config1 & MIPS_CONF1_CA) 478 c->ases |= MIPS_ASE_MIPS16; 479 if (config1 & MIPS_CONF1_EP) 480 c->options |= MIPS_CPU_EJTAG; 481 if (config1 & MIPS_CONF1_FP) { 482 c->options |= MIPS_CPU_FPU; 483 c->options |= MIPS_CPU_32FPR; 484 } 485 if (cpu_has_tlb) { 486 c->tlbsize = ((config1 & MIPS_CONF1_TLBS) >> 25) + 1; 487 c->tlbsizevtlb = c->tlbsize; 488 c->tlbsizeftlbsets = 0; 489 } 490 491 return config1 & MIPS_CONF_M; 492 } 493 494 static inline unsigned int decode_config2(struct cpuinfo_mips *c) 495 { 496 unsigned int config2; 497 498 config2 = read_c0_config2(); 499 500 if (config2 & MIPS_CONF2_SL) 501 c->scache.flags &= ~MIPS_CACHE_NOT_PRESENT; 502 503 return config2 & MIPS_CONF_M; 504 } 505 506 static inline unsigned int decode_config3(struct cpuinfo_mips *c) 507 { 508 unsigned int config3; 509 510 config3 = read_c0_config3(); 511 512 if (config3 & MIPS_CONF3_SM) { 513 c->ases |= MIPS_ASE_SMARTMIPS; 514 c->options |= MIPS_CPU_RIXI | MIPS_CPU_CTXTC; 515 } 516 if (config3 & MIPS_CONF3_RXI) 517 c->options |= MIPS_CPU_RIXI; 518 if (config3 & MIPS_CONF3_CTXTC) 519 c->options |= MIPS_CPU_CTXTC; 520 if (config3 & MIPS_CONF3_DSP) 521 c->ases |= MIPS_ASE_DSP; 522 if (config3 & MIPS_CONF3_DSP2P) { 523 c->ases |= MIPS_ASE_DSP2P; 524 if (cpu_has_mips_r6) 525 c->ases |= MIPS_ASE_DSP3; 526 } 527 if (config3 & MIPS_CONF3_VINT) 528 c->options |= MIPS_CPU_VINT; 529 if (config3 & MIPS_CONF3_VEIC) 530 c->options |= MIPS_CPU_VEIC; 531 if (config3 & MIPS_CONF3_LPA) 532 c->options |= MIPS_CPU_LPA; 533 if (config3 & MIPS_CONF3_MT) 534 c->ases |= MIPS_ASE_MIPSMT; 535 if (config3 & MIPS_CONF3_ULRI) 536 c->options |= MIPS_CPU_ULRI; 537 if (config3 & MIPS_CONF3_ISA) 538 c->options |= MIPS_CPU_MICROMIPS; 539 if (config3 & MIPS_CONF3_VZ) 540 c->ases |= MIPS_ASE_VZ; 541 if (config3 & MIPS_CONF3_SC) 542 c->options |= MIPS_CPU_SEGMENTS; 543 if (config3 & MIPS_CONF3_BI) 544 c->options |= MIPS_CPU_BADINSTR; 545 if (config3 & MIPS_CONF3_BP) 546 c->options |= MIPS_CPU_BADINSTRP; 547 if (config3 & MIPS_CONF3_MSA) 548 c->ases |= MIPS_ASE_MSA; 549 if (config3 & MIPS_CONF3_PW) { 550 c->htw_seq = 0; 551 c->options |= MIPS_CPU_HTW; 552 } 553 if (config3 & MIPS_CONF3_CDMM) 554 c->options |= MIPS_CPU_CDMM; 555 if (config3 & MIPS_CONF3_SP) 556 c->options |= MIPS_CPU_SP; 557 558 return config3 & MIPS_CONF_M; 559 } 560 561 static inline unsigned int decode_config4(struct cpuinfo_mips *c) 562 { 563 unsigned int config4; 564 unsigned int newcf4; 565 unsigned int mmuextdef; 566 unsigned int ftlb_page = MIPS_CONF4_FTLBPAGESIZE; 567 unsigned long asid_mask; 568 569 config4 = read_c0_config4(); 570 571 if (cpu_has_tlb) { 572 if (((config4 & MIPS_CONF4_IE) >> 29) == 2) 573 c->options |= MIPS_CPU_TLBINV; 574 575 /* 576 * R6 has dropped the MMUExtDef field from config4. 577 * On R6 the fields always describe the FTLB, and only if it is 578 * present according to Config.MT. 579 */ 580 if (!cpu_has_mips_r6) 581 mmuextdef = config4 & MIPS_CONF4_MMUEXTDEF; 582 else if (cpu_has_ftlb) 583 mmuextdef = MIPS_CONF4_MMUEXTDEF_VTLBSIZEEXT; 584 else 585 mmuextdef = 0; 586 587 switch (mmuextdef) { 588 case MIPS_CONF4_MMUEXTDEF_MMUSIZEEXT: 589 c->tlbsize += (config4 & MIPS_CONF4_MMUSIZEEXT) * 0x40; 590 c->tlbsizevtlb = c->tlbsize; 591 break; 592 case MIPS_CONF4_MMUEXTDEF_VTLBSIZEEXT: 593 c->tlbsizevtlb += 594 ((config4 & MIPS_CONF4_VTLBSIZEEXT) >> 595 MIPS_CONF4_VTLBSIZEEXT_SHIFT) * 0x40; 596 c->tlbsize = c->tlbsizevtlb; 597 ftlb_page = MIPS_CONF4_VFTLBPAGESIZE; 598 fallthrough; 599 case MIPS_CONF4_MMUEXTDEF_FTLBSIZEEXT: 600 if (mips_ftlb_disabled) 601 break; 602 newcf4 = (config4 & ~ftlb_page) | 603 (page_size_ftlb(mmuextdef) << 604 MIPS_CONF4_FTLBPAGESIZE_SHIFT); 605 write_c0_config4(newcf4); 606 back_to_back_c0_hazard(); 607 config4 = read_c0_config4(); 608 if (config4 != newcf4) { 609 pr_err("PAGE_SIZE 0x%lx is not supported by FTLB (config4=0x%x)\n", 610 PAGE_SIZE, config4); 611 /* Switch FTLB off */ 612 set_ftlb_enable(c, 0); 613 mips_ftlb_disabled = 1; 614 break; 615 } 616 c->tlbsizeftlbsets = 1 << 617 ((config4 & MIPS_CONF4_FTLBSETS) >> 618 MIPS_CONF4_FTLBSETS_SHIFT); 619 c->tlbsizeftlbways = ((config4 & MIPS_CONF4_FTLBWAYS) >> 620 MIPS_CONF4_FTLBWAYS_SHIFT) + 2; 621 c->tlbsize += c->tlbsizeftlbways * c->tlbsizeftlbsets; 622 mips_has_ftlb_configured = 1; 623 break; 624 } 625 } 626 627 c->kscratch_mask = (config4 & MIPS_CONF4_KSCREXIST) 628 >> MIPS_CONF4_KSCREXIST_SHIFT; 629 630 asid_mask = MIPS_ENTRYHI_ASID; 631 if (config4 & MIPS_CONF4_AE) 632 asid_mask |= MIPS_ENTRYHI_ASIDX; 633 set_cpu_asid_mask(c, asid_mask); 634 635 /* 636 * Warn if the computed ASID mask doesn't match the mask the kernel 637 * is built for. This may indicate either a serious problem or an 638 * easy optimisation opportunity, but either way should be addressed. 639 */ 640 WARN_ON(asid_mask != cpu_asid_mask(c)); 641 642 return config4 & MIPS_CONF_M; 643 } 644 645 static inline unsigned int decode_config5(struct cpuinfo_mips *c) 646 { 647 unsigned int config5, max_mmid_width; 648 unsigned long asid_mask; 649 650 config5 = read_c0_config5(); 651 config5 &= ~(MIPS_CONF5_UFR | MIPS_CONF5_UFE); 652 653 if (cpu_has_mips_r6) { 654 if (!mmid_disabled_quirk && (!__builtin_constant_p(cpu_has_mmid) || cpu_has_mmid)) 655 config5 |= MIPS_CONF5_MI; 656 else 657 config5 &= ~MIPS_CONF5_MI; 658 } 659 660 write_c0_config5(config5); 661 662 if (config5 & MIPS_CONF5_EVA) 663 c->options |= MIPS_CPU_EVA; 664 if (config5 & MIPS_CONF5_MRP) 665 c->options |= MIPS_CPU_MAAR; 666 if (config5 & MIPS_CONF5_LLB) 667 c->options |= MIPS_CPU_RW_LLB; 668 if (config5 & MIPS_CONF5_MVH) 669 c->options |= MIPS_CPU_MVH; 670 if (cpu_has_mips_r6 && (config5 & MIPS_CONF5_VP)) 671 c->options |= MIPS_CPU_VP; 672 if (config5 & MIPS_CONF5_CA2) 673 c->ases |= MIPS_ASE_MIPS16E2; 674 675 if (config5 & MIPS_CONF5_CRCP) 676 elf_hwcap |= HWCAP_MIPS_CRC32; 677 678 if (cpu_has_mips_r6) { 679 /* Ensure the write to config5 above takes effect */ 680 back_to_back_c0_hazard(); 681 682 /* Check whether we successfully enabled MMID support */ 683 config5 = read_c0_config5(); 684 if (config5 & MIPS_CONF5_MI) 685 c->options |= MIPS_CPU_MMID; 686 687 /* 688 * Warn if we've hardcoded cpu_has_mmid to a value unsuitable 689 * for the CPU we're running on, or if CPUs in an SMP system 690 * have inconsistent MMID support. 691 */ 692 WARN_ON(!!cpu_has_mmid != !!(config5 & MIPS_CONF5_MI)); 693 694 if (cpu_has_mmid) { 695 write_c0_memorymapid(~0ul); 696 back_to_back_c0_hazard(); 697 asid_mask = read_c0_memorymapid(); 698 699 /* 700 * We maintain a bitmap to track MMID allocation, and 701 * need a sensible upper bound on the size of that 702 * bitmap. The initial CPU with MMID support (I6500) 703 * supports 16 bit MMIDs, which gives us an 8KiB 704 * bitmap. The architecture recommends that hardware 705 * support 32 bit MMIDs, which would give us a 512MiB 706 * bitmap - that's too big in most cases. 707 * 708 * Cap MMID width at 16 bits for now & we can revisit 709 * this if & when hardware supports anything wider. 710 */ 711 max_mmid_width = 16; 712 if (asid_mask > GENMASK(max_mmid_width - 1, 0)) { 713 pr_info("Capping MMID width at %d bits", 714 max_mmid_width); 715 asid_mask = GENMASK(max_mmid_width - 1, 0); 716 } 717 set_cpu_asid_mask(c, asid_mask); 718 } 719 } 720 721 return config5 & MIPS_CONF_M; 722 } 723 724 static void decode_configs(struct cpuinfo_mips *c) 725 { 726 int ok; 727 728 /* MIPS32 or MIPS64 compliant CPU. */ 729 c->options = MIPS_CPU_4KEX | MIPS_CPU_4K_CACHE | MIPS_CPU_COUNTER | 730 MIPS_CPU_DIVEC | MIPS_CPU_LLSC | MIPS_CPU_MCHECK; 731 732 c->scache.flags = MIPS_CACHE_NOT_PRESENT; 733 734 /* Enable FTLB if present and not disabled */ 735 set_ftlb_enable(c, mips_ftlb_disabled ? 0 : FTLB_EN); 736 737 ok = decode_config0(c); /* Read Config registers. */ 738 BUG_ON(!ok); /* Arch spec violation! */ 739 if (ok) 740 ok = decode_config1(c); 741 if (ok) 742 ok = decode_config2(c); 743 if (ok) 744 ok = decode_config3(c); 745 if (ok) 746 ok = decode_config4(c); 747 if (ok) 748 ok = decode_config5(c); 749 750 /* Probe the EBase.WG bit */ 751 if (cpu_has_mips_r2_r6) { 752 u64 ebase; 753 unsigned int status; 754 755 /* {read,write}_c0_ebase_64() may be UNDEFINED prior to r6 */ 756 ebase = cpu_has_mips64r6 ? read_c0_ebase_64() 757 : (s32)read_c0_ebase(); 758 if (ebase & MIPS_EBASE_WG) { 759 /* WG bit already set, we can avoid the clumsy probe */ 760 c->options |= MIPS_CPU_EBASE_WG; 761 } else { 762 /* Its UNDEFINED to change EBase while BEV=0 */ 763 status = read_c0_status(); 764 write_c0_status(status | ST0_BEV); 765 irq_enable_hazard(); 766 /* 767 * On pre-r6 cores, this may well clobber the upper bits 768 * of EBase. This is hard to avoid without potentially 769 * hitting UNDEFINED dm*c0 behaviour if EBase is 32-bit. 770 */ 771 if (cpu_has_mips64r6) 772 write_c0_ebase_64(ebase | MIPS_EBASE_WG); 773 else 774 write_c0_ebase(ebase | MIPS_EBASE_WG); 775 back_to_back_c0_hazard(); 776 /* Restore BEV */ 777 write_c0_status(status); 778 if (read_c0_ebase() & MIPS_EBASE_WG) { 779 c->options |= MIPS_CPU_EBASE_WG; 780 write_c0_ebase(ebase); 781 } 782 } 783 } 784 785 /* configure the FTLB write probability */ 786 set_ftlb_enable(c, (mips_ftlb_disabled ? 0 : FTLB_EN) | FTLB_SET_PROB); 787 788 mips_probe_watch_registers(c); 789 790 #ifndef CONFIG_MIPS_CPS 791 if (cpu_has_mips_r2_r6) { 792 unsigned int core; 793 794 core = get_ebase_cpunum(); 795 if (cpu_has_mipsmt) 796 core >>= fls(core_nvpes()) - 1; 797 cpu_set_core(c, core); 798 } 799 #endif 800 } 801 802 /* 803 * Probe for certain guest capabilities by writing config bits and reading back. 804 * Finally write back the original value. 805 */ 806 #define probe_gc0_config(name, maxconf, bits) \ 807 do { \ 808 unsigned int tmp; \ 809 tmp = read_gc0_##name(); \ 810 write_gc0_##name(tmp | (bits)); \ 811 back_to_back_c0_hazard(); \ 812 maxconf = read_gc0_##name(); \ 813 write_gc0_##name(tmp); \ 814 } while (0) 815 816 /* 817 * Probe for dynamic guest capabilities by changing certain config bits and 818 * reading back to see if they change. Finally write back the original value. 819 */ 820 #define probe_gc0_config_dyn(name, maxconf, dynconf, bits) \ 821 do { \ 822 maxconf = read_gc0_##name(); \ 823 write_gc0_##name(maxconf ^ (bits)); \ 824 back_to_back_c0_hazard(); \ 825 dynconf = maxconf ^ read_gc0_##name(); \ 826 write_gc0_##name(maxconf); \ 827 maxconf |= dynconf; \ 828 } while (0) 829 830 static inline unsigned int decode_guest_config0(struct cpuinfo_mips *c) 831 { 832 unsigned int config0; 833 834 probe_gc0_config(config, config0, MIPS_CONF_M); 835 836 if (config0 & MIPS_CONF_M) 837 c->guest.conf |= BIT(1); 838 return config0 & MIPS_CONF_M; 839 } 840 841 static inline unsigned int decode_guest_config1(struct cpuinfo_mips *c) 842 { 843 unsigned int config1, config1_dyn; 844 845 probe_gc0_config_dyn(config1, config1, config1_dyn, 846 MIPS_CONF_M | MIPS_CONF1_PC | MIPS_CONF1_WR | 847 MIPS_CONF1_FP); 848 849 if (config1 & MIPS_CONF1_FP) 850 c->guest.options |= MIPS_CPU_FPU; 851 if (config1_dyn & MIPS_CONF1_FP) 852 c->guest.options_dyn |= MIPS_CPU_FPU; 853 854 if (config1 & MIPS_CONF1_WR) 855 c->guest.options |= MIPS_CPU_WATCH; 856 if (config1_dyn & MIPS_CONF1_WR) 857 c->guest.options_dyn |= MIPS_CPU_WATCH; 858 859 if (config1 & MIPS_CONF1_PC) 860 c->guest.options |= MIPS_CPU_PERF; 861 if (config1_dyn & MIPS_CONF1_PC) 862 c->guest.options_dyn |= MIPS_CPU_PERF; 863 864 if (config1 & MIPS_CONF_M) 865 c->guest.conf |= BIT(2); 866 return config1 & MIPS_CONF_M; 867 } 868 869 static inline unsigned int decode_guest_config2(struct cpuinfo_mips *c) 870 { 871 unsigned int config2; 872 873 probe_gc0_config(config2, config2, MIPS_CONF_M); 874 875 if (config2 & MIPS_CONF_M) 876 c->guest.conf |= BIT(3); 877 return config2 & MIPS_CONF_M; 878 } 879 880 static inline unsigned int decode_guest_config3(struct cpuinfo_mips *c) 881 { 882 unsigned int config3, config3_dyn; 883 884 probe_gc0_config_dyn(config3, config3, config3_dyn, 885 MIPS_CONF_M | MIPS_CONF3_MSA | MIPS_CONF3_ULRI | 886 MIPS_CONF3_CTXTC); 887 888 if (config3 & MIPS_CONF3_CTXTC) 889 c->guest.options |= MIPS_CPU_CTXTC; 890 if (config3_dyn & MIPS_CONF3_CTXTC) 891 c->guest.options_dyn |= MIPS_CPU_CTXTC; 892 893 if (config3 & MIPS_CONF3_PW) 894 c->guest.options |= MIPS_CPU_HTW; 895 896 if (config3 & MIPS_CONF3_ULRI) 897 c->guest.options |= MIPS_CPU_ULRI; 898 899 if (config3 & MIPS_CONF3_SC) 900 c->guest.options |= MIPS_CPU_SEGMENTS; 901 902 if (config3 & MIPS_CONF3_BI) 903 c->guest.options |= MIPS_CPU_BADINSTR; 904 if (config3 & MIPS_CONF3_BP) 905 c->guest.options |= MIPS_CPU_BADINSTRP; 906 907 if (config3 & MIPS_CONF3_MSA) 908 c->guest.ases |= MIPS_ASE_MSA; 909 if (config3_dyn & MIPS_CONF3_MSA) 910 c->guest.ases_dyn |= MIPS_ASE_MSA; 911 912 if (config3 & MIPS_CONF_M) 913 c->guest.conf |= BIT(4); 914 return config3 & MIPS_CONF_M; 915 } 916 917 static inline unsigned int decode_guest_config4(struct cpuinfo_mips *c) 918 { 919 unsigned int config4; 920 921 probe_gc0_config(config4, config4, 922 MIPS_CONF_M | MIPS_CONF4_KSCREXIST); 923 924 c->guest.kscratch_mask = (config4 & MIPS_CONF4_KSCREXIST) 925 >> MIPS_CONF4_KSCREXIST_SHIFT; 926 927 if (config4 & MIPS_CONF_M) 928 c->guest.conf |= BIT(5); 929 return config4 & MIPS_CONF_M; 930 } 931 932 static inline unsigned int decode_guest_config5(struct cpuinfo_mips *c) 933 { 934 unsigned int config5, config5_dyn; 935 936 probe_gc0_config_dyn(config5, config5, config5_dyn, 937 MIPS_CONF_M | MIPS_CONF5_MVH | MIPS_CONF5_MRP); 938 939 if (config5 & MIPS_CONF5_MRP) 940 c->guest.options |= MIPS_CPU_MAAR; 941 if (config5_dyn & MIPS_CONF5_MRP) 942 c->guest.options_dyn |= MIPS_CPU_MAAR; 943 944 if (config5 & MIPS_CONF5_LLB) 945 c->guest.options |= MIPS_CPU_RW_LLB; 946 947 if (config5 & MIPS_CONF5_MVH) 948 c->guest.options |= MIPS_CPU_MVH; 949 950 if (config5 & MIPS_CONF_M) 951 c->guest.conf |= BIT(6); 952 return config5 & MIPS_CONF_M; 953 } 954 955 static inline void decode_guest_configs(struct cpuinfo_mips *c) 956 { 957 unsigned int ok; 958 959 ok = decode_guest_config0(c); 960 if (ok) 961 ok = decode_guest_config1(c); 962 if (ok) 963 ok = decode_guest_config2(c); 964 if (ok) 965 ok = decode_guest_config3(c); 966 if (ok) 967 ok = decode_guest_config4(c); 968 if (ok) 969 decode_guest_config5(c); 970 } 971 972 static inline void cpu_probe_guestctl0(struct cpuinfo_mips *c) 973 { 974 unsigned int guestctl0, temp; 975 976 guestctl0 = read_c0_guestctl0(); 977 978 if (guestctl0 & MIPS_GCTL0_G0E) 979 c->options |= MIPS_CPU_GUESTCTL0EXT; 980 if (guestctl0 & MIPS_GCTL0_G1) 981 c->options |= MIPS_CPU_GUESTCTL1; 982 if (guestctl0 & MIPS_GCTL0_G2) 983 c->options |= MIPS_CPU_GUESTCTL2; 984 if (!(guestctl0 & MIPS_GCTL0_RAD)) { 985 c->options |= MIPS_CPU_GUESTID; 986 987 /* 988 * Probe for Direct Root to Guest (DRG). Set GuestCtl1.RID = 0 989 * first, otherwise all data accesses will be fully virtualised 990 * as if they were performed by guest mode. 991 */ 992 write_c0_guestctl1(0); 993 tlbw_use_hazard(); 994 995 write_c0_guestctl0(guestctl0 | MIPS_GCTL0_DRG); 996 back_to_back_c0_hazard(); 997 temp = read_c0_guestctl0(); 998 999 if (temp & MIPS_GCTL0_DRG) { 1000 write_c0_guestctl0(guestctl0); 1001 c->options |= MIPS_CPU_DRG; 1002 } 1003 } 1004 } 1005 1006 static inline void cpu_probe_guestctl1(struct cpuinfo_mips *c) 1007 { 1008 if (cpu_has_guestid) { 1009 /* determine the number of bits of GuestID available */ 1010 write_c0_guestctl1(MIPS_GCTL1_ID); 1011 back_to_back_c0_hazard(); 1012 c->guestid_mask = (read_c0_guestctl1() & MIPS_GCTL1_ID) 1013 >> MIPS_GCTL1_ID_SHIFT; 1014 write_c0_guestctl1(0); 1015 } 1016 } 1017 1018 static inline void cpu_probe_gtoffset(struct cpuinfo_mips *c) 1019 { 1020 /* determine the number of bits of GTOffset available */ 1021 write_c0_gtoffset(0xffffffff); 1022 back_to_back_c0_hazard(); 1023 c->gtoffset_mask = read_c0_gtoffset(); 1024 write_c0_gtoffset(0); 1025 } 1026 1027 static inline void cpu_probe_vz(struct cpuinfo_mips *c) 1028 { 1029 cpu_probe_guestctl0(c); 1030 if (cpu_has_guestctl1) 1031 cpu_probe_guestctl1(c); 1032 1033 cpu_probe_gtoffset(c); 1034 1035 decode_guest_configs(c); 1036 } 1037 1038 #define R4K_OPTS (MIPS_CPU_TLB | MIPS_CPU_4KEX | MIPS_CPU_4K_CACHE \ 1039 | MIPS_CPU_COUNTER) 1040 1041 static inline void cpu_probe_legacy(struct cpuinfo_mips *c, unsigned int cpu) 1042 { 1043 switch (c->processor_id & PRID_IMP_MASK) { 1044 case PRID_IMP_R2000: 1045 c->cputype = CPU_R2000; 1046 __cpu_name[cpu] = "R2000"; 1047 c->fpu_msk31 |= FPU_CSR_CONDX | FPU_CSR_FS; 1048 c->options = MIPS_CPU_TLB | MIPS_CPU_3K_CACHE | 1049 MIPS_CPU_NOFPUEX; 1050 if (__cpu_has_fpu()) 1051 c->options |= MIPS_CPU_FPU; 1052 c->tlbsize = 64; 1053 break; 1054 case PRID_IMP_R3000: 1055 if ((c->processor_id & PRID_REV_MASK) == PRID_REV_R3000A) { 1056 if (cpu_has_confreg()) { 1057 c->cputype = CPU_R3081E; 1058 __cpu_name[cpu] = "R3081"; 1059 } else { 1060 c->cputype = CPU_R3000A; 1061 __cpu_name[cpu] = "R3000A"; 1062 } 1063 } else { 1064 c->cputype = CPU_R3000; 1065 __cpu_name[cpu] = "R3000"; 1066 } 1067 c->fpu_msk31 |= FPU_CSR_CONDX | FPU_CSR_FS; 1068 c->options = MIPS_CPU_TLB | MIPS_CPU_3K_CACHE | 1069 MIPS_CPU_NOFPUEX; 1070 if (__cpu_has_fpu()) 1071 c->options |= MIPS_CPU_FPU; 1072 c->tlbsize = 64; 1073 break; 1074 case PRID_IMP_R4000: 1075 if (read_c0_config() & CONF_SC) { 1076 if ((c->processor_id & PRID_REV_MASK) >= 1077 PRID_REV_R4400) { 1078 c->cputype = CPU_R4400PC; 1079 __cpu_name[cpu] = "R4400PC"; 1080 } else { 1081 c->cputype = CPU_R4000PC; 1082 __cpu_name[cpu] = "R4000PC"; 1083 } 1084 } else { 1085 int cca = read_c0_config() & CONF_CM_CMASK; 1086 int mc; 1087 1088 /* 1089 * SC and MC versions can't be reliably told apart, 1090 * but only the latter support coherent caching 1091 * modes so assume the firmware has set the KSEG0 1092 * coherency attribute reasonably (if uncached, we 1093 * assume SC). 1094 */ 1095 switch (cca) { 1096 case CONF_CM_CACHABLE_CE: 1097 case CONF_CM_CACHABLE_COW: 1098 case CONF_CM_CACHABLE_CUW: 1099 mc = 1; 1100 break; 1101 default: 1102 mc = 0; 1103 break; 1104 } 1105 if ((c->processor_id & PRID_REV_MASK) >= 1106 PRID_REV_R4400) { 1107 c->cputype = mc ? CPU_R4400MC : CPU_R4400SC; 1108 __cpu_name[cpu] = mc ? "R4400MC" : "R4400SC"; 1109 } else { 1110 c->cputype = mc ? CPU_R4000MC : CPU_R4000SC; 1111 __cpu_name[cpu] = mc ? "R4000MC" : "R4000SC"; 1112 } 1113 } 1114 1115 set_isa(c, MIPS_CPU_ISA_III); 1116 c->fpu_msk31 |= FPU_CSR_CONDX; 1117 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR | 1118 MIPS_CPU_WATCH | MIPS_CPU_VCE | 1119 MIPS_CPU_LLSC; 1120 c->tlbsize = 48; 1121 break; 1122 case PRID_IMP_R4300: 1123 c->cputype = CPU_R4300; 1124 __cpu_name[cpu] = "R4300"; 1125 set_isa(c, MIPS_CPU_ISA_III); 1126 c->fpu_msk31 |= FPU_CSR_CONDX; 1127 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR | 1128 MIPS_CPU_LLSC; 1129 c->tlbsize = 32; 1130 break; 1131 case PRID_IMP_R4600: 1132 c->cputype = CPU_R4600; 1133 __cpu_name[cpu] = "R4600"; 1134 set_isa(c, MIPS_CPU_ISA_III); 1135 c->fpu_msk31 |= FPU_CSR_CONDX; 1136 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR | 1137 MIPS_CPU_LLSC; 1138 c->tlbsize = 48; 1139 break; 1140 #if 0 1141 case PRID_IMP_R4650: 1142 /* 1143 * This processor doesn't have an MMU, so it's not 1144 * "real easy" to run Linux on it. It is left purely 1145 * for documentation. Commented out because it shares 1146 * its c0_prid id number with the TX3900. 1147 */ 1148 c->cputype = CPU_R4650; 1149 __cpu_name[cpu] = "R4650"; 1150 set_isa(c, MIPS_CPU_ISA_III); 1151 c->fpu_msk31 |= FPU_CSR_CONDX; 1152 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_LLSC; 1153 c->tlbsize = 48; 1154 break; 1155 #endif 1156 case PRID_IMP_R4700: 1157 c->cputype = CPU_R4700; 1158 __cpu_name[cpu] = "R4700"; 1159 set_isa(c, MIPS_CPU_ISA_III); 1160 c->fpu_msk31 |= FPU_CSR_CONDX; 1161 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR | 1162 MIPS_CPU_LLSC; 1163 c->tlbsize = 48; 1164 break; 1165 case PRID_IMP_TX49: 1166 c->cputype = CPU_TX49XX; 1167 __cpu_name[cpu] = "R49XX"; 1168 set_isa(c, MIPS_CPU_ISA_III); 1169 c->fpu_msk31 |= FPU_CSR_CONDX; 1170 c->options = R4K_OPTS | MIPS_CPU_LLSC; 1171 if (!(c->processor_id & 0x08)) 1172 c->options |= MIPS_CPU_FPU | MIPS_CPU_32FPR; 1173 c->tlbsize = 48; 1174 break; 1175 case PRID_IMP_R5000: 1176 c->cputype = CPU_R5000; 1177 __cpu_name[cpu] = "R5000"; 1178 set_isa(c, MIPS_CPU_ISA_IV); 1179 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR | 1180 MIPS_CPU_LLSC; 1181 c->tlbsize = 48; 1182 break; 1183 case PRID_IMP_R5500: 1184 c->cputype = CPU_R5500; 1185 __cpu_name[cpu] = "R5500"; 1186 set_isa(c, MIPS_CPU_ISA_IV); 1187 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR | 1188 MIPS_CPU_WATCH | MIPS_CPU_LLSC; 1189 c->tlbsize = 48; 1190 break; 1191 case PRID_IMP_NEVADA: 1192 c->cputype = CPU_NEVADA; 1193 __cpu_name[cpu] = "Nevada"; 1194 set_isa(c, MIPS_CPU_ISA_IV); 1195 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR | 1196 MIPS_CPU_DIVEC | MIPS_CPU_LLSC; 1197 c->tlbsize = 48; 1198 break; 1199 case PRID_IMP_RM7000: 1200 c->cputype = CPU_RM7000; 1201 __cpu_name[cpu] = "RM7000"; 1202 set_isa(c, MIPS_CPU_ISA_IV); 1203 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR | 1204 MIPS_CPU_LLSC; 1205 /* 1206 * Undocumented RM7000: Bit 29 in the info register of 1207 * the RM7000 v2.0 indicates if the TLB has 48 or 64 1208 * entries. 1209 * 1210 * 29 1 => 64 entry JTLB 1211 * 0 => 48 entry JTLB 1212 */ 1213 c->tlbsize = (read_c0_info() & (1 << 29)) ? 64 : 48; 1214 break; 1215 case PRID_IMP_R10000: 1216 c->cputype = CPU_R10000; 1217 __cpu_name[cpu] = "R10000"; 1218 set_isa(c, MIPS_CPU_ISA_IV); 1219 c->options = MIPS_CPU_TLB | MIPS_CPU_4K_CACHE | MIPS_CPU_4KEX | 1220 MIPS_CPU_FPU | MIPS_CPU_32FPR | 1221 MIPS_CPU_COUNTER | MIPS_CPU_WATCH | 1222 MIPS_CPU_LLSC; 1223 c->tlbsize = 64; 1224 break; 1225 case PRID_IMP_R12000: 1226 c->cputype = CPU_R12000; 1227 __cpu_name[cpu] = "R12000"; 1228 set_isa(c, MIPS_CPU_ISA_IV); 1229 c->options = MIPS_CPU_TLB | MIPS_CPU_4K_CACHE | MIPS_CPU_4KEX | 1230 MIPS_CPU_FPU | MIPS_CPU_32FPR | 1231 MIPS_CPU_COUNTER | MIPS_CPU_WATCH | 1232 MIPS_CPU_LLSC; 1233 c->tlbsize = 64; 1234 write_c0_r10k_diag(read_c0_r10k_diag() | R10K_DIAG_E_GHIST); 1235 break; 1236 case PRID_IMP_R14000: 1237 if (((c->processor_id >> 4) & 0x0f) > 2) { 1238 c->cputype = CPU_R16000; 1239 __cpu_name[cpu] = "R16000"; 1240 } else { 1241 c->cputype = CPU_R14000; 1242 __cpu_name[cpu] = "R14000"; 1243 } 1244 set_isa(c, MIPS_CPU_ISA_IV); 1245 c->options = MIPS_CPU_TLB | MIPS_CPU_4K_CACHE | MIPS_CPU_4KEX | 1246 MIPS_CPU_FPU | MIPS_CPU_32FPR | 1247 MIPS_CPU_COUNTER | MIPS_CPU_WATCH | 1248 MIPS_CPU_LLSC; 1249 c->tlbsize = 64; 1250 write_c0_r10k_diag(read_c0_r10k_diag() | R10K_DIAG_E_GHIST); 1251 break; 1252 case PRID_IMP_LOONGSON_64C: /* Loongson-2/3 */ 1253 switch (c->processor_id & PRID_REV_MASK) { 1254 case PRID_REV_LOONGSON2E: 1255 c->cputype = CPU_LOONGSON2EF; 1256 __cpu_name[cpu] = "ICT Loongson-2"; 1257 set_elf_platform(cpu, "loongson2e"); 1258 set_isa(c, MIPS_CPU_ISA_III); 1259 c->fpu_msk31 |= FPU_CSR_CONDX; 1260 break; 1261 case PRID_REV_LOONGSON2F: 1262 c->cputype = CPU_LOONGSON2EF; 1263 __cpu_name[cpu] = "ICT Loongson-2"; 1264 set_elf_platform(cpu, "loongson2f"); 1265 set_isa(c, MIPS_CPU_ISA_III); 1266 c->fpu_msk31 |= FPU_CSR_CONDX; 1267 break; 1268 case PRID_REV_LOONGSON3A_R1: 1269 c->cputype = CPU_LOONGSON64; 1270 __cpu_name[cpu] = "ICT Loongson-3"; 1271 set_elf_platform(cpu, "loongson3a"); 1272 set_isa(c, MIPS_CPU_ISA_M64R1); 1273 c->ases |= (MIPS_ASE_LOONGSON_MMI | MIPS_ASE_LOONGSON_CAM | 1274 MIPS_ASE_LOONGSON_EXT); 1275 break; 1276 case PRID_REV_LOONGSON3B_R1: 1277 case PRID_REV_LOONGSON3B_R2: 1278 c->cputype = CPU_LOONGSON64; 1279 __cpu_name[cpu] = "ICT Loongson-3"; 1280 set_elf_platform(cpu, "loongson3b"); 1281 set_isa(c, MIPS_CPU_ISA_M64R1); 1282 c->ases |= (MIPS_ASE_LOONGSON_MMI | MIPS_ASE_LOONGSON_CAM | 1283 MIPS_ASE_LOONGSON_EXT); 1284 break; 1285 } 1286 1287 c->options = R4K_OPTS | 1288 MIPS_CPU_FPU | MIPS_CPU_LLSC | 1289 MIPS_CPU_32FPR; 1290 c->tlbsize = 64; 1291 set_cpu_asid_mask(c, MIPS_ENTRYHI_ASID); 1292 c->writecombine = _CACHE_UNCACHED_ACCELERATED; 1293 break; 1294 case PRID_IMP_LOONGSON_32: 1295 decode_configs(c); 1296 1297 c->cputype = CPU_LOONGSON32; 1298 1299 switch (c->processor_id & PRID_REV_MASK) { 1300 case PRID_REV_LOONGSON1: 1301 __cpu_name[cpu] = "ICT Loongson-1"; 1302 break; 1303 } 1304 1305 break; 1306 } 1307 } 1308 1309 static inline void cpu_probe_mips(struct cpuinfo_mips *c, unsigned int cpu) 1310 { 1311 c->writecombine = _CACHE_UNCACHED_ACCELERATED; 1312 switch (c->processor_id & PRID_IMP_MASK) { 1313 case PRID_IMP_QEMU_GENERIC: 1314 c->writecombine = _CACHE_UNCACHED; 1315 c->cputype = CPU_QEMU_GENERIC; 1316 __cpu_name[cpu] = "MIPS GENERIC QEMU"; 1317 break; 1318 case PRID_IMP_4KC: 1319 c->cputype = CPU_4KC; 1320 c->writecombine = _CACHE_UNCACHED; 1321 __cpu_name[cpu] = "MIPS 4Kc"; 1322 break; 1323 case PRID_IMP_4KEC: 1324 case PRID_IMP_4KECR2: 1325 c->cputype = CPU_4KEC; 1326 c->writecombine = _CACHE_UNCACHED; 1327 __cpu_name[cpu] = "MIPS 4KEc"; 1328 break; 1329 case PRID_IMP_4KSC: 1330 case PRID_IMP_4KSD: 1331 c->cputype = CPU_4KSC; 1332 c->writecombine = _CACHE_UNCACHED; 1333 __cpu_name[cpu] = "MIPS 4KSc"; 1334 break; 1335 case PRID_IMP_5KC: 1336 c->cputype = CPU_5KC; 1337 c->writecombine = _CACHE_UNCACHED; 1338 __cpu_name[cpu] = "MIPS 5Kc"; 1339 break; 1340 case PRID_IMP_5KE: 1341 c->cputype = CPU_5KE; 1342 c->writecombine = _CACHE_UNCACHED; 1343 __cpu_name[cpu] = "MIPS 5KE"; 1344 break; 1345 case PRID_IMP_20KC: 1346 c->cputype = CPU_20KC; 1347 c->writecombine = _CACHE_UNCACHED; 1348 __cpu_name[cpu] = "MIPS 20Kc"; 1349 break; 1350 case PRID_IMP_24K: 1351 c->cputype = CPU_24K; 1352 c->writecombine = _CACHE_UNCACHED; 1353 __cpu_name[cpu] = "MIPS 24Kc"; 1354 break; 1355 case PRID_IMP_24KE: 1356 c->cputype = CPU_24K; 1357 c->writecombine = _CACHE_UNCACHED; 1358 __cpu_name[cpu] = "MIPS 24KEc"; 1359 break; 1360 case PRID_IMP_25KF: 1361 c->cputype = CPU_25KF; 1362 c->writecombine = _CACHE_UNCACHED; 1363 __cpu_name[cpu] = "MIPS 25Kc"; 1364 break; 1365 case PRID_IMP_34K: 1366 c->cputype = CPU_34K; 1367 c->writecombine = _CACHE_UNCACHED; 1368 __cpu_name[cpu] = "MIPS 34Kc"; 1369 cpu_set_mt_per_tc_perf(c); 1370 break; 1371 case PRID_IMP_74K: 1372 c->cputype = CPU_74K; 1373 c->writecombine = _CACHE_UNCACHED; 1374 __cpu_name[cpu] = "MIPS 74Kc"; 1375 break; 1376 case PRID_IMP_M14KC: 1377 c->cputype = CPU_M14KC; 1378 c->writecombine = _CACHE_UNCACHED; 1379 __cpu_name[cpu] = "MIPS M14Kc"; 1380 break; 1381 case PRID_IMP_M14KEC: 1382 c->cputype = CPU_M14KEC; 1383 c->writecombine = _CACHE_UNCACHED; 1384 __cpu_name[cpu] = "MIPS M14KEc"; 1385 break; 1386 case PRID_IMP_1004K: 1387 c->cputype = CPU_1004K; 1388 c->writecombine = _CACHE_UNCACHED; 1389 __cpu_name[cpu] = "MIPS 1004Kc"; 1390 cpu_set_mt_per_tc_perf(c); 1391 break; 1392 case PRID_IMP_1074K: 1393 c->cputype = CPU_1074K; 1394 c->writecombine = _CACHE_UNCACHED; 1395 __cpu_name[cpu] = "MIPS 1074Kc"; 1396 break; 1397 case PRID_IMP_INTERAPTIV_UP: 1398 c->cputype = CPU_INTERAPTIV; 1399 __cpu_name[cpu] = "MIPS interAptiv"; 1400 cpu_set_mt_per_tc_perf(c); 1401 break; 1402 case PRID_IMP_INTERAPTIV_MP: 1403 c->cputype = CPU_INTERAPTIV; 1404 __cpu_name[cpu] = "MIPS interAptiv (multi)"; 1405 cpu_set_mt_per_tc_perf(c); 1406 break; 1407 case PRID_IMP_PROAPTIV_UP: 1408 c->cputype = CPU_PROAPTIV; 1409 __cpu_name[cpu] = "MIPS proAptiv"; 1410 break; 1411 case PRID_IMP_PROAPTIV_MP: 1412 c->cputype = CPU_PROAPTIV; 1413 __cpu_name[cpu] = "MIPS proAptiv (multi)"; 1414 break; 1415 case PRID_IMP_P5600: 1416 c->cputype = CPU_P5600; 1417 __cpu_name[cpu] = "MIPS P5600"; 1418 break; 1419 case PRID_IMP_P6600: 1420 c->cputype = CPU_P6600; 1421 __cpu_name[cpu] = "MIPS P6600"; 1422 break; 1423 case PRID_IMP_I6400: 1424 c->cputype = CPU_I6400; 1425 __cpu_name[cpu] = "MIPS I6400"; 1426 break; 1427 case PRID_IMP_I6500: 1428 c->cputype = CPU_I6500; 1429 __cpu_name[cpu] = "MIPS I6500"; 1430 break; 1431 case PRID_IMP_M5150: 1432 c->cputype = CPU_M5150; 1433 __cpu_name[cpu] = "MIPS M5150"; 1434 break; 1435 case PRID_IMP_M6250: 1436 c->cputype = CPU_M6250; 1437 __cpu_name[cpu] = "MIPS M6250"; 1438 break; 1439 } 1440 1441 decode_configs(c); 1442 1443 spram_config(); 1444 1445 mm_config(c); 1446 1447 switch (__get_cpu_type(c->cputype)) { 1448 case CPU_M5150: 1449 case CPU_P5600: 1450 set_isa(c, MIPS_CPU_ISA_M32R5); 1451 break; 1452 case CPU_I6500: 1453 c->options |= MIPS_CPU_SHARED_FTLB_ENTRIES; 1454 fallthrough; 1455 case CPU_I6400: 1456 c->options |= MIPS_CPU_SHARED_FTLB_RAM; 1457 fallthrough; 1458 default: 1459 break; 1460 } 1461 1462 /* Recent MIPS cores use the implementation-dependent ExcCode 16 for 1463 * cache/FTLB parity exceptions. 1464 */ 1465 switch (__get_cpu_type(c->cputype)) { 1466 case CPU_PROAPTIV: 1467 case CPU_P5600: 1468 case CPU_P6600: 1469 case CPU_I6400: 1470 case CPU_I6500: 1471 c->options |= MIPS_CPU_FTLBPAREX; 1472 break; 1473 } 1474 } 1475 1476 static inline void cpu_probe_alchemy(struct cpuinfo_mips *c, unsigned int cpu) 1477 { 1478 decode_configs(c); 1479 switch (c->processor_id & PRID_IMP_MASK) { 1480 case PRID_IMP_AU1_REV1: 1481 case PRID_IMP_AU1_REV2: 1482 c->cputype = CPU_ALCHEMY; 1483 switch ((c->processor_id >> 24) & 0xff) { 1484 case 0: 1485 __cpu_name[cpu] = "Au1000"; 1486 break; 1487 case 1: 1488 __cpu_name[cpu] = "Au1500"; 1489 break; 1490 case 2: 1491 __cpu_name[cpu] = "Au1100"; 1492 break; 1493 case 3: 1494 __cpu_name[cpu] = "Au1550"; 1495 break; 1496 case 4: 1497 __cpu_name[cpu] = "Au1200"; 1498 if ((c->processor_id & PRID_REV_MASK) == 2) 1499 __cpu_name[cpu] = "Au1250"; 1500 break; 1501 case 5: 1502 __cpu_name[cpu] = "Au1210"; 1503 break; 1504 default: 1505 __cpu_name[cpu] = "Au1xxx"; 1506 break; 1507 } 1508 break; 1509 case PRID_IMP_NETLOGIC_AU13XX: 1510 c->cputype = CPU_ALCHEMY; 1511 __cpu_name[cpu] = "Au1300"; 1512 break; 1513 } 1514 } 1515 1516 static inline void cpu_probe_sibyte(struct cpuinfo_mips *c, unsigned int cpu) 1517 { 1518 decode_configs(c); 1519 1520 c->writecombine = _CACHE_UNCACHED_ACCELERATED; 1521 switch (c->processor_id & PRID_IMP_MASK) { 1522 case PRID_IMP_SB1: 1523 c->cputype = CPU_SB1; 1524 __cpu_name[cpu] = "SiByte SB1"; 1525 /* FPU in pass1 is known to have issues. */ 1526 if ((c->processor_id & PRID_REV_MASK) < 0x02) 1527 c->options &= ~(MIPS_CPU_FPU | MIPS_CPU_32FPR); 1528 break; 1529 case PRID_IMP_SB1A: 1530 c->cputype = CPU_SB1A; 1531 __cpu_name[cpu] = "SiByte SB1A"; 1532 break; 1533 } 1534 } 1535 1536 static inline void cpu_probe_sandcraft(struct cpuinfo_mips *c, unsigned int cpu) 1537 { 1538 decode_configs(c); 1539 switch (c->processor_id & PRID_IMP_MASK) { 1540 case PRID_IMP_SR71000: 1541 c->cputype = CPU_SR71000; 1542 __cpu_name[cpu] = "Sandcraft SR71000"; 1543 c->scache.ways = 8; 1544 c->tlbsize = 64; 1545 break; 1546 } 1547 } 1548 1549 static inline void cpu_probe_nxp(struct cpuinfo_mips *c, unsigned int cpu) 1550 { 1551 decode_configs(c); 1552 switch (c->processor_id & PRID_IMP_MASK) { 1553 case PRID_IMP_PR4450: 1554 c->cputype = CPU_PR4450; 1555 __cpu_name[cpu] = "Philips PR4450"; 1556 set_isa(c, MIPS_CPU_ISA_M32R1); 1557 break; 1558 } 1559 } 1560 1561 static inline void cpu_probe_broadcom(struct cpuinfo_mips *c, unsigned int cpu) 1562 { 1563 decode_configs(c); 1564 switch (c->processor_id & PRID_IMP_MASK) { 1565 case PRID_IMP_BMIPS32_REV4: 1566 case PRID_IMP_BMIPS32_REV8: 1567 c->cputype = CPU_BMIPS32; 1568 __cpu_name[cpu] = "Broadcom BMIPS32"; 1569 set_elf_platform(cpu, "bmips32"); 1570 break; 1571 case PRID_IMP_BMIPS3300: 1572 case PRID_IMP_BMIPS3300_ALT: 1573 case PRID_IMP_BMIPS3300_BUG: 1574 c->cputype = CPU_BMIPS3300; 1575 __cpu_name[cpu] = "Broadcom BMIPS3300"; 1576 set_elf_platform(cpu, "bmips3300"); 1577 reserve_exception_space(0x400, VECTORSPACING * 64); 1578 break; 1579 case PRID_IMP_BMIPS43XX: { 1580 int rev = c->processor_id & PRID_REV_MASK; 1581 1582 if (rev >= PRID_REV_BMIPS4380_LO && 1583 rev <= PRID_REV_BMIPS4380_HI) { 1584 c->cputype = CPU_BMIPS4380; 1585 __cpu_name[cpu] = "Broadcom BMIPS4380"; 1586 set_elf_platform(cpu, "bmips4380"); 1587 c->options |= MIPS_CPU_RIXI; 1588 reserve_exception_space(0x400, VECTORSPACING * 64); 1589 } else { 1590 c->cputype = CPU_BMIPS4350; 1591 __cpu_name[cpu] = "Broadcom BMIPS4350"; 1592 set_elf_platform(cpu, "bmips4350"); 1593 } 1594 break; 1595 } 1596 case PRID_IMP_BMIPS5000: 1597 case PRID_IMP_BMIPS5200: 1598 c->cputype = CPU_BMIPS5000; 1599 if ((c->processor_id & PRID_IMP_MASK) == PRID_IMP_BMIPS5200) 1600 __cpu_name[cpu] = "Broadcom BMIPS5200"; 1601 else 1602 __cpu_name[cpu] = "Broadcom BMIPS5000"; 1603 set_elf_platform(cpu, "bmips5000"); 1604 c->options |= MIPS_CPU_ULRI | MIPS_CPU_RIXI; 1605 reserve_exception_space(0x1000, VECTORSPACING * 64); 1606 break; 1607 } 1608 } 1609 1610 static inline void cpu_probe_cavium(struct cpuinfo_mips *c, unsigned int cpu) 1611 { 1612 decode_configs(c); 1613 /* Octeon has different cache interface */ 1614 c->options &= ~MIPS_CPU_4K_CACHE; 1615 switch (c->processor_id & PRID_IMP_MASK) { 1616 case PRID_IMP_CAVIUM_CN38XX: 1617 case PRID_IMP_CAVIUM_CN31XX: 1618 case PRID_IMP_CAVIUM_CN30XX: 1619 c->cputype = CPU_CAVIUM_OCTEON; 1620 __cpu_name[cpu] = "Cavium Octeon"; 1621 goto platform; 1622 case PRID_IMP_CAVIUM_CN58XX: 1623 case PRID_IMP_CAVIUM_CN56XX: 1624 case PRID_IMP_CAVIUM_CN50XX: 1625 case PRID_IMP_CAVIUM_CN52XX: 1626 c->cputype = CPU_CAVIUM_OCTEON_PLUS; 1627 __cpu_name[cpu] = "Cavium Octeon+"; 1628 platform: 1629 set_elf_platform(cpu, "octeon"); 1630 break; 1631 case PRID_IMP_CAVIUM_CN61XX: 1632 case PRID_IMP_CAVIUM_CN63XX: 1633 case PRID_IMP_CAVIUM_CN66XX: 1634 case PRID_IMP_CAVIUM_CN68XX: 1635 case PRID_IMP_CAVIUM_CNF71XX: 1636 c->cputype = CPU_CAVIUM_OCTEON2; 1637 __cpu_name[cpu] = "Cavium Octeon II"; 1638 set_elf_platform(cpu, "octeon2"); 1639 break; 1640 case PRID_IMP_CAVIUM_CN70XX: 1641 case PRID_IMP_CAVIUM_CN73XX: 1642 case PRID_IMP_CAVIUM_CNF75XX: 1643 case PRID_IMP_CAVIUM_CN78XX: 1644 c->cputype = CPU_CAVIUM_OCTEON3; 1645 __cpu_name[cpu] = "Cavium Octeon III"; 1646 set_elf_platform(cpu, "octeon3"); 1647 break; 1648 default: 1649 printk(KERN_INFO "Unknown Octeon chip!\n"); 1650 c->cputype = CPU_UNKNOWN; 1651 break; 1652 } 1653 } 1654 1655 #ifdef CONFIG_CPU_LOONGSON64 1656 #include <loongson_regs.h> 1657 1658 static inline void decode_cpucfg(struct cpuinfo_mips *c) 1659 { 1660 u32 cfg1 = read_cpucfg(LOONGSON_CFG1); 1661 u32 cfg2 = read_cpucfg(LOONGSON_CFG2); 1662 u32 cfg3 = read_cpucfg(LOONGSON_CFG3); 1663 1664 if (cfg1 & LOONGSON_CFG1_MMI) 1665 c->ases |= MIPS_ASE_LOONGSON_MMI; 1666 1667 if (cfg2 & LOONGSON_CFG2_LEXT1) 1668 c->ases |= MIPS_ASE_LOONGSON_EXT; 1669 1670 if (cfg2 & LOONGSON_CFG2_LEXT2) 1671 c->ases |= MIPS_ASE_LOONGSON_EXT2; 1672 1673 if (cfg2 & LOONGSON_CFG2_LSPW) { 1674 c->options |= MIPS_CPU_LDPTE; 1675 c->guest.options |= MIPS_CPU_LDPTE; 1676 } 1677 1678 if (cfg3 & LOONGSON_CFG3_LCAMP) 1679 c->ases |= MIPS_ASE_LOONGSON_CAM; 1680 } 1681 1682 static inline void cpu_probe_loongson(struct cpuinfo_mips *c, unsigned int cpu) 1683 { 1684 c->cputype = CPU_LOONGSON64; 1685 1686 /* All Loongson processors covered here define ExcCode 16 as GSExc. */ 1687 decode_configs(c); 1688 c->options |= MIPS_CPU_GSEXCEX; 1689 1690 switch (c->processor_id & PRID_IMP_MASK) { 1691 case PRID_IMP_LOONGSON_64R: /* Loongson-64 Reduced */ 1692 switch (c->processor_id & PRID_REV_MASK) { 1693 case PRID_REV_LOONGSON2K_R1_0: 1694 case PRID_REV_LOONGSON2K_R1_1: 1695 case PRID_REV_LOONGSON2K_R1_2: 1696 case PRID_REV_LOONGSON2K_R1_3: 1697 __cpu_name[cpu] = "Loongson-2K"; 1698 set_elf_platform(cpu, "gs264e"); 1699 set_isa(c, MIPS_CPU_ISA_M64R2); 1700 break; 1701 } 1702 c->ases |= (MIPS_ASE_LOONGSON_MMI | MIPS_ASE_LOONGSON_EXT | 1703 MIPS_ASE_LOONGSON_EXT2); 1704 break; 1705 case PRID_IMP_LOONGSON_64C: /* Loongson-3 Classic */ 1706 switch (c->processor_id & PRID_REV_MASK) { 1707 case PRID_REV_LOONGSON3A_R2_0: 1708 case PRID_REV_LOONGSON3A_R2_1: 1709 __cpu_name[cpu] = "ICT Loongson-3"; 1710 set_elf_platform(cpu, "loongson3a"); 1711 set_isa(c, MIPS_CPU_ISA_M64R2); 1712 break; 1713 case PRID_REV_LOONGSON3A_R3_0: 1714 case PRID_REV_LOONGSON3A_R3_1: 1715 __cpu_name[cpu] = "ICT Loongson-3"; 1716 set_elf_platform(cpu, "loongson3a"); 1717 set_isa(c, MIPS_CPU_ISA_M64R2); 1718 break; 1719 } 1720 /* 1721 * Loongson-3 Classic did not implement MIPS standard TLBINV 1722 * but implemented TLBINVF and EHINV. As currently we're only 1723 * using these two features, enable MIPS_CPU_TLBINV as well. 1724 * 1725 * Also some early Loongson-3A2000 had wrong TLB type in Config 1726 * register, we correct it here. 1727 */ 1728 c->options |= MIPS_CPU_FTLB | MIPS_CPU_TLBINV | MIPS_CPU_LDPTE; 1729 c->ases |= (MIPS_ASE_LOONGSON_MMI | MIPS_ASE_LOONGSON_CAM | 1730 MIPS_ASE_LOONGSON_EXT | MIPS_ASE_LOONGSON_EXT2); 1731 c->ases &= ~MIPS_ASE_VZ; /* VZ of Loongson-3A2000/3000 is incomplete */ 1732 change_c0_config6(LOONGSON_CONF6_EXTIMER | LOONGSON_CONF6_INTIMER, 1733 LOONGSON_CONF6_INTIMER); 1734 break; 1735 case PRID_IMP_LOONGSON_64G: 1736 __cpu_name[cpu] = "ICT Loongson-3"; 1737 set_elf_platform(cpu, "loongson3a"); 1738 set_isa(c, MIPS_CPU_ISA_M64R2); 1739 decode_cpucfg(c); 1740 change_c0_config6(LOONGSON_CONF6_EXTIMER | LOONGSON_CONF6_INTIMER, 1741 LOONGSON_CONF6_INTIMER); 1742 break; 1743 default: 1744 panic("Unknown Loongson Processor ID!"); 1745 break; 1746 } 1747 } 1748 #else 1749 static inline void cpu_probe_loongson(struct cpuinfo_mips *c, unsigned int cpu) { } 1750 #endif 1751 1752 static inline void cpu_probe_ingenic(struct cpuinfo_mips *c, unsigned int cpu) 1753 { 1754 decode_configs(c); 1755 1756 /* 1757 * XBurst misses a config2 register, so config3 decode was skipped in 1758 * decode_configs(). 1759 */ 1760 decode_config3(c); 1761 1762 /* XBurst does not implement the CP0 counter. */ 1763 c->options &= ~MIPS_CPU_COUNTER; 1764 BUG_ON(__builtin_constant_p(cpu_has_counter) && cpu_has_counter); 1765 1766 /* XBurst has virtually tagged icache */ 1767 c->icache.flags |= MIPS_CACHE_VTAG; 1768 1769 switch (c->processor_id & PRID_IMP_MASK) { 1770 1771 /* XBurst®1 with MXU1.0/MXU1.1 SIMD ISA */ 1772 case PRID_IMP_XBURST_REV1: 1773 1774 /* 1775 * The XBurst core by default attempts to avoid branch target 1776 * buffer lookups by detecting & special casing loops. This 1777 * feature will cause BogoMIPS and lpj calculate in error. 1778 * Set cp0 config7 bit 4 to disable this feature. 1779 */ 1780 set_c0_config7(MIPS_CONF7_BTB_LOOP_EN); 1781 1782 switch (c->processor_id & PRID_COMP_MASK) { 1783 1784 /* 1785 * The config0 register in the XBurst CPUs with a processor ID of 1786 * PRID_COMP_INGENIC_D0 report themselves as MIPS32r2 compatible, 1787 * but they don't actually support this ISA. 1788 */ 1789 case PRID_COMP_INGENIC_D0: 1790 c->isa_level &= ~MIPS_CPU_ISA_M32R2; 1791 1792 /* FPU is not properly detected on JZ4760(B). */ 1793 if (c->processor_id == 0x2ed0024f) 1794 c->options |= MIPS_CPU_FPU; 1795 1796 fallthrough; 1797 1798 /* 1799 * The config0 register in the XBurst CPUs with a processor ID of 1800 * PRID_COMP_INGENIC_D0 or PRID_COMP_INGENIC_D1 has an abandoned 1801 * huge page tlb mode, this mode is not compatible with the MIPS 1802 * standard, it will cause tlbmiss and into an infinite loop 1803 * (line 21 in the tlb-funcs.S) when starting the init process. 1804 * After chip reset, the default is HPTLB mode, Write 0xa9000000 1805 * to cp0 register 5 sel 4 to switch back to VTLB mode to prevent 1806 * getting stuck. 1807 */ 1808 case PRID_COMP_INGENIC_D1: 1809 write_c0_page_ctrl(XBURST_PAGECTRL_HPTLB_DIS); 1810 break; 1811 1812 default: 1813 break; 1814 } 1815 fallthrough; 1816 1817 /* XBurst®1 with MXU2.0 SIMD ISA */ 1818 case PRID_IMP_XBURST_REV2: 1819 /* Ingenic uses the WA bit to achieve write-combine memory writes */ 1820 c->writecombine = _CACHE_CACHABLE_WA; 1821 c->cputype = CPU_XBURST; 1822 __cpu_name[cpu] = "Ingenic XBurst"; 1823 break; 1824 1825 /* XBurst®2 with MXU2.1 SIMD ISA */ 1826 case PRID_IMP_XBURST2: 1827 c->cputype = CPU_XBURST; 1828 __cpu_name[cpu] = "Ingenic XBurst II"; 1829 break; 1830 1831 default: 1832 panic("Unknown Ingenic Processor ID!"); 1833 break; 1834 } 1835 } 1836 1837 #ifdef CONFIG_64BIT 1838 /* For use by uaccess.h */ 1839 u64 __ua_limit; 1840 EXPORT_SYMBOL(__ua_limit); 1841 #endif 1842 1843 const char *__cpu_name[NR_CPUS]; 1844 const char *__elf_platform; 1845 const char *__elf_base_platform; 1846 1847 void cpu_probe(void) 1848 { 1849 struct cpuinfo_mips *c = ¤t_cpu_data; 1850 unsigned int cpu = smp_processor_id(); 1851 1852 /* 1853 * Set a default elf platform, cpu probe may later 1854 * overwrite it with a more precise value 1855 */ 1856 set_elf_platform(cpu, "mips"); 1857 1858 c->processor_id = PRID_IMP_UNKNOWN; 1859 c->fpu_id = FPIR_IMP_NONE; 1860 c->cputype = CPU_UNKNOWN; 1861 c->writecombine = _CACHE_UNCACHED; 1862 1863 c->fpu_csr31 = FPU_CSR_RN; 1864 c->fpu_msk31 = FPU_CSR_RSVD | FPU_CSR_ABS2008 | FPU_CSR_NAN2008; 1865 1866 c->processor_id = read_c0_prid(); 1867 switch (c->processor_id & PRID_COMP_MASK) { 1868 case PRID_COMP_LEGACY: 1869 cpu_probe_legacy(c, cpu); 1870 break; 1871 case PRID_COMP_MIPS: 1872 cpu_probe_mips(c, cpu); 1873 break; 1874 case PRID_COMP_ALCHEMY: 1875 case PRID_COMP_NETLOGIC: 1876 cpu_probe_alchemy(c, cpu); 1877 break; 1878 case PRID_COMP_SIBYTE: 1879 cpu_probe_sibyte(c, cpu); 1880 break; 1881 case PRID_COMP_BROADCOM: 1882 cpu_probe_broadcom(c, cpu); 1883 break; 1884 case PRID_COMP_SANDCRAFT: 1885 cpu_probe_sandcraft(c, cpu); 1886 break; 1887 case PRID_COMP_NXP: 1888 cpu_probe_nxp(c, cpu); 1889 break; 1890 case PRID_COMP_CAVIUM: 1891 cpu_probe_cavium(c, cpu); 1892 break; 1893 case PRID_COMP_LOONGSON: 1894 cpu_probe_loongson(c, cpu); 1895 break; 1896 case PRID_COMP_INGENIC_13: 1897 case PRID_COMP_INGENIC_D0: 1898 case PRID_COMP_INGENIC_D1: 1899 case PRID_COMP_INGENIC_E1: 1900 cpu_probe_ingenic(c, cpu); 1901 break; 1902 } 1903 1904 BUG_ON(!__cpu_name[cpu]); 1905 BUG_ON(c->cputype == CPU_UNKNOWN); 1906 1907 /* 1908 * Platform code can force the cpu type to optimize code 1909 * generation. In that case be sure the cpu type is correctly 1910 * manually setup otherwise it could trigger some nasty bugs. 1911 */ 1912 BUG_ON(current_cpu_type() != c->cputype); 1913 1914 if (cpu_has_rixi) { 1915 /* Enable the RIXI exceptions */ 1916 set_c0_pagegrain(PG_IEC); 1917 back_to_back_c0_hazard(); 1918 /* Verify the IEC bit is set */ 1919 if (read_c0_pagegrain() & PG_IEC) 1920 c->options |= MIPS_CPU_RIXIEX; 1921 } 1922 1923 if (mips_fpu_disabled) 1924 c->options &= ~MIPS_CPU_FPU; 1925 1926 if (mips_dsp_disabled) 1927 c->ases &= ~(MIPS_ASE_DSP | MIPS_ASE_DSP2P); 1928 1929 if (mips_htw_disabled) { 1930 c->options &= ~MIPS_CPU_HTW; 1931 write_c0_pwctl(read_c0_pwctl() & 1932 ~(1 << MIPS_PWCTL_PWEN_SHIFT)); 1933 } 1934 1935 if (c->options & MIPS_CPU_FPU) 1936 cpu_set_fpu_opts(c); 1937 else 1938 cpu_set_nofpu_opts(c); 1939 1940 if (cpu_has_mips_r2_r6) { 1941 c->srsets = ((read_c0_srsctl() >> 26) & 0x0f) + 1; 1942 /* R2 has Performance Counter Interrupt indicator */ 1943 c->options |= MIPS_CPU_PCI; 1944 } 1945 else 1946 c->srsets = 1; 1947 1948 if (cpu_has_mips_r6) 1949 elf_hwcap |= HWCAP_MIPS_R6; 1950 1951 if (cpu_has_msa) { 1952 c->msa_id = cpu_get_msa_id(); 1953 WARN(c->msa_id & MSA_IR_WRPF, 1954 "Vector register partitioning unimplemented!"); 1955 elf_hwcap |= HWCAP_MIPS_MSA; 1956 } 1957 1958 if (cpu_has_mips16) 1959 elf_hwcap |= HWCAP_MIPS_MIPS16; 1960 1961 if (cpu_has_mdmx) 1962 elf_hwcap |= HWCAP_MIPS_MDMX; 1963 1964 if (cpu_has_mips3d) 1965 elf_hwcap |= HWCAP_MIPS_MIPS3D; 1966 1967 if (cpu_has_smartmips) 1968 elf_hwcap |= HWCAP_MIPS_SMARTMIPS; 1969 1970 if (cpu_has_dsp) 1971 elf_hwcap |= HWCAP_MIPS_DSP; 1972 1973 if (cpu_has_dsp2) 1974 elf_hwcap |= HWCAP_MIPS_DSP2; 1975 1976 if (cpu_has_dsp3) 1977 elf_hwcap |= HWCAP_MIPS_DSP3; 1978 1979 if (cpu_has_mips16e2) 1980 elf_hwcap |= HWCAP_MIPS_MIPS16E2; 1981 1982 if (cpu_has_loongson_mmi) 1983 elf_hwcap |= HWCAP_LOONGSON_MMI; 1984 1985 if (cpu_has_loongson_ext) 1986 elf_hwcap |= HWCAP_LOONGSON_EXT; 1987 1988 if (cpu_has_loongson_ext2) 1989 elf_hwcap |= HWCAP_LOONGSON_EXT2; 1990 1991 if (cpu_has_vz) 1992 cpu_probe_vz(c); 1993 1994 cpu_probe_vmbits(c); 1995 1996 /* Synthesize CPUCFG data if running on Loongson processors; 1997 * no-op otherwise. 1998 * 1999 * This looks at previously probed features, so keep this at bottom. 2000 */ 2001 loongson3_cpucfg_synthesize_data(c); 2002 2003 #ifdef CONFIG_64BIT 2004 if (cpu == 0) 2005 __ua_limit = ~((1ull << cpu_vmbits) - 1); 2006 #endif 2007 2008 reserve_exception_space(0, 0x1000); 2009 } 2010 2011 void cpu_report(void) 2012 { 2013 struct cpuinfo_mips *c = ¤t_cpu_data; 2014 2015 pr_info("CPU%d revision is: %08x (%s)\n", 2016 smp_processor_id(), c->processor_id, cpu_name_string()); 2017 if (c->options & MIPS_CPU_FPU) 2018 printk(KERN_INFO "FPU revision is: %08x\n", c->fpu_id); 2019 if (cpu_has_msa) 2020 pr_info("MSA revision is: %08x\n", c->msa_id); 2021 } 2022 2023 void cpu_set_cluster(struct cpuinfo_mips *cpuinfo, unsigned int cluster) 2024 { 2025 /* Ensure the core number fits in the field */ 2026 WARN_ON(cluster > (MIPS_GLOBALNUMBER_CLUSTER >> 2027 MIPS_GLOBALNUMBER_CLUSTER_SHF)); 2028 2029 cpuinfo->globalnumber &= ~MIPS_GLOBALNUMBER_CLUSTER; 2030 cpuinfo->globalnumber |= cluster << MIPS_GLOBALNUMBER_CLUSTER_SHF; 2031 } 2032 2033 void cpu_set_core(struct cpuinfo_mips *cpuinfo, unsigned int core) 2034 { 2035 /* Ensure the core number fits in the field */ 2036 WARN_ON(core > (MIPS_GLOBALNUMBER_CORE >> MIPS_GLOBALNUMBER_CORE_SHF)); 2037 2038 cpuinfo->globalnumber &= ~MIPS_GLOBALNUMBER_CORE; 2039 cpuinfo->globalnumber |= core << MIPS_GLOBALNUMBER_CORE_SHF; 2040 } 2041 2042 void cpu_set_vpe_id(struct cpuinfo_mips *cpuinfo, unsigned int vpe) 2043 { 2044 /* Ensure the VP(E) ID fits in the field */ 2045 WARN_ON(vpe > (MIPS_GLOBALNUMBER_VP >> MIPS_GLOBALNUMBER_VP_SHF)); 2046 2047 /* Ensure we're not using VP(E)s without support */ 2048 WARN_ON(vpe && !IS_ENABLED(CONFIG_MIPS_MT_SMP) && 2049 !IS_ENABLED(CONFIG_CPU_MIPSR6)); 2050 2051 cpuinfo->globalnumber &= ~MIPS_GLOBALNUMBER_VP; 2052 cpuinfo->globalnumber |= vpe << MIPS_GLOBALNUMBER_VP_SHF; 2053 } 2054 2055 void cpu_disable_mmid(void) 2056 { 2057 int i; 2058 unsigned long asid_mask; 2059 unsigned int cpu = smp_processor_id(); 2060 struct cpuinfo_mips *c = ¤t_cpu_data; 2061 unsigned int config4 = read_c0_config4(); 2062 unsigned int config5 = read_c0_config5(); 2063 2064 /* Setup the initial ASID mask based on config4 */ 2065 asid_mask = MIPS_ENTRYHI_ASID; 2066 if (config4 & MIPS_CONF4_AE) 2067 asid_mask |= MIPS_ENTRYHI_ASIDX; 2068 set_cpu_asid_mask(c, asid_mask); 2069 2070 /* Disable MMID in the C0 and update cpuinfo_mips accordingly */ 2071 config5 &= ~(MIPS_CONF5_UFR | MIPS_CONF5_UFE); 2072 config5 &= ~MIPS_CONF5_MI; 2073 write_c0_config5(config5); 2074 /* Ensure the write to config5 above takes effect */ 2075 back_to_back_c0_hazard(); 2076 c->options &= ~MIPS_CPU_MMID; 2077 2078 /* Setup asid cache value cleared in per_cpu_trap_init() */ 2079 cpu_data[cpu].asid_cache = asid_first_version(cpu); 2080 2081 /* Reinit context for each CPU */ 2082 for_each_possible_cpu(i) 2083 set_cpu_context(i, &init_mm, 0); 2084 2085 /* Ensure that now MMID will be seen as disable */ 2086 mmid_disabled_quirk = true; 2087 2088 pr_info("MMID support disabled due to hardware support issue\n"); 2089 } 2090