1 /* 2 * Processor capabilities determination functions. 3 * 4 * Copyright (C) xxxx the Anonymous 5 * Copyright (C) 1994 - 2006 Ralf Baechle 6 * Copyright (C) 2003, 2004 Maciej W. Rozycki 7 * Copyright (C) 2001, 2004 MIPS Inc. 8 * 9 * This program is free software; you can redistribute it and/or 10 * modify it under the terms of the GNU General Public License 11 * as published by the Free Software Foundation; either version 12 * 2 of the License, or (at your option) any later version. 13 */ 14 #include <linux/init.h> 15 #include <linux/kernel.h> 16 #include <linux/ptrace.h> 17 #include <linux/stddef.h> 18 19 #include <asm/bugs.h> 20 #include <asm/cpu.h> 21 #include <asm/fpu.h> 22 #include <asm/mipsregs.h> 23 #include <asm/system.h> 24 #include <asm/watch.h> 25 26 /* 27 * Not all of the MIPS CPUs have the "wait" instruction available. Moreover, 28 * the implementation of the "wait" feature differs between CPU families. This 29 * points to the function that implements CPU specific wait. 30 * The wait instruction stops the pipeline and reduces the power consumption of 31 * the CPU very much. 32 */ 33 void (*cpu_wait)(void) = NULL; 34 35 static void r3081_wait(void) 36 { 37 unsigned long cfg = read_c0_conf(); 38 write_c0_conf(cfg | R30XX_CONF_HALT); 39 } 40 41 static void r39xx_wait(void) 42 { 43 local_irq_disable(); 44 if (!need_resched()) 45 write_c0_conf(read_c0_conf() | TX39_CONF_HALT); 46 local_irq_enable(); 47 } 48 49 extern void r4k_wait(void); 50 51 /* 52 * This variant is preferable as it allows testing need_resched and going to 53 * sleep depending on the outcome atomically. Unfortunately the "It is 54 * implementation-dependent whether the pipeline restarts when a non-enabled 55 * interrupt is requested" restriction in the MIPS32/MIPS64 architecture makes 56 * using this version a gamble. 57 */ 58 void r4k_wait_irqoff(void) 59 { 60 local_irq_disable(); 61 if (!need_resched()) 62 __asm__(" .set push \n" 63 " .set mips3 \n" 64 " wait \n" 65 " .set pop \n"); 66 local_irq_enable(); 67 __asm__(" .globl __pastwait \n" 68 "__pastwait: \n"); 69 return; 70 } 71 72 /* 73 * The RM7000 variant has to handle erratum 38. The workaround is to not 74 * have any pending stores when the WAIT instruction is executed. 75 */ 76 static void rm7k_wait_irqoff(void) 77 { 78 local_irq_disable(); 79 if (!need_resched()) 80 __asm__( 81 " .set push \n" 82 " .set mips3 \n" 83 " .set noat \n" 84 " mfc0 $1, $12 \n" 85 " sync \n" 86 " mtc0 $1, $12 # stalls until W stage \n" 87 " wait \n" 88 " mtc0 $1, $12 # stalls until W stage \n" 89 " .set pop \n"); 90 local_irq_enable(); 91 } 92 93 /* The Au1xxx wait is available only if using 32khz counter or 94 * external timer source, but specifically not CP0 Counter. */ 95 int allow_au1k_wait; 96 97 static void au1k_wait(void) 98 { 99 /* using the wait instruction makes CP0 counter unusable */ 100 __asm__(" .set mips3 \n" 101 " cache 0x14, 0(%0) \n" 102 " cache 0x14, 32(%0) \n" 103 " sync \n" 104 " nop \n" 105 " wait \n" 106 " nop \n" 107 " nop \n" 108 " nop \n" 109 " nop \n" 110 " .set mips0 \n" 111 : : "r" (au1k_wait)); 112 } 113 114 static int __initdata nowait = 0; 115 116 static int __init wait_disable(char *s) 117 { 118 nowait = 1; 119 120 return 1; 121 } 122 123 __setup("nowait", wait_disable); 124 125 void __init check_wait(void) 126 { 127 struct cpuinfo_mips *c = ¤t_cpu_data; 128 129 if (nowait) { 130 printk("Wait instruction disabled.\n"); 131 return; 132 } 133 134 switch (c->cputype) { 135 case CPU_R3081: 136 case CPU_R3081E: 137 cpu_wait = r3081_wait; 138 break; 139 case CPU_TX3927: 140 cpu_wait = r39xx_wait; 141 break; 142 case CPU_R4200: 143 /* case CPU_R4300: */ 144 case CPU_R4600: 145 case CPU_R4640: 146 case CPU_R4650: 147 case CPU_R4700: 148 case CPU_R5000: 149 case CPU_NEVADA: 150 case CPU_4KC: 151 case CPU_4KEC: 152 case CPU_4KSC: 153 case CPU_5KC: 154 case CPU_25KF: 155 case CPU_PR4450: 156 case CPU_BCM3302: 157 cpu_wait = r4k_wait; 158 break; 159 160 case CPU_RM7000: 161 cpu_wait = rm7k_wait_irqoff; 162 break; 163 164 case CPU_24K: 165 case CPU_34K: 166 case CPU_1004K: 167 cpu_wait = r4k_wait; 168 if (read_c0_config7() & MIPS_CONF7_WII) 169 cpu_wait = r4k_wait_irqoff; 170 break; 171 172 case CPU_74K: 173 cpu_wait = r4k_wait; 174 if ((c->processor_id & 0xff) >= PRID_REV_ENCODE_332(2, 1, 0)) 175 cpu_wait = r4k_wait_irqoff; 176 break; 177 178 case CPU_TX49XX: 179 cpu_wait = r4k_wait_irqoff; 180 break; 181 case CPU_AU1000: 182 case CPU_AU1100: 183 case CPU_AU1500: 184 case CPU_AU1550: 185 case CPU_AU1200: 186 case CPU_AU1210: 187 case CPU_AU1250: 188 if (allow_au1k_wait) 189 cpu_wait = au1k_wait; 190 break; 191 case CPU_20KC: 192 /* 193 * WAIT on Rev1.0 has E1, E2, E3 and E16. 194 * WAIT on Rev2.0 and Rev3.0 has E16. 195 * Rev3.1 WAIT is nop, why bother 196 */ 197 if ((c->processor_id & 0xff) <= 0x64) 198 break; 199 200 /* 201 * Another rev is incremeting c0_count at a reduced clock 202 * rate while in WAIT mode. So we basically have the choice 203 * between using the cp0 timer as clocksource or avoiding 204 * the WAIT instruction. Until more details are known, 205 * disable the use of WAIT for 20Kc entirely. 206 cpu_wait = r4k_wait; 207 */ 208 break; 209 case CPU_RM9000: 210 if ((c->processor_id & 0x00ff) >= 0x40) 211 cpu_wait = r4k_wait; 212 break; 213 default: 214 break; 215 } 216 } 217 218 static inline void check_errata(void) 219 { 220 struct cpuinfo_mips *c = ¤t_cpu_data; 221 222 switch (c->cputype) { 223 case CPU_34K: 224 /* 225 * Erratum "RPS May Cause Incorrect Instruction Execution" 226 * This code only handles VPE0, any SMP/SMTC/RTOS code 227 * making use of VPE1 will be responsable for that VPE. 228 */ 229 if ((c->processor_id & PRID_REV_MASK) <= PRID_REV_34K_V1_0_2) 230 write_c0_config7(read_c0_config7() | MIPS_CONF7_RPS); 231 break; 232 default: 233 break; 234 } 235 } 236 237 void __init check_bugs32(void) 238 { 239 check_errata(); 240 } 241 242 /* 243 * Probe whether cpu has config register by trying to play with 244 * alternate cache bit and see whether it matters. 245 * It's used by cpu_probe to distinguish between R3000A and R3081. 246 */ 247 static inline int cpu_has_confreg(void) 248 { 249 #ifdef CONFIG_CPU_R3000 250 extern unsigned long r3k_cache_size(unsigned long); 251 unsigned long size1, size2; 252 unsigned long cfg = read_c0_conf(); 253 254 size1 = r3k_cache_size(ST0_ISC); 255 write_c0_conf(cfg ^ R30XX_CONF_AC); 256 size2 = r3k_cache_size(ST0_ISC); 257 write_c0_conf(cfg); 258 return size1 != size2; 259 #else 260 return 0; 261 #endif 262 } 263 264 /* 265 * Get the FPU Implementation/Revision. 266 */ 267 static inline unsigned long cpu_get_fpu_id(void) 268 { 269 unsigned long tmp, fpu_id; 270 271 tmp = read_c0_status(); 272 __enable_fpu(); 273 fpu_id = read_32bit_cp1_register(CP1_REVISION); 274 write_c0_status(tmp); 275 return fpu_id; 276 } 277 278 /* 279 * Check the CPU has an FPU the official way. 280 */ 281 static inline int __cpu_has_fpu(void) 282 { 283 return ((cpu_get_fpu_id() & 0xff00) != FPIR_IMP_NONE); 284 } 285 286 #define R4K_OPTS (MIPS_CPU_TLB | MIPS_CPU_4KEX | MIPS_CPU_4K_CACHE \ 287 | MIPS_CPU_COUNTER) 288 289 static inline void cpu_probe_legacy(struct cpuinfo_mips *c) 290 { 291 switch (c->processor_id & 0xff00) { 292 case PRID_IMP_R2000: 293 c->cputype = CPU_R2000; 294 c->isa_level = MIPS_CPU_ISA_I; 295 c->options = MIPS_CPU_TLB | MIPS_CPU_3K_CACHE | 296 MIPS_CPU_NOFPUEX; 297 if (__cpu_has_fpu()) 298 c->options |= MIPS_CPU_FPU; 299 c->tlbsize = 64; 300 break; 301 case PRID_IMP_R3000: 302 if ((c->processor_id & 0xff) == PRID_REV_R3000A) 303 if (cpu_has_confreg()) 304 c->cputype = CPU_R3081E; 305 else 306 c->cputype = CPU_R3000A; 307 else 308 c->cputype = CPU_R3000; 309 c->isa_level = MIPS_CPU_ISA_I; 310 c->options = MIPS_CPU_TLB | MIPS_CPU_3K_CACHE | 311 MIPS_CPU_NOFPUEX; 312 if (__cpu_has_fpu()) 313 c->options |= MIPS_CPU_FPU; 314 c->tlbsize = 64; 315 break; 316 case PRID_IMP_R4000: 317 if (read_c0_config() & CONF_SC) { 318 if ((c->processor_id & 0xff) >= PRID_REV_R4400) 319 c->cputype = CPU_R4400PC; 320 else 321 c->cputype = CPU_R4000PC; 322 } else { 323 if ((c->processor_id & 0xff) >= PRID_REV_R4400) 324 c->cputype = CPU_R4400SC; 325 else 326 c->cputype = CPU_R4000SC; 327 } 328 329 c->isa_level = MIPS_CPU_ISA_III; 330 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR | 331 MIPS_CPU_WATCH | MIPS_CPU_VCE | 332 MIPS_CPU_LLSC; 333 c->tlbsize = 48; 334 break; 335 case PRID_IMP_VR41XX: 336 switch (c->processor_id & 0xf0) { 337 case PRID_REV_VR4111: 338 c->cputype = CPU_VR4111; 339 break; 340 case PRID_REV_VR4121: 341 c->cputype = CPU_VR4121; 342 break; 343 case PRID_REV_VR4122: 344 if ((c->processor_id & 0xf) < 0x3) 345 c->cputype = CPU_VR4122; 346 else 347 c->cputype = CPU_VR4181A; 348 break; 349 case PRID_REV_VR4130: 350 if ((c->processor_id & 0xf) < 0x4) 351 c->cputype = CPU_VR4131; 352 else 353 c->cputype = CPU_VR4133; 354 break; 355 default: 356 printk(KERN_INFO "Unexpected CPU of NEC VR4100 series\n"); 357 c->cputype = CPU_VR41XX; 358 break; 359 } 360 c->isa_level = MIPS_CPU_ISA_III; 361 c->options = R4K_OPTS; 362 c->tlbsize = 32; 363 break; 364 case PRID_IMP_R4300: 365 c->cputype = CPU_R4300; 366 c->isa_level = MIPS_CPU_ISA_III; 367 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR | 368 MIPS_CPU_LLSC; 369 c->tlbsize = 32; 370 break; 371 case PRID_IMP_R4600: 372 c->cputype = CPU_R4600; 373 c->isa_level = MIPS_CPU_ISA_III; 374 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR | 375 MIPS_CPU_LLSC; 376 c->tlbsize = 48; 377 break; 378 #if 0 379 case PRID_IMP_R4650: 380 /* 381 * This processor doesn't have an MMU, so it's not 382 * "real easy" to run Linux on it. It is left purely 383 * for documentation. Commented out because it shares 384 * it's c0_prid id number with the TX3900. 385 */ 386 c->cputype = CPU_R4650; 387 c->isa_level = MIPS_CPU_ISA_III; 388 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_LLSC; 389 c->tlbsize = 48; 390 break; 391 #endif 392 case PRID_IMP_TX39: 393 c->isa_level = MIPS_CPU_ISA_I; 394 c->options = MIPS_CPU_TLB | MIPS_CPU_TX39_CACHE; 395 396 if ((c->processor_id & 0xf0) == (PRID_REV_TX3927 & 0xf0)) { 397 c->cputype = CPU_TX3927; 398 c->tlbsize = 64; 399 } else { 400 switch (c->processor_id & 0xff) { 401 case PRID_REV_TX3912: 402 c->cputype = CPU_TX3912; 403 c->tlbsize = 32; 404 break; 405 case PRID_REV_TX3922: 406 c->cputype = CPU_TX3922; 407 c->tlbsize = 64; 408 break; 409 default: 410 c->cputype = CPU_UNKNOWN; 411 break; 412 } 413 } 414 break; 415 case PRID_IMP_R4700: 416 c->cputype = CPU_R4700; 417 c->isa_level = MIPS_CPU_ISA_III; 418 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR | 419 MIPS_CPU_LLSC; 420 c->tlbsize = 48; 421 break; 422 case PRID_IMP_TX49: 423 c->cputype = CPU_TX49XX; 424 c->isa_level = MIPS_CPU_ISA_III; 425 c->options = R4K_OPTS | MIPS_CPU_LLSC; 426 if (!(c->processor_id & 0x08)) 427 c->options |= MIPS_CPU_FPU | MIPS_CPU_32FPR; 428 c->tlbsize = 48; 429 break; 430 case PRID_IMP_R5000: 431 c->cputype = CPU_R5000; 432 c->isa_level = MIPS_CPU_ISA_IV; 433 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR | 434 MIPS_CPU_LLSC; 435 c->tlbsize = 48; 436 break; 437 case PRID_IMP_R5432: 438 c->cputype = CPU_R5432; 439 c->isa_level = MIPS_CPU_ISA_IV; 440 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR | 441 MIPS_CPU_WATCH | MIPS_CPU_LLSC; 442 c->tlbsize = 48; 443 break; 444 case PRID_IMP_R5500: 445 c->cputype = CPU_R5500; 446 c->isa_level = MIPS_CPU_ISA_IV; 447 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR | 448 MIPS_CPU_WATCH | MIPS_CPU_LLSC; 449 c->tlbsize = 48; 450 break; 451 case PRID_IMP_NEVADA: 452 c->cputype = CPU_NEVADA; 453 c->isa_level = MIPS_CPU_ISA_IV; 454 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR | 455 MIPS_CPU_DIVEC | MIPS_CPU_LLSC; 456 c->tlbsize = 48; 457 break; 458 case PRID_IMP_R6000: 459 c->cputype = CPU_R6000; 460 c->isa_level = MIPS_CPU_ISA_II; 461 c->options = MIPS_CPU_TLB | MIPS_CPU_FPU | 462 MIPS_CPU_LLSC; 463 c->tlbsize = 32; 464 break; 465 case PRID_IMP_R6000A: 466 c->cputype = CPU_R6000A; 467 c->isa_level = MIPS_CPU_ISA_II; 468 c->options = MIPS_CPU_TLB | MIPS_CPU_FPU | 469 MIPS_CPU_LLSC; 470 c->tlbsize = 32; 471 break; 472 case PRID_IMP_RM7000: 473 c->cputype = CPU_RM7000; 474 c->isa_level = MIPS_CPU_ISA_IV; 475 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR | 476 MIPS_CPU_LLSC; 477 /* 478 * Undocumented RM7000: Bit 29 in the info register of 479 * the RM7000 v2.0 indicates if the TLB has 48 or 64 480 * entries. 481 * 482 * 29 1 => 64 entry JTLB 483 * 0 => 48 entry JTLB 484 */ 485 c->tlbsize = (read_c0_info() & (1 << 29)) ? 64 : 48; 486 break; 487 case PRID_IMP_RM9000: 488 c->cputype = CPU_RM9000; 489 c->isa_level = MIPS_CPU_ISA_IV; 490 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR | 491 MIPS_CPU_LLSC; 492 /* 493 * Bit 29 in the info register of the RM9000 494 * indicates if the TLB has 48 or 64 entries. 495 * 496 * 29 1 => 64 entry JTLB 497 * 0 => 48 entry JTLB 498 */ 499 c->tlbsize = (read_c0_info() & (1 << 29)) ? 64 : 48; 500 break; 501 case PRID_IMP_R8000: 502 c->cputype = CPU_R8000; 503 c->isa_level = MIPS_CPU_ISA_IV; 504 c->options = MIPS_CPU_TLB | MIPS_CPU_4KEX | 505 MIPS_CPU_FPU | MIPS_CPU_32FPR | 506 MIPS_CPU_LLSC; 507 c->tlbsize = 384; /* has weird TLB: 3-way x 128 */ 508 break; 509 case PRID_IMP_R10000: 510 c->cputype = CPU_R10000; 511 c->isa_level = MIPS_CPU_ISA_IV; 512 c->options = MIPS_CPU_TLB | MIPS_CPU_4K_CACHE | MIPS_CPU_4KEX | 513 MIPS_CPU_FPU | MIPS_CPU_32FPR | 514 MIPS_CPU_COUNTER | MIPS_CPU_WATCH | 515 MIPS_CPU_LLSC; 516 c->tlbsize = 64; 517 break; 518 case PRID_IMP_R12000: 519 c->cputype = CPU_R12000; 520 c->isa_level = MIPS_CPU_ISA_IV; 521 c->options = MIPS_CPU_TLB | MIPS_CPU_4K_CACHE | MIPS_CPU_4KEX | 522 MIPS_CPU_FPU | MIPS_CPU_32FPR | 523 MIPS_CPU_COUNTER | MIPS_CPU_WATCH | 524 MIPS_CPU_LLSC; 525 c->tlbsize = 64; 526 break; 527 case PRID_IMP_R14000: 528 c->cputype = CPU_R14000; 529 c->isa_level = MIPS_CPU_ISA_IV; 530 c->options = MIPS_CPU_TLB | MIPS_CPU_4K_CACHE | MIPS_CPU_4KEX | 531 MIPS_CPU_FPU | MIPS_CPU_32FPR | 532 MIPS_CPU_COUNTER | MIPS_CPU_WATCH | 533 MIPS_CPU_LLSC; 534 c->tlbsize = 64; 535 break; 536 case PRID_IMP_LOONGSON2: 537 c->cputype = CPU_LOONGSON2; 538 c->isa_level = MIPS_CPU_ISA_III; 539 c->options = R4K_OPTS | 540 MIPS_CPU_FPU | MIPS_CPU_LLSC | 541 MIPS_CPU_32FPR; 542 c->tlbsize = 64; 543 break; 544 } 545 } 546 547 static char unknown_isa[] __cpuinitdata = KERN_ERR \ 548 "Unsupported ISA type, c0.config0: %d."; 549 550 static inline unsigned int decode_config0(struct cpuinfo_mips *c) 551 { 552 unsigned int config0; 553 int isa; 554 555 config0 = read_c0_config(); 556 557 if (((config0 & MIPS_CONF_MT) >> 7) == 1) 558 c->options |= MIPS_CPU_TLB; 559 isa = (config0 & MIPS_CONF_AT) >> 13; 560 switch (isa) { 561 case 0: 562 switch ((config0 & MIPS_CONF_AR) >> 10) { 563 case 0: 564 c->isa_level = MIPS_CPU_ISA_M32R1; 565 break; 566 case 1: 567 c->isa_level = MIPS_CPU_ISA_M32R2; 568 break; 569 default: 570 goto unknown; 571 } 572 break; 573 case 2: 574 switch ((config0 & MIPS_CONF_AR) >> 10) { 575 case 0: 576 c->isa_level = MIPS_CPU_ISA_M64R1; 577 break; 578 case 1: 579 c->isa_level = MIPS_CPU_ISA_M64R2; 580 break; 581 default: 582 goto unknown; 583 } 584 break; 585 default: 586 goto unknown; 587 } 588 589 return config0 & MIPS_CONF_M; 590 591 unknown: 592 panic(unknown_isa, config0); 593 } 594 595 static inline unsigned int decode_config1(struct cpuinfo_mips *c) 596 { 597 unsigned int config1; 598 599 config1 = read_c0_config1(); 600 601 if (config1 & MIPS_CONF1_MD) 602 c->ases |= MIPS_ASE_MDMX; 603 if (config1 & MIPS_CONF1_WR) 604 c->options |= MIPS_CPU_WATCH; 605 if (config1 & MIPS_CONF1_CA) 606 c->ases |= MIPS_ASE_MIPS16; 607 if (config1 & MIPS_CONF1_EP) 608 c->options |= MIPS_CPU_EJTAG; 609 if (config1 & MIPS_CONF1_FP) { 610 c->options |= MIPS_CPU_FPU; 611 c->options |= MIPS_CPU_32FPR; 612 } 613 if (cpu_has_tlb) 614 c->tlbsize = ((config1 & MIPS_CONF1_TLBS) >> 25) + 1; 615 616 return config1 & MIPS_CONF_M; 617 } 618 619 static inline unsigned int decode_config2(struct cpuinfo_mips *c) 620 { 621 unsigned int config2; 622 623 config2 = read_c0_config2(); 624 625 if (config2 & MIPS_CONF2_SL) 626 c->scache.flags &= ~MIPS_CACHE_NOT_PRESENT; 627 628 return config2 & MIPS_CONF_M; 629 } 630 631 static inline unsigned int decode_config3(struct cpuinfo_mips *c) 632 { 633 unsigned int config3; 634 635 config3 = read_c0_config3(); 636 637 if (config3 & MIPS_CONF3_SM) 638 c->ases |= MIPS_ASE_SMARTMIPS; 639 if (config3 & MIPS_CONF3_DSP) 640 c->ases |= MIPS_ASE_DSP; 641 if (config3 & MIPS_CONF3_VINT) 642 c->options |= MIPS_CPU_VINT; 643 if (config3 & MIPS_CONF3_VEIC) 644 c->options |= MIPS_CPU_VEIC; 645 if (config3 & MIPS_CONF3_MT) 646 c->ases |= MIPS_ASE_MIPSMT; 647 if (config3 & MIPS_CONF3_ULRI) 648 c->options |= MIPS_CPU_ULRI; 649 650 return config3 & MIPS_CONF_M; 651 } 652 653 static void __cpuinit decode_configs(struct cpuinfo_mips *c) 654 { 655 /* MIPS32 or MIPS64 compliant CPU. */ 656 c->options = MIPS_CPU_4KEX | MIPS_CPU_4K_CACHE | MIPS_CPU_COUNTER | 657 MIPS_CPU_DIVEC | MIPS_CPU_LLSC | MIPS_CPU_MCHECK; 658 659 c->scache.flags = MIPS_CACHE_NOT_PRESENT; 660 661 /* Read Config registers. */ 662 if (!decode_config0(c)) 663 return; /* actually worth a panic() */ 664 if (!decode_config1(c)) 665 return; 666 if (!decode_config2(c)) 667 return; 668 if (!decode_config3(c)) 669 return; 670 } 671 672 #ifdef CONFIG_CPU_MIPSR2 673 extern void spram_config(void); 674 #else 675 static inline void spram_config(void) {} 676 #endif 677 678 static inline void cpu_probe_mips(struct cpuinfo_mips *c) 679 { 680 decode_configs(c); 681 mips_probe_watch_registers(c); 682 switch (c->processor_id & 0xff00) { 683 case PRID_IMP_4KC: 684 c->cputype = CPU_4KC; 685 break; 686 case PRID_IMP_4KEC: 687 c->cputype = CPU_4KEC; 688 break; 689 case PRID_IMP_4KECR2: 690 c->cputype = CPU_4KEC; 691 break; 692 case PRID_IMP_4KSC: 693 case PRID_IMP_4KSD: 694 c->cputype = CPU_4KSC; 695 break; 696 case PRID_IMP_5KC: 697 c->cputype = CPU_5KC; 698 break; 699 case PRID_IMP_20KC: 700 c->cputype = CPU_20KC; 701 break; 702 case PRID_IMP_24K: 703 case PRID_IMP_24KE: 704 c->cputype = CPU_24K; 705 break; 706 case PRID_IMP_25KF: 707 c->cputype = CPU_25KF; 708 break; 709 case PRID_IMP_34K: 710 c->cputype = CPU_34K; 711 break; 712 case PRID_IMP_74K: 713 c->cputype = CPU_74K; 714 break; 715 case PRID_IMP_1004K: 716 c->cputype = CPU_1004K; 717 break; 718 } 719 720 spram_config(); 721 } 722 723 static inline void cpu_probe_alchemy(struct cpuinfo_mips *c) 724 { 725 decode_configs(c); 726 switch (c->processor_id & 0xff00) { 727 case PRID_IMP_AU1_REV1: 728 case PRID_IMP_AU1_REV2: 729 switch ((c->processor_id >> 24) & 0xff) { 730 case 0: 731 c->cputype = CPU_AU1000; 732 break; 733 case 1: 734 c->cputype = CPU_AU1500; 735 break; 736 case 2: 737 c->cputype = CPU_AU1100; 738 break; 739 case 3: 740 c->cputype = CPU_AU1550; 741 break; 742 case 4: 743 c->cputype = CPU_AU1200; 744 if (2 == (c->processor_id & 0xff)) 745 c->cputype = CPU_AU1250; 746 break; 747 case 5: 748 c->cputype = CPU_AU1210; 749 break; 750 default: 751 panic("Unknown Au Core!"); 752 break; 753 } 754 break; 755 } 756 } 757 758 static inline void cpu_probe_sibyte(struct cpuinfo_mips *c) 759 { 760 decode_configs(c); 761 762 switch (c->processor_id & 0xff00) { 763 case PRID_IMP_SB1: 764 c->cputype = CPU_SB1; 765 /* FPU in pass1 is known to have issues. */ 766 if ((c->processor_id & 0xff) < 0x02) 767 c->options &= ~(MIPS_CPU_FPU | MIPS_CPU_32FPR); 768 break; 769 case PRID_IMP_SB1A: 770 c->cputype = CPU_SB1A; 771 break; 772 } 773 } 774 775 static inline void cpu_probe_sandcraft(struct cpuinfo_mips *c) 776 { 777 decode_configs(c); 778 switch (c->processor_id & 0xff00) { 779 case PRID_IMP_SR71000: 780 c->cputype = CPU_SR71000; 781 c->scache.ways = 8; 782 c->tlbsize = 64; 783 break; 784 } 785 } 786 787 static inline void cpu_probe_nxp(struct cpuinfo_mips *c) 788 { 789 decode_configs(c); 790 switch (c->processor_id & 0xff00) { 791 case PRID_IMP_PR4450: 792 c->cputype = CPU_PR4450; 793 c->isa_level = MIPS_CPU_ISA_M32R1; 794 break; 795 default: 796 panic("Unknown NXP Core!"); /* REVISIT: die? */ 797 break; 798 } 799 } 800 801 802 static inline void cpu_probe_broadcom(struct cpuinfo_mips *c) 803 { 804 decode_configs(c); 805 switch (c->processor_id & 0xff00) { 806 case PRID_IMP_BCM3302: 807 c->cputype = CPU_BCM3302; 808 break; 809 case PRID_IMP_BCM4710: 810 c->cputype = CPU_BCM4710; 811 break; 812 default: 813 c->cputype = CPU_UNKNOWN; 814 break; 815 } 816 } 817 818 const char *__cpu_name[NR_CPUS]; 819 820 /* 821 * Name a CPU 822 */ 823 static __cpuinit const char *cpu_to_name(struct cpuinfo_mips *c) 824 { 825 const char *name = NULL; 826 827 switch (c->cputype) { 828 case CPU_UNKNOWN: name = "unknown"; break; 829 case CPU_R2000: name = "R2000"; break; 830 case CPU_R3000: name = "R3000"; break; 831 case CPU_R3000A: name = "R3000A"; break; 832 case CPU_R3041: name = "R3041"; break; 833 case CPU_R3051: name = "R3051"; break; 834 case CPU_R3052: name = "R3052"; break; 835 case CPU_R3081: name = "R3081"; break; 836 case CPU_R3081E: name = "R3081E"; break; 837 case CPU_R4000PC: name = "R4000PC"; break; 838 case CPU_R4000SC: name = "R4000SC"; break; 839 case CPU_R4000MC: name = "R4000MC"; break; 840 case CPU_R4200: name = "R4200"; break; 841 case CPU_R4400PC: name = "R4400PC"; break; 842 case CPU_R4400SC: name = "R4400SC"; break; 843 case CPU_R4400MC: name = "R4400MC"; break; 844 case CPU_R4600: name = "R4600"; break; 845 case CPU_R6000: name = "R6000"; break; 846 case CPU_R6000A: name = "R6000A"; break; 847 case CPU_R8000: name = "R8000"; break; 848 case CPU_R10000: name = "R10000"; break; 849 case CPU_R12000: name = "R12000"; break; 850 case CPU_R14000: name = "R14000"; break; 851 case CPU_R4300: name = "R4300"; break; 852 case CPU_R4650: name = "R4650"; break; 853 case CPU_R4700: name = "R4700"; break; 854 case CPU_R5000: name = "R5000"; break; 855 case CPU_R5000A: name = "R5000A"; break; 856 case CPU_R4640: name = "R4640"; break; 857 case CPU_NEVADA: name = "Nevada"; break; 858 case CPU_RM7000: name = "RM7000"; break; 859 case CPU_RM9000: name = "RM9000"; break; 860 case CPU_R5432: name = "R5432"; break; 861 case CPU_4KC: name = "MIPS 4Kc"; break; 862 case CPU_5KC: name = "MIPS 5Kc"; break; 863 case CPU_R4310: name = "R4310"; break; 864 case CPU_SB1: name = "SiByte SB1"; break; 865 case CPU_SB1A: name = "SiByte SB1A"; break; 866 case CPU_TX3912: name = "TX3912"; break; 867 case CPU_TX3922: name = "TX3922"; break; 868 case CPU_TX3927: name = "TX3927"; break; 869 case CPU_AU1000: name = "Au1000"; break; 870 case CPU_AU1500: name = "Au1500"; break; 871 case CPU_AU1100: name = "Au1100"; break; 872 case CPU_AU1550: name = "Au1550"; break; 873 case CPU_AU1200: name = "Au1200"; break; 874 case CPU_AU1210: name = "Au1210"; break; 875 case CPU_AU1250: name = "Au1250"; break; 876 case CPU_4KEC: name = "MIPS 4KEc"; break; 877 case CPU_4KSC: name = "MIPS 4KSc"; break; 878 case CPU_VR41XX: name = "NEC Vr41xx"; break; 879 case CPU_R5500: name = "R5500"; break; 880 case CPU_TX49XX: name = "TX49xx"; break; 881 case CPU_20KC: name = "MIPS 20Kc"; break; 882 case CPU_24K: name = "MIPS 24K"; break; 883 case CPU_25KF: name = "MIPS 25Kf"; break; 884 case CPU_34K: name = "MIPS 34K"; break; 885 case CPU_1004K: name = "MIPS 1004K"; break; 886 case CPU_74K: name = "MIPS 74K"; break; 887 case CPU_VR4111: name = "NEC VR4111"; break; 888 case CPU_VR4121: name = "NEC VR4121"; break; 889 case CPU_VR4122: name = "NEC VR4122"; break; 890 case CPU_VR4131: name = "NEC VR4131"; break; 891 case CPU_VR4133: name = "NEC VR4133"; break; 892 case CPU_VR4181: name = "NEC VR4181"; break; 893 case CPU_VR4181A: name = "NEC VR4181A"; break; 894 case CPU_SR71000: name = "Sandcraft SR71000"; break; 895 case CPU_BCM3302: name = "Broadcom BCM3302"; break; 896 case CPU_BCM4710: name = "Broadcom BCM4710"; break; 897 case CPU_PR4450: name = "Philips PR4450"; break; 898 case CPU_LOONGSON2: name = "ICT Loongson-2"; break; 899 default: 900 BUG(); 901 } 902 903 return name; 904 } 905 906 __cpuinit void cpu_probe(void) 907 { 908 struct cpuinfo_mips *c = ¤t_cpu_data; 909 unsigned int cpu = smp_processor_id(); 910 911 c->processor_id = PRID_IMP_UNKNOWN; 912 c->fpu_id = FPIR_IMP_NONE; 913 c->cputype = CPU_UNKNOWN; 914 915 c->processor_id = read_c0_prid(); 916 switch (c->processor_id & 0xff0000) { 917 case PRID_COMP_LEGACY: 918 cpu_probe_legacy(c); 919 break; 920 case PRID_COMP_MIPS: 921 cpu_probe_mips(c); 922 break; 923 case PRID_COMP_ALCHEMY: 924 cpu_probe_alchemy(c); 925 break; 926 case PRID_COMP_SIBYTE: 927 cpu_probe_sibyte(c); 928 break; 929 case PRID_COMP_BROADCOM: 930 cpu_probe_broadcom(c); 931 break; 932 case PRID_COMP_SANDCRAFT: 933 cpu_probe_sandcraft(c); 934 break; 935 case PRID_COMP_NXP: 936 cpu_probe_nxp(c); 937 break; 938 default: 939 c->cputype = CPU_UNKNOWN; 940 } 941 942 /* 943 * Platform code can force the cpu type to optimize code 944 * generation. In that case be sure the cpu type is correctly 945 * manually setup otherwise it could trigger some nasty bugs. 946 */ 947 BUG_ON(current_cpu_type() != c->cputype); 948 949 if (c->options & MIPS_CPU_FPU) { 950 c->fpu_id = cpu_get_fpu_id(); 951 952 if (c->isa_level == MIPS_CPU_ISA_M32R1 || 953 c->isa_level == MIPS_CPU_ISA_M32R2 || 954 c->isa_level == MIPS_CPU_ISA_M64R1 || 955 c->isa_level == MIPS_CPU_ISA_M64R2) { 956 if (c->fpu_id & MIPS_FPIR_3D) 957 c->ases |= MIPS_ASE_MIPS3D; 958 } 959 } 960 961 __cpu_name[cpu] = cpu_to_name(c); 962 963 if (cpu_has_mips_r2) 964 c->srsets = ((read_c0_srsctl() >> 26) & 0x0f) + 1; 965 else 966 c->srsets = 1; 967 } 968 969 __cpuinit void cpu_report(void) 970 { 971 struct cpuinfo_mips *c = ¤t_cpu_data; 972 973 printk(KERN_INFO "CPU revision is: %08x (%s)\n", 974 c->processor_id, cpu_name_string()); 975 if (c->options & MIPS_CPU_FPU) 976 printk(KERN_INFO "FPU revision is: %08x\n", c->fpu_id); 977 } 978