1 /* 2 * Processor capabilities determination functions. 3 * 4 * Copyright (C) xxxx the Anonymous 5 * Copyright (C) 1994 - 2006 Ralf Baechle 6 * Copyright (C) 2003, 2004 Maciej W. Rozycki 7 * Copyright (C) 2001, 2004, 2011, 2012 MIPS Technologies, Inc. 8 * 9 * This program is free software; you can redistribute it and/or 10 * modify it under the terms of the GNU General Public License 11 * as published by the Free Software Foundation; either version 12 * 2 of the License, or (at your option) any later version. 13 */ 14 #include <linux/init.h> 15 #include <linux/kernel.h> 16 #include <linux/ptrace.h> 17 #include <linux/smp.h> 18 #include <linux/stddef.h> 19 #include <linux/export.h> 20 21 #include <asm/bugs.h> 22 #include <asm/cpu.h> 23 #include <asm/cpu-features.h> 24 #include <asm/cpu-type.h> 25 #include <asm/fpu.h> 26 #include <asm/mipsregs.h> 27 #include <asm/mipsmtregs.h> 28 #include <asm/msa.h> 29 #include <asm/watch.h> 30 #include <asm/elf.h> 31 #include <asm/pgtable-bits.h> 32 #include <asm/spram.h> 33 #include <asm/uaccess.h> 34 35 /* 36 * Get the FPU Implementation/Revision. 37 */ 38 static inline unsigned long cpu_get_fpu_id(void) 39 { 40 unsigned long tmp, fpu_id; 41 42 tmp = read_c0_status(); 43 __enable_fpu(FPU_AS_IS); 44 fpu_id = read_32bit_cp1_register(CP1_REVISION); 45 write_c0_status(tmp); 46 return fpu_id; 47 } 48 49 /* 50 * Check if the CPU has an external FPU. 51 */ 52 static inline int __cpu_has_fpu(void) 53 { 54 return (cpu_get_fpu_id() & FPIR_IMP_MASK) != FPIR_IMP_NONE; 55 } 56 57 static inline unsigned long cpu_get_msa_id(void) 58 { 59 unsigned long status, msa_id; 60 61 status = read_c0_status(); 62 __enable_fpu(FPU_64BIT); 63 enable_msa(); 64 msa_id = read_msa_ir(); 65 disable_msa(); 66 write_c0_status(status); 67 return msa_id; 68 } 69 70 /* 71 * Determine the FCSR mask for FPU hardware. 72 */ 73 static inline void cpu_set_fpu_fcsr_mask(struct cpuinfo_mips *c) 74 { 75 unsigned long sr, mask, fcsr, fcsr0, fcsr1; 76 77 mask = FPU_CSR_ALL_X | FPU_CSR_ALL_E | FPU_CSR_ALL_S | FPU_CSR_RM; 78 79 sr = read_c0_status(); 80 __enable_fpu(FPU_AS_IS); 81 82 fcsr = read_32bit_cp1_register(CP1_STATUS); 83 84 fcsr0 = fcsr & mask; 85 write_32bit_cp1_register(CP1_STATUS, fcsr0); 86 fcsr0 = read_32bit_cp1_register(CP1_STATUS); 87 88 fcsr1 = fcsr | ~mask; 89 write_32bit_cp1_register(CP1_STATUS, fcsr1); 90 fcsr1 = read_32bit_cp1_register(CP1_STATUS); 91 92 write_32bit_cp1_register(CP1_STATUS, fcsr); 93 94 write_c0_status(sr); 95 96 c->fpu_msk31 = ~(fcsr0 ^ fcsr1) & ~mask; 97 } 98 99 /* 100 * Set the FIR feature flags for the FPU emulator. 101 */ 102 static void cpu_set_nofpu_id(struct cpuinfo_mips *c) 103 { 104 u32 value; 105 106 value = 0; 107 if (c->isa_level & (MIPS_CPU_ISA_M32R1 | MIPS_CPU_ISA_M64R1 | 108 MIPS_CPU_ISA_M32R2 | MIPS_CPU_ISA_M64R2 | 109 MIPS_CPU_ISA_M32R6 | MIPS_CPU_ISA_M64R6)) 110 value |= MIPS_FPIR_D | MIPS_FPIR_S; 111 if (c->isa_level & (MIPS_CPU_ISA_M32R2 | MIPS_CPU_ISA_M64R2 | 112 MIPS_CPU_ISA_M32R6 | MIPS_CPU_ISA_M64R6)) 113 value |= MIPS_FPIR_F64 | MIPS_FPIR_L | MIPS_FPIR_W; 114 c->fpu_id = value; 115 } 116 117 /* Determined FPU emulator mask to use for the boot CPU with "nofpu". */ 118 static unsigned int mips_nofpu_msk31; 119 120 /* 121 * Set options for FPU hardware. 122 */ 123 static void cpu_set_fpu_opts(struct cpuinfo_mips *c) 124 { 125 c->fpu_id = cpu_get_fpu_id(); 126 mips_nofpu_msk31 = c->fpu_msk31; 127 128 if (c->isa_level & (MIPS_CPU_ISA_M32R1 | MIPS_CPU_ISA_M64R1 | 129 MIPS_CPU_ISA_M32R2 | MIPS_CPU_ISA_M64R2 | 130 MIPS_CPU_ISA_M32R6 | MIPS_CPU_ISA_M64R6)) { 131 if (c->fpu_id & MIPS_FPIR_3D) 132 c->ases |= MIPS_ASE_MIPS3D; 133 if (c->fpu_id & MIPS_FPIR_FREP) 134 c->options |= MIPS_CPU_FRE; 135 } 136 137 cpu_set_fpu_fcsr_mask(c); 138 } 139 140 /* 141 * Set options for the FPU emulator. 142 */ 143 static void cpu_set_nofpu_opts(struct cpuinfo_mips *c) 144 { 145 c->options &= ~MIPS_CPU_FPU; 146 c->fpu_msk31 = mips_nofpu_msk31; 147 148 cpu_set_nofpu_id(c); 149 } 150 151 static int mips_fpu_disabled; 152 153 static int __init fpu_disable(char *s) 154 { 155 cpu_set_nofpu_opts(&boot_cpu_data); 156 mips_fpu_disabled = 1; 157 158 return 1; 159 } 160 161 __setup("nofpu", fpu_disable); 162 163 int mips_dsp_disabled; 164 165 static int __init dsp_disable(char *s) 166 { 167 cpu_data[0].ases &= ~(MIPS_ASE_DSP | MIPS_ASE_DSP2P); 168 mips_dsp_disabled = 1; 169 170 return 1; 171 } 172 173 __setup("nodsp", dsp_disable); 174 175 static int mips_htw_disabled; 176 177 static int __init htw_disable(char *s) 178 { 179 mips_htw_disabled = 1; 180 cpu_data[0].options &= ~MIPS_CPU_HTW; 181 write_c0_pwctl(read_c0_pwctl() & 182 ~(1 << MIPS_PWCTL_PWEN_SHIFT)); 183 184 return 1; 185 } 186 187 __setup("nohtw", htw_disable); 188 189 static int mips_ftlb_disabled; 190 static int mips_has_ftlb_configured; 191 192 static void set_ftlb_enable(struct cpuinfo_mips *c, int enable); 193 194 static int __init ftlb_disable(char *s) 195 { 196 unsigned int config4, mmuextdef; 197 198 /* 199 * If the core hasn't done any FTLB configuration, there is nothing 200 * for us to do here. 201 */ 202 if (!mips_has_ftlb_configured) 203 return 1; 204 205 /* Disable it in the boot cpu */ 206 set_ftlb_enable(&cpu_data[0], 0); 207 208 back_to_back_c0_hazard(); 209 210 config4 = read_c0_config4(); 211 212 /* Check that FTLB has been disabled */ 213 mmuextdef = config4 & MIPS_CONF4_MMUEXTDEF; 214 /* MMUSIZEEXT == VTLB ON, FTLB OFF */ 215 if (mmuextdef == MIPS_CONF4_MMUEXTDEF_FTLBSIZEEXT) { 216 /* This should never happen */ 217 pr_warn("FTLB could not be disabled!\n"); 218 return 1; 219 } 220 221 mips_ftlb_disabled = 1; 222 mips_has_ftlb_configured = 0; 223 224 /* 225 * noftlb is mainly used for debug purposes so print 226 * an informative message instead of using pr_debug() 227 */ 228 pr_info("FTLB has been disabled\n"); 229 230 /* 231 * Some of these bits are duplicated in the decode_config4. 232 * MIPS_CONF4_MMUEXTDEF_MMUSIZEEXT is the only possible case 233 * once FTLB has been disabled so undo what decode_config4 did. 234 */ 235 cpu_data[0].tlbsize -= cpu_data[0].tlbsizeftlbways * 236 cpu_data[0].tlbsizeftlbsets; 237 cpu_data[0].tlbsizeftlbsets = 0; 238 cpu_data[0].tlbsizeftlbways = 0; 239 240 return 1; 241 } 242 243 __setup("noftlb", ftlb_disable); 244 245 246 static inline void check_errata(void) 247 { 248 struct cpuinfo_mips *c = ¤t_cpu_data; 249 250 switch (current_cpu_type()) { 251 case CPU_34K: 252 /* 253 * Erratum "RPS May Cause Incorrect Instruction Execution" 254 * This code only handles VPE0, any SMP/RTOS code 255 * making use of VPE1 will be responsable for that VPE. 256 */ 257 if ((c->processor_id & PRID_REV_MASK) <= PRID_REV_34K_V1_0_2) 258 write_c0_config7(read_c0_config7() | MIPS_CONF7_RPS); 259 break; 260 default: 261 break; 262 } 263 } 264 265 void __init check_bugs32(void) 266 { 267 check_errata(); 268 } 269 270 /* 271 * Probe whether cpu has config register by trying to play with 272 * alternate cache bit and see whether it matters. 273 * It's used by cpu_probe to distinguish between R3000A and R3081. 274 */ 275 static inline int cpu_has_confreg(void) 276 { 277 #ifdef CONFIG_CPU_R3000 278 extern unsigned long r3k_cache_size(unsigned long); 279 unsigned long size1, size2; 280 unsigned long cfg = read_c0_conf(); 281 282 size1 = r3k_cache_size(ST0_ISC); 283 write_c0_conf(cfg ^ R30XX_CONF_AC); 284 size2 = r3k_cache_size(ST0_ISC); 285 write_c0_conf(cfg); 286 return size1 != size2; 287 #else 288 return 0; 289 #endif 290 } 291 292 static inline void set_elf_platform(int cpu, const char *plat) 293 { 294 if (cpu == 0) 295 __elf_platform = plat; 296 } 297 298 static inline void cpu_probe_vmbits(struct cpuinfo_mips *c) 299 { 300 #ifdef __NEED_VMBITS_PROBE 301 write_c0_entryhi(0x3fffffffffffe000ULL); 302 back_to_back_c0_hazard(); 303 c->vmbits = fls64(read_c0_entryhi() & 0x3fffffffffffe000ULL); 304 #endif 305 } 306 307 static void set_isa(struct cpuinfo_mips *c, unsigned int isa) 308 { 309 switch (isa) { 310 case MIPS_CPU_ISA_M64R2: 311 c->isa_level |= MIPS_CPU_ISA_M32R2 | MIPS_CPU_ISA_M64R2; 312 case MIPS_CPU_ISA_M64R1: 313 c->isa_level |= MIPS_CPU_ISA_M32R1 | MIPS_CPU_ISA_M64R1; 314 case MIPS_CPU_ISA_V: 315 c->isa_level |= MIPS_CPU_ISA_V; 316 case MIPS_CPU_ISA_IV: 317 c->isa_level |= MIPS_CPU_ISA_IV; 318 case MIPS_CPU_ISA_III: 319 c->isa_level |= MIPS_CPU_ISA_II | MIPS_CPU_ISA_III; 320 break; 321 322 /* R6 incompatible with everything else */ 323 case MIPS_CPU_ISA_M64R6: 324 c->isa_level |= MIPS_CPU_ISA_M32R6 | MIPS_CPU_ISA_M64R6; 325 case MIPS_CPU_ISA_M32R6: 326 c->isa_level |= MIPS_CPU_ISA_M32R6; 327 /* Break here so we don't add incompatible ISAs */ 328 break; 329 case MIPS_CPU_ISA_M32R2: 330 c->isa_level |= MIPS_CPU_ISA_M32R2; 331 case MIPS_CPU_ISA_M32R1: 332 c->isa_level |= MIPS_CPU_ISA_M32R1; 333 case MIPS_CPU_ISA_II: 334 c->isa_level |= MIPS_CPU_ISA_II; 335 break; 336 } 337 } 338 339 static char unknown_isa[] = KERN_ERR \ 340 "Unsupported ISA type, c0.config0: %d."; 341 342 static unsigned int calculate_ftlb_probability(struct cpuinfo_mips *c) 343 { 344 345 unsigned int probability = c->tlbsize / c->tlbsizevtlb; 346 347 /* 348 * 0 = All TLBWR instructions go to FTLB 349 * 1 = 15:1: For every 16 TBLWR instructions, 15 go to the 350 * FTLB and 1 goes to the VTLB. 351 * 2 = 7:1: As above with 7:1 ratio. 352 * 3 = 3:1: As above with 3:1 ratio. 353 * 354 * Use the linear midpoint as the probability threshold. 355 */ 356 if (probability >= 12) 357 return 1; 358 else if (probability >= 6) 359 return 2; 360 else 361 /* 362 * So FTLB is less than 4 times bigger than VTLB. 363 * A 3:1 ratio can still be useful though. 364 */ 365 return 3; 366 } 367 368 static void set_ftlb_enable(struct cpuinfo_mips *c, int enable) 369 { 370 unsigned int config6; 371 372 /* It's implementation dependent how the FTLB can be enabled */ 373 switch (c->cputype) { 374 case CPU_PROAPTIV: 375 case CPU_P5600: 376 /* proAptiv & related cores use Config6 to enable the FTLB */ 377 config6 = read_c0_config6(); 378 /* Clear the old probability value */ 379 config6 &= ~(3 << MIPS_CONF6_FTLBP_SHIFT); 380 if (enable) 381 /* Enable FTLB */ 382 write_c0_config6(config6 | 383 (calculate_ftlb_probability(c) 384 << MIPS_CONF6_FTLBP_SHIFT) 385 | MIPS_CONF6_FTLBEN); 386 else 387 /* Disable FTLB */ 388 write_c0_config6(config6 & ~MIPS_CONF6_FTLBEN); 389 back_to_back_c0_hazard(); 390 break; 391 } 392 } 393 394 static inline unsigned int decode_config0(struct cpuinfo_mips *c) 395 { 396 unsigned int config0; 397 int isa; 398 399 config0 = read_c0_config(); 400 401 /* 402 * Look for Standard TLB or Dual VTLB and FTLB 403 */ 404 if ((((config0 & MIPS_CONF_MT) >> 7) == 1) || 405 (((config0 & MIPS_CONF_MT) >> 7) == 4)) 406 c->options |= MIPS_CPU_TLB; 407 408 isa = (config0 & MIPS_CONF_AT) >> 13; 409 switch (isa) { 410 case 0: 411 switch ((config0 & MIPS_CONF_AR) >> 10) { 412 case 0: 413 set_isa(c, MIPS_CPU_ISA_M32R1); 414 break; 415 case 1: 416 set_isa(c, MIPS_CPU_ISA_M32R2); 417 break; 418 case 2: 419 set_isa(c, MIPS_CPU_ISA_M32R6); 420 break; 421 default: 422 goto unknown; 423 } 424 break; 425 case 2: 426 switch ((config0 & MIPS_CONF_AR) >> 10) { 427 case 0: 428 set_isa(c, MIPS_CPU_ISA_M64R1); 429 break; 430 case 1: 431 set_isa(c, MIPS_CPU_ISA_M64R2); 432 break; 433 case 2: 434 set_isa(c, MIPS_CPU_ISA_M64R6); 435 break; 436 default: 437 goto unknown; 438 } 439 break; 440 default: 441 goto unknown; 442 } 443 444 return config0 & MIPS_CONF_M; 445 446 unknown: 447 panic(unknown_isa, config0); 448 } 449 450 static inline unsigned int decode_config1(struct cpuinfo_mips *c) 451 { 452 unsigned int config1; 453 454 config1 = read_c0_config1(); 455 456 if (config1 & MIPS_CONF1_MD) 457 c->ases |= MIPS_ASE_MDMX; 458 if (config1 & MIPS_CONF1_WR) 459 c->options |= MIPS_CPU_WATCH; 460 if (config1 & MIPS_CONF1_CA) 461 c->ases |= MIPS_ASE_MIPS16; 462 if (config1 & MIPS_CONF1_EP) 463 c->options |= MIPS_CPU_EJTAG; 464 if (config1 & MIPS_CONF1_FP) { 465 c->options |= MIPS_CPU_FPU; 466 c->options |= MIPS_CPU_32FPR; 467 } 468 if (cpu_has_tlb) { 469 c->tlbsize = ((config1 & MIPS_CONF1_TLBS) >> 25) + 1; 470 c->tlbsizevtlb = c->tlbsize; 471 c->tlbsizeftlbsets = 0; 472 } 473 474 return config1 & MIPS_CONF_M; 475 } 476 477 static inline unsigned int decode_config2(struct cpuinfo_mips *c) 478 { 479 unsigned int config2; 480 481 config2 = read_c0_config2(); 482 483 if (config2 & MIPS_CONF2_SL) 484 c->scache.flags &= ~MIPS_CACHE_NOT_PRESENT; 485 486 return config2 & MIPS_CONF_M; 487 } 488 489 static inline unsigned int decode_config3(struct cpuinfo_mips *c) 490 { 491 unsigned int config3; 492 493 config3 = read_c0_config3(); 494 495 if (config3 & MIPS_CONF3_SM) { 496 c->ases |= MIPS_ASE_SMARTMIPS; 497 c->options |= MIPS_CPU_RIXI; 498 } 499 if (config3 & MIPS_CONF3_RXI) 500 c->options |= MIPS_CPU_RIXI; 501 if (config3 & MIPS_CONF3_DSP) 502 c->ases |= MIPS_ASE_DSP; 503 if (config3 & MIPS_CONF3_DSP2P) 504 c->ases |= MIPS_ASE_DSP2P; 505 if (config3 & MIPS_CONF3_VINT) 506 c->options |= MIPS_CPU_VINT; 507 if (config3 & MIPS_CONF3_VEIC) 508 c->options |= MIPS_CPU_VEIC; 509 if (config3 & MIPS_CONF3_MT) 510 c->ases |= MIPS_ASE_MIPSMT; 511 if (config3 & MIPS_CONF3_ULRI) 512 c->options |= MIPS_CPU_ULRI; 513 if (config3 & MIPS_CONF3_ISA) 514 c->options |= MIPS_CPU_MICROMIPS; 515 if (config3 & MIPS_CONF3_VZ) 516 c->ases |= MIPS_ASE_VZ; 517 if (config3 & MIPS_CONF3_SC) 518 c->options |= MIPS_CPU_SEGMENTS; 519 if (config3 & MIPS_CONF3_MSA) 520 c->ases |= MIPS_ASE_MSA; 521 /* Only tested on 32-bit cores */ 522 if ((config3 & MIPS_CONF3_PW) && config_enabled(CONFIG_32BIT)) { 523 c->htw_seq = 0; 524 c->options |= MIPS_CPU_HTW; 525 } 526 if (config3 & MIPS_CONF3_CDMM) 527 c->options |= MIPS_CPU_CDMM; 528 529 return config3 & MIPS_CONF_M; 530 } 531 532 static inline unsigned int decode_config4(struct cpuinfo_mips *c) 533 { 534 unsigned int config4; 535 unsigned int newcf4; 536 unsigned int mmuextdef; 537 unsigned int ftlb_page = MIPS_CONF4_FTLBPAGESIZE; 538 539 config4 = read_c0_config4(); 540 541 if (cpu_has_tlb) { 542 if (((config4 & MIPS_CONF4_IE) >> 29) == 2) 543 c->options |= MIPS_CPU_TLBINV; 544 mmuextdef = config4 & MIPS_CONF4_MMUEXTDEF; 545 switch (mmuextdef) { 546 case MIPS_CONF4_MMUEXTDEF_MMUSIZEEXT: 547 c->tlbsize += (config4 & MIPS_CONF4_MMUSIZEEXT) * 0x40; 548 c->tlbsizevtlb = c->tlbsize; 549 break; 550 case MIPS_CONF4_MMUEXTDEF_VTLBSIZEEXT: 551 c->tlbsizevtlb += 552 ((config4 & MIPS_CONF4_VTLBSIZEEXT) >> 553 MIPS_CONF4_VTLBSIZEEXT_SHIFT) * 0x40; 554 c->tlbsize = c->tlbsizevtlb; 555 ftlb_page = MIPS_CONF4_VFTLBPAGESIZE; 556 /* fall through */ 557 case MIPS_CONF4_MMUEXTDEF_FTLBSIZEEXT: 558 if (mips_ftlb_disabled) 559 break; 560 newcf4 = (config4 & ~ftlb_page) | 561 (page_size_ftlb(mmuextdef) << 562 MIPS_CONF4_FTLBPAGESIZE_SHIFT); 563 write_c0_config4(newcf4); 564 back_to_back_c0_hazard(); 565 config4 = read_c0_config4(); 566 if (config4 != newcf4) { 567 pr_err("PAGE_SIZE 0x%lx is not supported by FTLB (config4=0x%x)\n", 568 PAGE_SIZE, config4); 569 /* Switch FTLB off */ 570 set_ftlb_enable(c, 0); 571 break; 572 } 573 c->tlbsizeftlbsets = 1 << 574 ((config4 & MIPS_CONF4_FTLBSETS) >> 575 MIPS_CONF4_FTLBSETS_SHIFT); 576 c->tlbsizeftlbways = ((config4 & MIPS_CONF4_FTLBWAYS) >> 577 MIPS_CONF4_FTLBWAYS_SHIFT) + 2; 578 c->tlbsize += c->tlbsizeftlbways * c->tlbsizeftlbsets; 579 mips_has_ftlb_configured = 1; 580 break; 581 } 582 } 583 584 c->kscratch_mask = (config4 >> 16) & 0xff; 585 586 return config4 & MIPS_CONF_M; 587 } 588 589 static inline unsigned int decode_config5(struct cpuinfo_mips *c) 590 { 591 unsigned int config5; 592 593 config5 = read_c0_config5(); 594 config5 &= ~(MIPS_CONF5_UFR | MIPS_CONF5_UFE); 595 write_c0_config5(config5); 596 597 if (config5 & MIPS_CONF5_EVA) 598 c->options |= MIPS_CPU_EVA; 599 if (config5 & MIPS_CONF5_MRP) 600 c->options |= MIPS_CPU_MAAR; 601 if (config5 & MIPS_CONF5_LLB) 602 c->options |= MIPS_CPU_RW_LLB; 603 604 return config5 & MIPS_CONF_M; 605 } 606 607 static void decode_configs(struct cpuinfo_mips *c) 608 { 609 int ok; 610 611 /* MIPS32 or MIPS64 compliant CPU. */ 612 c->options = MIPS_CPU_4KEX | MIPS_CPU_4K_CACHE | MIPS_CPU_COUNTER | 613 MIPS_CPU_DIVEC | MIPS_CPU_LLSC | MIPS_CPU_MCHECK; 614 615 c->scache.flags = MIPS_CACHE_NOT_PRESENT; 616 617 /* Enable FTLB if present and not disabled */ 618 set_ftlb_enable(c, !mips_ftlb_disabled); 619 620 ok = decode_config0(c); /* Read Config registers. */ 621 BUG_ON(!ok); /* Arch spec violation! */ 622 if (ok) 623 ok = decode_config1(c); 624 if (ok) 625 ok = decode_config2(c); 626 if (ok) 627 ok = decode_config3(c); 628 if (ok) 629 ok = decode_config4(c); 630 if (ok) 631 ok = decode_config5(c); 632 633 mips_probe_watch_registers(c); 634 635 if (cpu_has_rixi) { 636 /* Enable the RIXI exceptions */ 637 set_c0_pagegrain(PG_IEC); 638 back_to_back_c0_hazard(); 639 /* Verify the IEC bit is set */ 640 if (read_c0_pagegrain() & PG_IEC) 641 c->options |= MIPS_CPU_RIXIEX; 642 } 643 644 #ifndef CONFIG_MIPS_CPS 645 if (cpu_has_mips_r2_r6) { 646 c->core = get_ebase_cpunum(); 647 if (cpu_has_mipsmt) 648 c->core >>= fls(core_nvpes()) - 1; 649 } 650 #endif 651 } 652 653 #define R4K_OPTS (MIPS_CPU_TLB | MIPS_CPU_4KEX | MIPS_CPU_4K_CACHE \ 654 | MIPS_CPU_COUNTER) 655 656 static inline void cpu_probe_legacy(struct cpuinfo_mips *c, unsigned int cpu) 657 { 658 switch (c->processor_id & PRID_IMP_MASK) { 659 case PRID_IMP_R2000: 660 c->cputype = CPU_R2000; 661 __cpu_name[cpu] = "R2000"; 662 c->fpu_msk31 |= FPU_CSR_CONDX | FPU_CSR_FS; 663 c->options = MIPS_CPU_TLB | MIPS_CPU_3K_CACHE | 664 MIPS_CPU_NOFPUEX; 665 if (__cpu_has_fpu()) 666 c->options |= MIPS_CPU_FPU; 667 c->tlbsize = 64; 668 break; 669 case PRID_IMP_R3000: 670 if ((c->processor_id & PRID_REV_MASK) == PRID_REV_R3000A) { 671 if (cpu_has_confreg()) { 672 c->cputype = CPU_R3081E; 673 __cpu_name[cpu] = "R3081"; 674 } else { 675 c->cputype = CPU_R3000A; 676 __cpu_name[cpu] = "R3000A"; 677 } 678 } else { 679 c->cputype = CPU_R3000; 680 __cpu_name[cpu] = "R3000"; 681 } 682 c->fpu_msk31 |= FPU_CSR_CONDX | FPU_CSR_FS; 683 c->options = MIPS_CPU_TLB | MIPS_CPU_3K_CACHE | 684 MIPS_CPU_NOFPUEX; 685 if (__cpu_has_fpu()) 686 c->options |= MIPS_CPU_FPU; 687 c->tlbsize = 64; 688 break; 689 case PRID_IMP_R4000: 690 if (read_c0_config() & CONF_SC) { 691 if ((c->processor_id & PRID_REV_MASK) >= 692 PRID_REV_R4400) { 693 c->cputype = CPU_R4400PC; 694 __cpu_name[cpu] = "R4400PC"; 695 } else { 696 c->cputype = CPU_R4000PC; 697 __cpu_name[cpu] = "R4000PC"; 698 } 699 } else { 700 int cca = read_c0_config() & CONF_CM_CMASK; 701 int mc; 702 703 /* 704 * SC and MC versions can't be reliably told apart, 705 * but only the latter support coherent caching 706 * modes so assume the firmware has set the KSEG0 707 * coherency attribute reasonably (if uncached, we 708 * assume SC). 709 */ 710 switch (cca) { 711 case CONF_CM_CACHABLE_CE: 712 case CONF_CM_CACHABLE_COW: 713 case CONF_CM_CACHABLE_CUW: 714 mc = 1; 715 break; 716 default: 717 mc = 0; 718 break; 719 } 720 if ((c->processor_id & PRID_REV_MASK) >= 721 PRID_REV_R4400) { 722 c->cputype = mc ? CPU_R4400MC : CPU_R4400SC; 723 __cpu_name[cpu] = mc ? "R4400MC" : "R4400SC"; 724 } else { 725 c->cputype = mc ? CPU_R4000MC : CPU_R4000SC; 726 __cpu_name[cpu] = mc ? "R4000MC" : "R4000SC"; 727 } 728 } 729 730 set_isa(c, MIPS_CPU_ISA_III); 731 c->fpu_msk31 |= FPU_CSR_CONDX; 732 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR | 733 MIPS_CPU_WATCH | MIPS_CPU_VCE | 734 MIPS_CPU_LLSC; 735 c->tlbsize = 48; 736 break; 737 case PRID_IMP_VR41XX: 738 set_isa(c, MIPS_CPU_ISA_III); 739 c->fpu_msk31 |= FPU_CSR_CONDX; 740 c->options = R4K_OPTS; 741 c->tlbsize = 32; 742 switch (c->processor_id & 0xf0) { 743 case PRID_REV_VR4111: 744 c->cputype = CPU_VR4111; 745 __cpu_name[cpu] = "NEC VR4111"; 746 break; 747 case PRID_REV_VR4121: 748 c->cputype = CPU_VR4121; 749 __cpu_name[cpu] = "NEC VR4121"; 750 break; 751 case PRID_REV_VR4122: 752 if ((c->processor_id & 0xf) < 0x3) { 753 c->cputype = CPU_VR4122; 754 __cpu_name[cpu] = "NEC VR4122"; 755 } else { 756 c->cputype = CPU_VR4181A; 757 __cpu_name[cpu] = "NEC VR4181A"; 758 } 759 break; 760 case PRID_REV_VR4130: 761 if ((c->processor_id & 0xf) < 0x4) { 762 c->cputype = CPU_VR4131; 763 __cpu_name[cpu] = "NEC VR4131"; 764 } else { 765 c->cputype = CPU_VR4133; 766 c->options |= MIPS_CPU_LLSC; 767 __cpu_name[cpu] = "NEC VR4133"; 768 } 769 break; 770 default: 771 printk(KERN_INFO "Unexpected CPU of NEC VR4100 series\n"); 772 c->cputype = CPU_VR41XX; 773 __cpu_name[cpu] = "NEC Vr41xx"; 774 break; 775 } 776 break; 777 case PRID_IMP_R4300: 778 c->cputype = CPU_R4300; 779 __cpu_name[cpu] = "R4300"; 780 set_isa(c, MIPS_CPU_ISA_III); 781 c->fpu_msk31 |= FPU_CSR_CONDX; 782 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR | 783 MIPS_CPU_LLSC; 784 c->tlbsize = 32; 785 break; 786 case PRID_IMP_R4600: 787 c->cputype = CPU_R4600; 788 __cpu_name[cpu] = "R4600"; 789 set_isa(c, MIPS_CPU_ISA_III); 790 c->fpu_msk31 |= FPU_CSR_CONDX; 791 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR | 792 MIPS_CPU_LLSC; 793 c->tlbsize = 48; 794 break; 795 #if 0 796 case PRID_IMP_R4650: 797 /* 798 * This processor doesn't have an MMU, so it's not 799 * "real easy" to run Linux on it. It is left purely 800 * for documentation. Commented out because it shares 801 * it's c0_prid id number with the TX3900. 802 */ 803 c->cputype = CPU_R4650; 804 __cpu_name[cpu] = "R4650"; 805 set_isa(c, MIPS_CPU_ISA_III); 806 c->fpu_msk31 |= FPU_CSR_CONDX; 807 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_LLSC; 808 c->tlbsize = 48; 809 break; 810 #endif 811 case PRID_IMP_TX39: 812 c->fpu_msk31 |= FPU_CSR_CONDX | FPU_CSR_FS; 813 c->options = MIPS_CPU_TLB | MIPS_CPU_TX39_CACHE; 814 815 if ((c->processor_id & 0xf0) == (PRID_REV_TX3927 & 0xf0)) { 816 c->cputype = CPU_TX3927; 817 __cpu_name[cpu] = "TX3927"; 818 c->tlbsize = 64; 819 } else { 820 switch (c->processor_id & PRID_REV_MASK) { 821 case PRID_REV_TX3912: 822 c->cputype = CPU_TX3912; 823 __cpu_name[cpu] = "TX3912"; 824 c->tlbsize = 32; 825 break; 826 case PRID_REV_TX3922: 827 c->cputype = CPU_TX3922; 828 __cpu_name[cpu] = "TX3922"; 829 c->tlbsize = 64; 830 break; 831 } 832 } 833 break; 834 case PRID_IMP_R4700: 835 c->cputype = CPU_R4700; 836 __cpu_name[cpu] = "R4700"; 837 set_isa(c, MIPS_CPU_ISA_III); 838 c->fpu_msk31 |= FPU_CSR_CONDX; 839 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR | 840 MIPS_CPU_LLSC; 841 c->tlbsize = 48; 842 break; 843 case PRID_IMP_TX49: 844 c->cputype = CPU_TX49XX; 845 __cpu_name[cpu] = "R49XX"; 846 set_isa(c, MIPS_CPU_ISA_III); 847 c->fpu_msk31 |= FPU_CSR_CONDX; 848 c->options = R4K_OPTS | MIPS_CPU_LLSC; 849 if (!(c->processor_id & 0x08)) 850 c->options |= MIPS_CPU_FPU | MIPS_CPU_32FPR; 851 c->tlbsize = 48; 852 break; 853 case PRID_IMP_R5000: 854 c->cputype = CPU_R5000; 855 __cpu_name[cpu] = "R5000"; 856 set_isa(c, MIPS_CPU_ISA_IV); 857 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR | 858 MIPS_CPU_LLSC; 859 c->tlbsize = 48; 860 break; 861 case PRID_IMP_R5432: 862 c->cputype = CPU_R5432; 863 __cpu_name[cpu] = "R5432"; 864 set_isa(c, MIPS_CPU_ISA_IV); 865 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR | 866 MIPS_CPU_WATCH | MIPS_CPU_LLSC; 867 c->tlbsize = 48; 868 break; 869 case PRID_IMP_R5500: 870 c->cputype = CPU_R5500; 871 __cpu_name[cpu] = "R5500"; 872 set_isa(c, MIPS_CPU_ISA_IV); 873 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR | 874 MIPS_CPU_WATCH | MIPS_CPU_LLSC; 875 c->tlbsize = 48; 876 break; 877 case PRID_IMP_NEVADA: 878 c->cputype = CPU_NEVADA; 879 __cpu_name[cpu] = "Nevada"; 880 set_isa(c, MIPS_CPU_ISA_IV); 881 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR | 882 MIPS_CPU_DIVEC | MIPS_CPU_LLSC; 883 c->tlbsize = 48; 884 break; 885 case PRID_IMP_R6000: 886 c->cputype = CPU_R6000; 887 __cpu_name[cpu] = "R6000"; 888 set_isa(c, MIPS_CPU_ISA_II); 889 c->fpu_msk31 |= FPU_CSR_CONDX | FPU_CSR_FS; 890 c->options = MIPS_CPU_TLB | MIPS_CPU_FPU | 891 MIPS_CPU_LLSC; 892 c->tlbsize = 32; 893 break; 894 case PRID_IMP_R6000A: 895 c->cputype = CPU_R6000A; 896 __cpu_name[cpu] = "R6000A"; 897 set_isa(c, MIPS_CPU_ISA_II); 898 c->fpu_msk31 |= FPU_CSR_CONDX | FPU_CSR_FS; 899 c->options = MIPS_CPU_TLB | MIPS_CPU_FPU | 900 MIPS_CPU_LLSC; 901 c->tlbsize = 32; 902 break; 903 case PRID_IMP_RM7000: 904 c->cputype = CPU_RM7000; 905 __cpu_name[cpu] = "RM7000"; 906 set_isa(c, MIPS_CPU_ISA_IV); 907 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR | 908 MIPS_CPU_LLSC; 909 /* 910 * Undocumented RM7000: Bit 29 in the info register of 911 * the RM7000 v2.0 indicates if the TLB has 48 or 64 912 * entries. 913 * 914 * 29 1 => 64 entry JTLB 915 * 0 => 48 entry JTLB 916 */ 917 c->tlbsize = (read_c0_info() & (1 << 29)) ? 64 : 48; 918 break; 919 case PRID_IMP_R8000: 920 c->cputype = CPU_R8000; 921 __cpu_name[cpu] = "RM8000"; 922 set_isa(c, MIPS_CPU_ISA_IV); 923 c->options = MIPS_CPU_TLB | MIPS_CPU_4KEX | 924 MIPS_CPU_FPU | MIPS_CPU_32FPR | 925 MIPS_CPU_LLSC; 926 c->tlbsize = 384; /* has weird TLB: 3-way x 128 */ 927 break; 928 case PRID_IMP_R10000: 929 c->cputype = CPU_R10000; 930 __cpu_name[cpu] = "R10000"; 931 set_isa(c, MIPS_CPU_ISA_IV); 932 c->options = MIPS_CPU_TLB | MIPS_CPU_4K_CACHE | MIPS_CPU_4KEX | 933 MIPS_CPU_FPU | MIPS_CPU_32FPR | 934 MIPS_CPU_COUNTER | MIPS_CPU_WATCH | 935 MIPS_CPU_LLSC; 936 c->tlbsize = 64; 937 break; 938 case PRID_IMP_R12000: 939 c->cputype = CPU_R12000; 940 __cpu_name[cpu] = "R12000"; 941 set_isa(c, MIPS_CPU_ISA_IV); 942 c->options = MIPS_CPU_TLB | MIPS_CPU_4K_CACHE | MIPS_CPU_4KEX | 943 MIPS_CPU_FPU | MIPS_CPU_32FPR | 944 MIPS_CPU_COUNTER | MIPS_CPU_WATCH | 945 MIPS_CPU_LLSC; 946 c->tlbsize = 64; 947 break; 948 case PRID_IMP_R14000: 949 if (((c->processor_id >> 4) & 0x0f) > 2) { 950 c->cputype = CPU_R16000; 951 __cpu_name[cpu] = "R16000"; 952 } else { 953 c->cputype = CPU_R14000; 954 __cpu_name[cpu] = "R14000"; 955 } 956 set_isa(c, MIPS_CPU_ISA_IV); 957 c->options = MIPS_CPU_TLB | MIPS_CPU_4K_CACHE | MIPS_CPU_4KEX | 958 MIPS_CPU_FPU | MIPS_CPU_32FPR | 959 MIPS_CPU_COUNTER | MIPS_CPU_WATCH | 960 MIPS_CPU_LLSC; 961 c->tlbsize = 64; 962 break; 963 case PRID_IMP_LOONGSON_64: /* Loongson-2/3 */ 964 switch (c->processor_id & PRID_REV_MASK) { 965 case PRID_REV_LOONGSON2E: 966 c->cputype = CPU_LOONGSON2; 967 __cpu_name[cpu] = "ICT Loongson-2"; 968 set_elf_platform(cpu, "loongson2e"); 969 set_isa(c, MIPS_CPU_ISA_III); 970 c->fpu_msk31 |= FPU_CSR_CONDX; 971 break; 972 case PRID_REV_LOONGSON2F: 973 c->cputype = CPU_LOONGSON2; 974 __cpu_name[cpu] = "ICT Loongson-2"; 975 set_elf_platform(cpu, "loongson2f"); 976 set_isa(c, MIPS_CPU_ISA_III); 977 c->fpu_msk31 |= FPU_CSR_CONDX; 978 break; 979 case PRID_REV_LOONGSON3A: 980 c->cputype = CPU_LOONGSON3; 981 __cpu_name[cpu] = "ICT Loongson-3"; 982 set_elf_platform(cpu, "loongson3a"); 983 set_isa(c, MIPS_CPU_ISA_M64R1); 984 break; 985 case PRID_REV_LOONGSON3B_R1: 986 case PRID_REV_LOONGSON3B_R2: 987 c->cputype = CPU_LOONGSON3; 988 __cpu_name[cpu] = "ICT Loongson-3"; 989 set_elf_platform(cpu, "loongson3b"); 990 set_isa(c, MIPS_CPU_ISA_M64R1); 991 break; 992 } 993 994 c->options = R4K_OPTS | 995 MIPS_CPU_FPU | MIPS_CPU_LLSC | 996 MIPS_CPU_32FPR; 997 c->tlbsize = 64; 998 c->writecombine = _CACHE_UNCACHED_ACCELERATED; 999 break; 1000 case PRID_IMP_LOONGSON_32: /* Loongson-1 */ 1001 decode_configs(c); 1002 1003 c->cputype = CPU_LOONGSON1; 1004 1005 switch (c->processor_id & PRID_REV_MASK) { 1006 case PRID_REV_LOONGSON1B: 1007 __cpu_name[cpu] = "Loongson 1B"; 1008 break; 1009 } 1010 1011 break; 1012 } 1013 } 1014 1015 static inline void cpu_probe_mips(struct cpuinfo_mips *c, unsigned int cpu) 1016 { 1017 c->writecombine = _CACHE_UNCACHED_ACCELERATED; 1018 switch (c->processor_id & PRID_IMP_MASK) { 1019 case PRID_IMP_QEMU_GENERIC: 1020 c->writecombine = _CACHE_UNCACHED; 1021 c->cputype = CPU_QEMU_GENERIC; 1022 __cpu_name[cpu] = "MIPS GENERIC QEMU"; 1023 break; 1024 case PRID_IMP_4KC: 1025 c->cputype = CPU_4KC; 1026 c->writecombine = _CACHE_UNCACHED; 1027 __cpu_name[cpu] = "MIPS 4Kc"; 1028 break; 1029 case PRID_IMP_4KEC: 1030 case PRID_IMP_4KECR2: 1031 c->cputype = CPU_4KEC; 1032 c->writecombine = _CACHE_UNCACHED; 1033 __cpu_name[cpu] = "MIPS 4KEc"; 1034 break; 1035 case PRID_IMP_4KSC: 1036 case PRID_IMP_4KSD: 1037 c->cputype = CPU_4KSC; 1038 c->writecombine = _CACHE_UNCACHED; 1039 __cpu_name[cpu] = "MIPS 4KSc"; 1040 break; 1041 case PRID_IMP_5KC: 1042 c->cputype = CPU_5KC; 1043 c->writecombine = _CACHE_UNCACHED; 1044 __cpu_name[cpu] = "MIPS 5Kc"; 1045 break; 1046 case PRID_IMP_5KE: 1047 c->cputype = CPU_5KE; 1048 c->writecombine = _CACHE_UNCACHED; 1049 __cpu_name[cpu] = "MIPS 5KE"; 1050 break; 1051 case PRID_IMP_20KC: 1052 c->cputype = CPU_20KC; 1053 c->writecombine = _CACHE_UNCACHED; 1054 __cpu_name[cpu] = "MIPS 20Kc"; 1055 break; 1056 case PRID_IMP_24K: 1057 c->cputype = CPU_24K; 1058 c->writecombine = _CACHE_UNCACHED; 1059 __cpu_name[cpu] = "MIPS 24Kc"; 1060 break; 1061 case PRID_IMP_24KE: 1062 c->cputype = CPU_24K; 1063 c->writecombine = _CACHE_UNCACHED; 1064 __cpu_name[cpu] = "MIPS 24KEc"; 1065 break; 1066 case PRID_IMP_25KF: 1067 c->cputype = CPU_25KF; 1068 c->writecombine = _CACHE_UNCACHED; 1069 __cpu_name[cpu] = "MIPS 25Kc"; 1070 break; 1071 case PRID_IMP_34K: 1072 c->cputype = CPU_34K; 1073 c->writecombine = _CACHE_UNCACHED; 1074 __cpu_name[cpu] = "MIPS 34Kc"; 1075 break; 1076 case PRID_IMP_74K: 1077 c->cputype = CPU_74K; 1078 c->writecombine = _CACHE_UNCACHED; 1079 __cpu_name[cpu] = "MIPS 74Kc"; 1080 break; 1081 case PRID_IMP_M14KC: 1082 c->cputype = CPU_M14KC; 1083 c->writecombine = _CACHE_UNCACHED; 1084 __cpu_name[cpu] = "MIPS M14Kc"; 1085 break; 1086 case PRID_IMP_M14KEC: 1087 c->cputype = CPU_M14KEC; 1088 c->writecombine = _CACHE_UNCACHED; 1089 __cpu_name[cpu] = "MIPS M14KEc"; 1090 break; 1091 case PRID_IMP_1004K: 1092 c->cputype = CPU_1004K; 1093 c->writecombine = _CACHE_UNCACHED; 1094 __cpu_name[cpu] = "MIPS 1004Kc"; 1095 break; 1096 case PRID_IMP_1074K: 1097 c->cputype = CPU_1074K; 1098 c->writecombine = _CACHE_UNCACHED; 1099 __cpu_name[cpu] = "MIPS 1074Kc"; 1100 break; 1101 case PRID_IMP_INTERAPTIV_UP: 1102 c->cputype = CPU_INTERAPTIV; 1103 __cpu_name[cpu] = "MIPS interAptiv"; 1104 break; 1105 case PRID_IMP_INTERAPTIV_MP: 1106 c->cputype = CPU_INTERAPTIV; 1107 __cpu_name[cpu] = "MIPS interAptiv (multi)"; 1108 break; 1109 case PRID_IMP_PROAPTIV_UP: 1110 c->cputype = CPU_PROAPTIV; 1111 __cpu_name[cpu] = "MIPS proAptiv"; 1112 break; 1113 case PRID_IMP_PROAPTIV_MP: 1114 c->cputype = CPU_PROAPTIV; 1115 __cpu_name[cpu] = "MIPS proAptiv (multi)"; 1116 break; 1117 case PRID_IMP_P5600: 1118 c->cputype = CPU_P5600; 1119 __cpu_name[cpu] = "MIPS P5600"; 1120 break; 1121 case PRID_IMP_M5150: 1122 c->cputype = CPU_M5150; 1123 __cpu_name[cpu] = "MIPS M5150"; 1124 break; 1125 } 1126 1127 decode_configs(c); 1128 1129 spram_config(); 1130 } 1131 1132 static inline void cpu_probe_alchemy(struct cpuinfo_mips *c, unsigned int cpu) 1133 { 1134 decode_configs(c); 1135 switch (c->processor_id & PRID_IMP_MASK) { 1136 case PRID_IMP_AU1_REV1: 1137 case PRID_IMP_AU1_REV2: 1138 c->cputype = CPU_ALCHEMY; 1139 switch ((c->processor_id >> 24) & 0xff) { 1140 case 0: 1141 __cpu_name[cpu] = "Au1000"; 1142 break; 1143 case 1: 1144 __cpu_name[cpu] = "Au1500"; 1145 break; 1146 case 2: 1147 __cpu_name[cpu] = "Au1100"; 1148 break; 1149 case 3: 1150 __cpu_name[cpu] = "Au1550"; 1151 break; 1152 case 4: 1153 __cpu_name[cpu] = "Au1200"; 1154 if ((c->processor_id & PRID_REV_MASK) == 2) 1155 __cpu_name[cpu] = "Au1250"; 1156 break; 1157 case 5: 1158 __cpu_name[cpu] = "Au1210"; 1159 break; 1160 default: 1161 __cpu_name[cpu] = "Au1xxx"; 1162 break; 1163 } 1164 break; 1165 } 1166 } 1167 1168 static inline void cpu_probe_sibyte(struct cpuinfo_mips *c, unsigned int cpu) 1169 { 1170 decode_configs(c); 1171 1172 c->writecombine = _CACHE_UNCACHED_ACCELERATED; 1173 switch (c->processor_id & PRID_IMP_MASK) { 1174 case PRID_IMP_SB1: 1175 c->cputype = CPU_SB1; 1176 __cpu_name[cpu] = "SiByte SB1"; 1177 /* FPU in pass1 is known to have issues. */ 1178 if ((c->processor_id & PRID_REV_MASK) < 0x02) 1179 c->options &= ~(MIPS_CPU_FPU | MIPS_CPU_32FPR); 1180 break; 1181 case PRID_IMP_SB1A: 1182 c->cputype = CPU_SB1A; 1183 __cpu_name[cpu] = "SiByte SB1A"; 1184 break; 1185 } 1186 } 1187 1188 static inline void cpu_probe_sandcraft(struct cpuinfo_mips *c, unsigned int cpu) 1189 { 1190 decode_configs(c); 1191 switch (c->processor_id & PRID_IMP_MASK) { 1192 case PRID_IMP_SR71000: 1193 c->cputype = CPU_SR71000; 1194 __cpu_name[cpu] = "Sandcraft SR71000"; 1195 c->scache.ways = 8; 1196 c->tlbsize = 64; 1197 break; 1198 } 1199 } 1200 1201 static inline void cpu_probe_nxp(struct cpuinfo_mips *c, unsigned int cpu) 1202 { 1203 decode_configs(c); 1204 switch (c->processor_id & PRID_IMP_MASK) { 1205 case PRID_IMP_PR4450: 1206 c->cputype = CPU_PR4450; 1207 __cpu_name[cpu] = "Philips PR4450"; 1208 set_isa(c, MIPS_CPU_ISA_M32R1); 1209 break; 1210 } 1211 } 1212 1213 static inline void cpu_probe_broadcom(struct cpuinfo_mips *c, unsigned int cpu) 1214 { 1215 decode_configs(c); 1216 switch (c->processor_id & PRID_IMP_MASK) { 1217 case PRID_IMP_BMIPS32_REV4: 1218 case PRID_IMP_BMIPS32_REV8: 1219 c->cputype = CPU_BMIPS32; 1220 __cpu_name[cpu] = "Broadcom BMIPS32"; 1221 set_elf_platform(cpu, "bmips32"); 1222 break; 1223 case PRID_IMP_BMIPS3300: 1224 case PRID_IMP_BMIPS3300_ALT: 1225 case PRID_IMP_BMIPS3300_BUG: 1226 c->cputype = CPU_BMIPS3300; 1227 __cpu_name[cpu] = "Broadcom BMIPS3300"; 1228 set_elf_platform(cpu, "bmips3300"); 1229 break; 1230 case PRID_IMP_BMIPS43XX: { 1231 int rev = c->processor_id & PRID_REV_MASK; 1232 1233 if (rev >= PRID_REV_BMIPS4380_LO && 1234 rev <= PRID_REV_BMIPS4380_HI) { 1235 c->cputype = CPU_BMIPS4380; 1236 __cpu_name[cpu] = "Broadcom BMIPS4380"; 1237 set_elf_platform(cpu, "bmips4380"); 1238 } else { 1239 c->cputype = CPU_BMIPS4350; 1240 __cpu_name[cpu] = "Broadcom BMIPS4350"; 1241 set_elf_platform(cpu, "bmips4350"); 1242 } 1243 break; 1244 } 1245 case PRID_IMP_BMIPS5000: 1246 case PRID_IMP_BMIPS5200: 1247 c->cputype = CPU_BMIPS5000; 1248 __cpu_name[cpu] = "Broadcom BMIPS5000"; 1249 set_elf_platform(cpu, "bmips5000"); 1250 c->options |= MIPS_CPU_ULRI; 1251 break; 1252 } 1253 } 1254 1255 static inline void cpu_probe_cavium(struct cpuinfo_mips *c, unsigned int cpu) 1256 { 1257 decode_configs(c); 1258 switch (c->processor_id & PRID_IMP_MASK) { 1259 case PRID_IMP_CAVIUM_CN38XX: 1260 case PRID_IMP_CAVIUM_CN31XX: 1261 case PRID_IMP_CAVIUM_CN30XX: 1262 c->cputype = CPU_CAVIUM_OCTEON; 1263 __cpu_name[cpu] = "Cavium Octeon"; 1264 goto platform; 1265 case PRID_IMP_CAVIUM_CN58XX: 1266 case PRID_IMP_CAVIUM_CN56XX: 1267 case PRID_IMP_CAVIUM_CN50XX: 1268 case PRID_IMP_CAVIUM_CN52XX: 1269 c->cputype = CPU_CAVIUM_OCTEON_PLUS; 1270 __cpu_name[cpu] = "Cavium Octeon+"; 1271 platform: 1272 set_elf_platform(cpu, "octeon"); 1273 break; 1274 case PRID_IMP_CAVIUM_CN61XX: 1275 case PRID_IMP_CAVIUM_CN63XX: 1276 case PRID_IMP_CAVIUM_CN66XX: 1277 case PRID_IMP_CAVIUM_CN68XX: 1278 case PRID_IMP_CAVIUM_CNF71XX: 1279 c->cputype = CPU_CAVIUM_OCTEON2; 1280 __cpu_name[cpu] = "Cavium Octeon II"; 1281 set_elf_platform(cpu, "octeon2"); 1282 break; 1283 case PRID_IMP_CAVIUM_CN70XX: 1284 case PRID_IMP_CAVIUM_CN78XX: 1285 c->cputype = CPU_CAVIUM_OCTEON3; 1286 __cpu_name[cpu] = "Cavium Octeon III"; 1287 set_elf_platform(cpu, "octeon3"); 1288 break; 1289 default: 1290 printk(KERN_INFO "Unknown Octeon chip!\n"); 1291 c->cputype = CPU_UNKNOWN; 1292 break; 1293 } 1294 } 1295 1296 static inline void cpu_probe_ingenic(struct cpuinfo_mips *c, unsigned int cpu) 1297 { 1298 decode_configs(c); 1299 /* JZRISC does not implement the CP0 counter. */ 1300 c->options &= ~MIPS_CPU_COUNTER; 1301 BUG_ON(!__builtin_constant_p(cpu_has_counter) || cpu_has_counter); 1302 switch (c->processor_id & PRID_IMP_MASK) { 1303 case PRID_IMP_JZRISC: 1304 c->cputype = CPU_JZRISC; 1305 c->writecombine = _CACHE_UNCACHED_ACCELERATED; 1306 __cpu_name[cpu] = "Ingenic JZRISC"; 1307 break; 1308 default: 1309 panic("Unknown Ingenic Processor ID!"); 1310 break; 1311 } 1312 } 1313 1314 static inline void cpu_probe_netlogic(struct cpuinfo_mips *c, int cpu) 1315 { 1316 decode_configs(c); 1317 1318 if ((c->processor_id & PRID_IMP_MASK) == PRID_IMP_NETLOGIC_AU13XX) { 1319 c->cputype = CPU_ALCHEMY; 1320 __cpu_name[cpu] = "Au1300"; 1321 /* following stuff is not for Alchemy */ 1322 return; 1323 } 1324 1325 c->options = (MIPS_CPU_TLB | 1326 MIPS_CPU_4KEX | 1327 MIPS_CPU_COUNTER | 1328 MIPS_CPU_DIVEC | 1329 MIPS_CPU_WATCH | 1330 MIPS_CPU_EJTAG | 1331 MIPS_CPU_LLSC); 1332 1333 switch (c->processor_id & PRID_IMP_MASK) { 1334 case PRID_IMP_NETLOGIC_XLP2XX: 1335 case PRID_IMP_NETLOGIC_XLP9XX: 1336 case PRID_IMP_NETLOGIC_XLP5XX: 1337 c->cputype = CPU_XLP; 1338 __cpu_name[cpu] = "Broadcom XLPII"; 1339 break; 1340 1341 case PRID_IMP_NETLOGIC_XLP8XX: 1342 case PRID_IMP_NETLOGIC_XLP3XX: 1343 c->cputype = CPU_XLP; 1344 __cpu_name[cpu] = "Netlogic XLP"; 1345 break; 1346 1347 case PRID_IMP_NETLOGIC_XLR732: 1348 case PRID_IMP_NETLOGIC_XLR716: 1349 case PRID_IMP_NETLOGIC_XLR532: 1350 case PRID_IMP_NETLOGIC_XLR308: 1351 case PRID_IMP_NETLOGIC_XLR532C: 1352 case PRID_IMP_NETLOGIC_XLR516C: 1353 case PRID_IMP_NETLOGIC_XLR508C: 1354 case PRID_IMP_NETLOGIC_XLR308C: 1355 c->cputype = CPU_XLR; 1356 __cpu_name[cpu] = "Netlogic XLR"; 1357 break; 1358 1359 case PRID_IMP_NETLOGIC_XLS608: 1360 case PRID_IMP_NETLOGIC_XLS408: 1361 case PRID_IMP_NETLOGIC_XLS404: 1362 case PRID_IMP_NETLOGIC_XLS208: 1363 case PRID_IMP_NETLOGIC_XLS204: 1364 case PRID_IMP_NETLOGIC_XLS108: 1365 case PRID_IMP_NETLOGIC_XLS104: 1366 case PRID_IMP_NETLOGIC_XLS616B: 1367 case PRID_IMP_NETLOGIC_XLS608B: 1368 case PRID_IMP_NETLOGIC_XLS416B: 1369 case PRID_IMP_NETLOGIC_XLS412B: 1370 case PRID_IMP_NETLOGIC_XLS408B: 1371 case PRID_IMP_NETLOGIC_XLS404B: 1372 c->cputype = CPU_XLR; 1373 __cpu_name[cpu] = "Netlogic XLS"; 1374 break; 1375 1376 default: 1377 pr_info("Unknown Netlogic chip id [%02x]!\n", 1378 c->processor_id); 1379 c->cputype = CPU_XLR; 1380 break; 1381 } 1382 1383 if (c->cputype == CPU_XLP) { 1384 set_isa(c, MIPS_CPU_ISA_M64R2); 1385 c->options |= (MIPS_CPU_FPU | MIPS_CPU_ULRI | MIPS_CPU_MCHECK); 1386 /* This will be updated again after all threads are woken up */ 1387 c->tlbsize = ((read_c0_config6() >> 16) & 0xffff) + 1; 1388 } else { 1389 set_isa(c, MIPS_CPU_ISA_M64R1); 1390 c->tlbsize = ((read_c0_config1() >> 25) & 0x3f) + 1; 1391 } 1392 c->kscratch_mask = 0xf; 1393 } 1394 1395 #ifdef CONFIG_64BIT 1396 /* For use by uaccess.h */ 1397 u64 __ua_limit; 1398 EXPORT_SYMBOL(__ua_limit); 1399 #endif 1400 1401 const char *__cpu_name[NR_CPUS]; 1402 const char *__elf_platform; 1403 1404 void cpu_probe(void) 1405 { 1406 struct cpuinfo_mips *c = ¤t_cpu_data; 1407 unsigned int cpu = smp_processor_id(); 1408 1409 c->processor_id = PRID_IMP_UNKNOWN; 1410 c->fpu_id = FPIR_IMP_NONE; 1411 c->cputype = CPU_UNKNOWN; 1412 c->writecombine = _CACHE_UNCACHED; 1413 1414 c->fpu_csr31 = FPU_CSR_RN; 1415 c->fpu_msk31 = FPU_CSR_RSVD | FPU_CSR_ABS2008 | FPU_CSR_NAN2008; 1416 1417 c->processor_id = read_c0_prid(); 1418 switch (c->processor_id & PRID_COMP_MASK) { 1419 case PRID_COMP_LEGACY: 1420 cpu_probe_legacy(c, cpu); 1421 break; 1422 case PRID_COMP_MIPS: 1423 cpu_probe_mips(c, cpu); 1424 break; 1425 case PRID_COMP_ALCHEMY: 1426 cpu_probe_alchemy(c, cpu); 1427 break; 1428 case PRID_COMP_SIBYTE: 1429 cpu_probe_sibyte(c, cpu); 1430 break; 1431 case PRID_COMP_BROADCOM: 1432 cpu_probe_broadcom(c, cpu); 1433 break; 1434 case PRID_COMP_SANDCRAFT: 1435 cpu_probe_sandcraft(c, cpu); 1436 break; 1437 case PRID_COMP_NXP: 1438 cpu_probe_nxp(c, cpu); 1439 break; 1440 case PRID_COMP_CAVIUM: 1441 cpu_probe_cavium(c, cpu); 1442 break; 1443 case PRID_COMP_INGENIC: 1444 cpu_probe_ingenic(c, cpu); 1445 break; 1446 case PRID_COMP_NETLOGIC: 1447 cpu_probe_netlogic(c, cpu); 1448 break; 1449 } 1450 1451 BUG_ON(!__cpu_name[cpu]); 1452 BUG_ON(c->cputype == CPU_UNKNOWN); 1453 1454 /* 1455 * Platform code can force the cpu type to optimize code 1456 * generation. In that case be sure the cpu type is correctly 1457 * manually setup otherwise it could trigger some nasty bugs. 1458 */ 1459 BUG_ON(current_cpu_type() != c->cputype); 1460 1461 if (mips_fpu_disabled) 1462 c->options &= ~MIPS_CPU_FPU; 1463 1464 if (mips_dsp_disabled) 1465 c->ases &= ~(MIPS_ASE_DSP | MIPS_ASE_DSP2P); 1466 1467 if (mips_htw_disabled) { 1468 c->options &= ~MIPS_CPU_HTW; 1469 write_c0_pwctl(read_c0_pwctl() & 1470 ~(1 << MIPS_PWCTL_PWEN_SHIFT)); 1471 } 1472 1473 if (c->options & MIPS_CPU_FPU) 1474 cpu_set_fpu_opts(c); 1475 else 1476 cpu_set_nofpu_opts(c); 1477 1478 if (cpu_has_mips_r2_r6) { 1479 c->srsets = ((read_c0_srsctl() >> 26) & 0x0f) + 1; 1480 /* R2 has Performance Counter Interrupt indicator */ 1481 c->options |= MIPS_CPU_PCI; 1482 } 1483 else 1484 c->srsets = 1; 1485 1486 if (cpu_has_msa) { 1487 c->msa_id = cpu_get_msa_id(); 1488 WARN(c->msa_id & MSA_IR_WRPF, 1489 "Vector register partitioning unimplemented!"); 1490 } 1491 1492 cpu_probe_vmbits(c); 1493 1494 #ifdef CONFIG_64BIT 1495 if (cpu == 0) 1496 __ua_limit = ~((1ull << cpu_vmbits) - 1); 1497 #endif 1498 } 1499 1500 void cpu_report(void) 1501 { 1502 struct cpuinfo_mips *c = ¤t_cpu_data; 1503 1504 pr_info("CPU%d revision is: %08x (%s)\n", 1505 smp_processor_id(), c->processor_id, cpu_name_string()); 1506 if (c->options & MIPS_CPU_FPU) 1507 printk(KERN_INFO "FPU revision is: %08x\n", c->fpu_id); 1508 if (cpu_has_msa) 1509 pr_info("MSA revision is: %08x\n", c->msa_id); 1510 } 1511