1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * Processor capabilities determination functions. 4 * 5 * Copyright (C) xxxx the Anonymous 6 * Copyright (C) 1994 - 2006 Ralf Baechle 7 * Copyright (C) 2003, 2004 Maciej W. Rozycki 8 * Copyright (C) 2001, 2004, 2011, 2012 MIPS Technologies, Inc. 9 */ 10 #include <linux/init.h> 11 #include <linux/kernel.h> 12 #include <linux/mmu_context.h> 13 #include <linux/ptrace.h> 14 #include <linux/smp.h> 15 #include <linux/stddef.h> 16 #include <linux/export.h> 17 18 #include <asm/bugs.h> 19 #include <asm/cpu.h> 20 #include <asm/cpu-features.h> 21 #include <asm/cpu-type.h> 22 #include <asm/fpu.h> 23 #include <asm/mipsregs.h> 24 #include <asm/mipsmtregs.h> 25 #include <asm/msa.h> 26 #include <asm/watch.h> 27 #include <asm/elf.h> 28 #include <asm/pgtable-bits.h> 29 #include <asm/spram.h> 30 #include <asm/traps.h> 31 #include <linux/uaccess.h> 32 33 #include "fpu-probe.h" 34 35 #include <asm/mach-loongson64/cpucfg-emul.h> 36 37 /* Hardware capabilities */ 38 unsigned int elf_hwcap __read_mostly; 39 EXPORT_SYMBOL_GPL(elf_hwcap); 40 41 static bool mmid_disabled_quirk; 42 43 static inline unsigned long cpu_get_msa_id(void) 44 { 45 unsigned long status, msa_id; 46 47 status = read_c0_status(); 48 __enable_fpu(FPU_64BIT); 49 enable_msa(); 50 msa_id = read_msa_ir(); 51 disable_msa(); 52 write_c0_status(status); 53 return msa_id; 54 } 55 56 static int mips_dsp_disabled; 57 58 static int __init dsp_disable(char *s) 59 { 60 cpu_data[0].ases &= ~(MIPS_ASE_DSP | MIPS_ASE_DSP2P); 61 mips_dsp_disabled = 1; 62 63 return 1; 64 } 65 66 __setup("nodsp", dsp_disable); 67 68 static int mips_htw_disabled; 69 70 static int __init htw_disable(char *s) 71 { 72 mips_htw_disabled = 1; 73 cpu_data[0].options &= ~MIPS_CPU_HTW; 74 write_c0_pwctl(read_c0_pwctl() & 75 ~(1 << MIPS_PWCTL_PWEN_SHIFT)); 76 77 return 1; 78 } 79 80 __setup("nohtw", htw_disable); 81 82 static int mips_ftlb_disabled; 83 static int mips_has_ftlb_configured; 84 85 enum ftlb_flags { 86 FTLB_EN = 1 << 0, 87 FTLB_SET_PROB = 1 << 1, 88 }; 89 90 static int set_ftlb_enable(struct cpuinfo_mips *c, enum ftlb_flags flags); 91 92 static int __init ftlb_disable(char *s) 93 { 94 unsigned int config4, mmuextdef; 95 96 /* 97 * If the core hasn't done any FTLB configuration, there is nothing 98 * for us to do here. 99 */ 100 if (!mips_has_ftlb_configured) 101 return 1; 102 103 /* Disable it in the boot cpu */ 104 if (set_ftlb_enable(&cpu_data[0], 0)) { 105 pr_warn("Can't turn FTLB off\n"); 106 return 1; 107 } 108 109 config4 = read_c0_config4(); 110 111 /* Check that FTLB has been disabled */ 112 mmuextdef = config4 & MIPS_CONF4_MMUEXTDEF; 113 /* MMUSIZEEXT == VTLB ON, FTLB OFF */ 114 if (mmuextdef == MIPS_CONF4_MMUEXTDEF_FTLBSIZEEXT) { 115 /* This should never happen */ 116 pr_warn("FTLB could not be disabled!\n"); 117 return 1; 118 } 119 120 mips_ftlb_disabled = 1; 121 mips_has_ftlb_configured = 0; 122 123 /* 124 * noftlb is mainly used for debug purposes so print 125 * an informative message instead of using pr_debug() 126 */ 127 pr_info("FTLB has been disabled\n"); 128 129 /* 130 * Some of these bits are duplicated in the decode_config4. 131 * MIPS_CONF4_MMUEXTDEF_MMUSIZEEXT is the only possible case 132 * once FTLB has been disabled so undo what decode_config4 did. 133 */ 134 cpu_data[0].tlbsize -= cpu_data[0].tlbsizeftlbways * 135 cpu_data[0].tlbsizeftlbsets; 136 cpu_data[0].tlbsizeftlbsets = 0; 137 cpu_data[0].tlbsizeftlbways = 0; 138 139 return 1; 140 } 141 142 __setup("noftlb", ftlb_disable); 143 144 /* 145 * Check if the CPU has per tc perf counters 146 */ 147 static inline void cpu_set_mt_per_tc_perf(struct cpuinfo_mips *c) 148 { 149 if (read_c0_config7() & MTI_CONF7_PTC) 150 c->options |= MIPS_CPU_MT_PER_TC_PERF_COUNTERS; 151 } 152 153 static inline void check_errata(void) 154 { 155 struct cpuinfo_mips *c = ¤t_cpu_data; 156 157 switch (current_cpu_type()) { 158 case CPU_34K: 159 /* 160 * Erratum "RPS May Cause Incorrect Instruction Execution" 161 * This code only handles VPE0, any SMP/RTOS code 162 * making use of VPE1 will be responsible for that VPE. 163 */ 164 if ((c->processor_id & PRID_REV_MASK) <= PRID_REV_34K_V1_0_2) 165 write_c0_config7(read_c0_config7() | MIPS_CONF7_RPS); 166 break; 167 default: 168 break; 169 } 170 } 171 172 void __init check_bugs32(void) 173 { 174 check_errata(); 175 } 176 177 /* 178 * Probe whether cpu has config register by trying to play with 179 * alternate cache bit and see whether it matters. 180 * It's used by cpu_probe to distinguish between R3000A and R3081. 181 */ 182 static inline int cpu_has_confreg(void) 183 { 184 #ifdef CONFIG_CPU_R3000 185 unsigned long size1, size2; 186 unsigned long cfg = read_c0_conf(); 187 188 size1 = r3k_cache_size(ST0_ISC); 189 write_c0_conf(cfg ^ R30XX_CONF_AC); 190 size2 = r3k_cache_size(ST0_ISC); 191 write_c0_conf(cfg); 192 return size1 != size2; 193 #else 194 return 0; 195 #endif 196 } 197 198 static inline void set_elf_platform(int cpu, const char *plat) 199 { 200 if (cpu == 0) 201 __elf_platform = plat; 202 } 203 204 static inline void set_elf_base_platform(const char *plat) 205 { 206 if (__elf_base_platform == NULL) { 207 __elf_base_platform = plat; 208 } 209 } 210 211 static inline void cpu_probe_vmbits(struct cpuinfo_mips *c) 212 { 213 #ifdef __NEED_VMBITS_PROBE 214 write_c0_entryhi(0x3fffffffffffe000ULL); 215 back_to_back_c0_hazard(); 216 c->vmbits = fls64(read_c0_entryhi() & 0x3fffffffffffe000ULL); 217 #endif 218 } 219 220 static void set_isa(struct cpuinfo_mips *c, unsigned int isa) 221 { 222 switch (isa) { 223 case MIPS_CPU_ISA_M64R5: 224 c->isa_level |= MIPS_CPU_ISA_M32R5 | MIPS_CPU_ISA_M64R5; 225 set_elf_base_platform("mips64r5"); 226 fallthrough; 227 case MIPS_CPU_ISA_M64R2: 228 c->isa_level |= MIPS_CPU_ISA_M32R2 | MIPS_CPU_ISA_M64R2; 229 set_elf_base_platform("mips64r2"); 230 fallthrough; 231 case MIPS_CPU_ISA_M64R1: 232 c->isa_level |= MIPS_CPU_ISA_M32R1 | MIPS_CPU_ISA_M64R1; 233 set_elf_base_platform("mips64"); 234 fallthrough; 235 case MIPS_CPU_ISA_V: 236 c->isa_level |= MIPS_CPU_ISA_V; 237 set_elf_base_platform("mips5"); 238 fallthrough; 239 case MIPS_CPU_ISA_IV: 240 c->isa_level |= MIPS_CPU_ISA_IV; 241 set_elf_base_platform("mips4"); 242 fallthrough; 243 case MIPS_CPU_ISA_III: 244 c->isa_level |= MIPS_CPU_ISA_II | MIPS_CPU_ISA_III; 245 set_elf_base_platform("mips3"); 246 break; 247 248 /* R6 incompatible with everything else */ 249 case MIPS_CPU_ISA_M64R6: 250 c->isa_level |= MIPS_CPU_ISA_M32R6 | MIPS_CPU_ISA_M64R6; 251 set_elf_base_platform("mips64r6"); 252 fallthrough; 253 case MIPS_CPU_ISA_M32R6: 254 c->isa_level |= MIPS_CPU_ISA_M32R6; 255 set_elf_base_platform("mips32r6"); 256 /* Break here so we don't add incompatible ISAs */ 257 break; 258 case MIPS_CPU_ISA_M32R5: 259 c->isa_level |= MIPS_CPU_ISA_M32R5; 260 set_elf_base_platform("mips32r5"); 261 fallthrough; 262 case MIPS_CPU_ISA_M32R2: 263 c->isa_level |= MIPS_CPU_ISA_M32R2; 264 set_elf_base_platform("mips32r2"); 265 fallthrough; 266 case MIPS_CPU_ISA_M32R1: 267 c->isa_level |= MIPS_CPU_ISA_M32R1; 268 set_elf_base_platform("mips32"); 269 fallthrough; 270 case MIPS_CPU_ISA_II: 271 c->isa_level |= MIPS_CPU_ISA_II; 272 set_elf_base_platform("mips2"); 273 break; 274 } 275 } 276 277 static char unknown_isa[] = KERN_ERR \ 278 "Unsupported ISA type, c0.config0: %d."; 279 280 static unsigned int calculate_ftlb_probability(struct cpuinfo_mips *c) 281 { 282 283 unsigned int probability = c->tlbsize / c->tlbsizevtlb; 284 285 /* 286 * 0 = All TLBWR instructions go to FTLB 287 * 1 = 15:1: For every 16 TBLWR instructions, 15 go to the 288 * FTLB and 1 goes to the VTLB. 289 * 2 = 7:1: As above with 7:1 ratio. 290 * 3 = 3:1: As above with 3:1 ratio. 291 * 292 * Use the linear midpoint as the probability threshold. 293 */ 294 if (probability >= 12) 295 return 1; 296 else if (probability >= 6) 297 return 2; 298 else 299 /* 300 * So FTLB is less than 4 times bigger than VTLB. 301 * A 3:1 ratio can still be useful though. 302 */ 303 return 3; 304 } 305 306 static int set_ftlb_enable(struct cpuinfo_mips *c, enum ftlb_flags flags) 307 { 308 unsigned int config; 309 310 /* It's implementation dependent how the FTLB can be enabled */ 311 switch (c->cputype) { 312 case CPU_PROAPTIV: 313 case CPU_P5600: 314 case CPU_P6600: 315 /* proAptiv & related cores use Config6 to enable the FTLB */ 316 config = read_c0_config6(); 317 318 if (flags & FTLB_EN) 319 config |= MTI_CONF6_FTLBEN; 320 else 321 config &= ~MTI_CONF6_FTLBEN; 322 323 if (flags & FTLB_SET_PROB) { 324 config &= ~(3 << MTI_CONF6_FTLBP_SHIFT); 325 config |= calculate_ftlb_probability(c) 326 << MTI_CONF6_FTLBP_SHIFT; 327 } 328 329 write_c0_config6(config); 330 back_to_back_c0_hazard(); 331 break; 332 case CPU_I6400: 333 case CPU_I6500: 334 /* There's no way to disable the FTLB */ 335 if (!(flags & FTLB_EN)) 336 return 1; 337 return 0; 338 case CPU_LOONGSON64: 339 /* Flush ITLB, DTLB, VTLB and FTLB */ 340 write_c0_diag(LOONGSON_DIAG_ITLB | LOONGSON_DIAG_DTLB | 341 LOONGSON_DIAG_VTLB | LOONGSON_DIAG_FTLB); 342 /* Loongson-3 cores use Config6 to enable the FTLB */ 343 config = read_c0_config6(); 344 if (flags & FTLB_EN) 345 /* Enable FTLB */ 346 write_c0_config6(config & ~LOONGSON_CONF6_FTLBDIS); 347 else 348 /* Disable FTLB */ 349 write_c0_config6(config | LOONGSON_CONF6_FTLBDIS); 350 break; 351 default: 352 return 1; 353 } 354 355 return 0; 356 } 357 358 static int mm_config(struct cpuinfo_mips *c) 359 { 360 unsigned int config0, update, mm; 361 362 config0 = read_c0_config(); 363 mm = config0 & MIPS_CONF_MM; 364 365 /* 366 * It's implementation dependent what type of write-merge is supported 367 * and whether it can be enabled/disabled. If it is settable lets make 368 * the merging allowed by default. Some platforms might have 369 * write-through caching unsupported. In this case just ignore the 370 * CP0.Config.MM bit field value. 371 */ 372 switch (c->cputype) { 373 case CPU_24K: 374 case CPU_34K: 375 case CPU_74K: 376 case CPU_P5600: 377 case CPU_P6600: 378 c->options |= MIPS_CPU_MM_FULL; 379 update = MIPS_CONF_MM_FULL; 380 break; 381 case CPU_1004K: 382 case CPU_1074K: 383 case CPU_INTERAPTIV: 384 case CPU_PROAPTIV: 385 mm = 0; 386 fallthrough; 387 default: 388 update = 0; 389 break; 390 } 391 392 if (update) { 393 config0 = (config0 & ~MIPS_CONF_MM) | update; 394 write_c0_config(config0); 395 } else if (mm == MIPS_CONF_MM_SYSAD) { 396 c->options |= MIPS_CPU_MM_SYSAD; 397 } else if (mm == MIPS_CONF_MM_FULL) { 398 c->options |= MIPS_CPU_MM_FULL; 399 } 400 401 return 0; 402 } 403 404 static inline unsigned int decode_config0(struct cpuinfo_mips *c) 405 { 406 unsigned int config0; 407 int isa, mt; 408 409 config0 = read_c0_config(); 410 411 /* 412 * Look for Standard TLB or Dual VTLB and FTLB 413 */ 414 mt = config0 & MIPS_CONF_MT; 415 if (mt == MIPS_CONF_MT_TLB) 416 c->options |= MIPS_CPU_TLB; 417 else if (mt == MIPS_CONF_MT_FTLB) 418 c->options |= MIPS_CPU_TLB | MIPS_CPU_FTLB; 419 420 isa = (config0 & MIPS_CONF_AT) >> 13; 421 switch (isa) { 422 case 0: 423 switch ((config0 & MIPS_CONF_AR) >> 10) { 424 case 0: 425 set_isa(c, MIPS_CPU_ISA_M32R1); 426 break; 427 case 1: 428 set_isa(c, MIPS_CPU_ISA_M32R2); 429 break; 430 case 2: 431 set_isa(c, MIPS_CPU_ISA_M32R6); 432 break; 433 default: 434 goto unknown; 435 } 436 break; 437 case 2: 438 switch ((config0 & MIPS_CONF_AR) >> 10) { 439 case 0: 440 set_isa(c, MIPS_CPU_ISA_M64R1); 441 break; 442 case 1: 443 set_isa(c, MIPS_CPU_ISA_M64R2); 444 break; 445 case 2: 446 set_isa(c, MIPS_CPU_ISA_M64R6); 447 break; 448 default: 449 goto unknown; 450 } 451 break; 452 default: 453 goto unknown; 454 } 455 456 return config0 & MIPS_CONF_M; 457 458 unknown: 459 panic(unknown_isa, config0); 460 } 461 462 static inline unsigned int decode_config1(struct cpuinfo_mips *c) 463 { 464 unsigned int config1; 465 466 config1 = read_c0_config1(); 467 468 if (config1 & MIPS_CONF1_MD) 469 c->ases |= MIPS_ASE_MDMX; 470 if (config1 & MIPS_CONF1_PC) 471 c->options |= MIPS_CPU_PERF; 472 if (config1 & MIPS_CONF1_WR) 473 c->options |= MIPS_CPU_WATCH; 474 if (config1 & MIPS_CONF1_CA) 475 c->ases |= MIPS_ASE_MIPS16; 476 if (config1 & MIPS_CONF1_EP) 477 c->options |= MIPS_CPU_EJTAG; 478 if (config1 & MIPS_CONF1_FP) { 479 c->options |= MIPS_CPU_FPU; 480 c->options |= MIPS_CPU_32FPR; 481 } 482 if (cpu_has_tlb) { 483 c->tlbsize = ((config1 & MIPS_CONF1_TLBS) >> 25) + 1; 484 c->tlbsizevtlb = c->tlbsize; 485 c->tlbsizeftlbsets = 0; 486 } 487 488 return config1 & MIPS_CONF_M; 489 } 490 491 static inline unsigned int decode_config2(struct cpuinfo_mips *c) 492 { 493 unsigned int config2; 494 495 config2 = read_c0_config2(); 496 497 if (config2 & MIPS_CONF2_SL) 498 c->scache.flags &= ~MIPS_CACHE_NOT_PRESENT; 499 500 return config2 & MIPS_CONF_M; 501 } 502 503 static inline unsigned int decode_config3(struct cpuinfo_mips *c) 504 { 505 unsigned int config3; 506 507 config3 = read_c0_config3(); 508 509 if (config3 & MIPS_CONF3_SM) { 510 c->ases |= MIPS_ASE_SMARTMIPS; 511 c->options |= MIPS_CPU_RIXI | MIPS_CPU_CTXTC; 512 } 513 if (config3 & MIPS_CONF3_RXI) 514 c->options |= MIPS_CPU_RIXI; 515 if (config3 & MIPS_CONF3_CTXTC) 516 c->options |= MIPS_CPU_CTXTC; 517 if (config3 & MIPS_CONF3_DSP) 518 c->ases |= MIPS_ASE_DSP; 519 if (config3 & MIPS_CONF3_DSP2P) { 520 c->ases |= MIPS_ASE_DSP2P; 521 if (cpu_has_mips_r6) 522 c->ases |= MIPS_ASE_DSP3; 523 } 524 if (config3 & MIPS_CONF3_VINT) 525 c->options |= MIPS_CPU_VINT; 526 if (config3 & MIPS_CONF3_VEIC) 527 c->options |= MIPS_CPU_VEIC; 528 if (config3 & MIPS_CONF3_LPA) 529 c->options |= MIPS_CPU_LPA; 530 if (config3 & MIPS_CONF3_MT) 531 c->ases |= MIPS_ASE_MIPSMT; 532 if (config3 & MIPS_CONF3_ULRI) 533 c->options |= MIPS_CPU_ULRI; 534 if (config3 & MIPS_CONF3_ISA) 535 c->options |= MIPS_CPU_MICROMIPS; 536 if (config3 & MIPS_CONF3_VZ) 537 c->ases |= MIPS_ASE_VZ; 538 if (config3 & MIPS_CONF3_SC) 539 c->options |= MIPS_CPU_SEGMENTS; 540 if (config3 & MIPS_CONF3_BI) 541 c->options |= MIPS_CPU_BADINSTR; 542 if (config3 & MIPS_CONF3_BP) 543 c->options |= MIPS_CPU_BADINSTRP; 544 if (config3 & MIPS_CONF3_MSA) 545 c->ases |= MIPS_ASE_MSA; 546 if (config3 & MIPS_CONF3_PW) { 547 c->htw_seq = 0; 548 c->options |= MIPS_CPU_HTW; 549 } 550 if (config3 & MIPS_CONF3_CDMM) 551 c->options |= MIPS_CPU_CDMM; 552 if (config3 & MIPS_CONF3_SP) 553 c->options |= MIPS_CPU_SP; 554 555 return config3 & MIPS_CONF_M; 556 } 557 558 static inline unsigned int decode_config4(struct cpuinfo_mips *c) 559 { 560 unsigned int config4; 561 unsigned int newcf4; 562 unsigned int mmuextdef; 563 unsigned int ftlb_page = MIPS_CONF4_FTLBPAGESIZE; 564 unsigned long asid_mask; 565 566 config4 = read_c0_config4(); 567 568 if (cpu_has_tlb) { 569 if (((config4 & MIPS_CONF4_IE) >> 29) == 2) 570 c->options |= MIPS_CPU_TLBINV; 571 572 /* 573 * R6 has dropped the MMUExtDef field from config4. 574 * On R6 the fields always describe the FTLB, and only if it is 575 * present according to Config.MT. 576 */ 577 if (!cpu_has_mips_r6) 578 mmuextdef = config4 & MIPS_CONF4_MMUEXTDEF; 579 else if (cpu_has_ftlb) 580 mmuextdef = MIPS_CONF4_MMUEXTDEF_VTLBSIZEEXT; 581 else 582 mmuextdef = 0; 583 584 switch (mmuextdef) { 585 case MIPS_CONF4_MMUEXTDEF_MMUSIZEEXT: 586 c->tlbsize += (config4 & MIPS_CONF4_MMUSIZEEXT) * 0x40; 587 c->tlbsizevtlb = c->tlbsize; 588 break; 589 case MIPS_CONF4_MMUEXTDEF_VTLBSIZEEXT: 590 c->tlbsizevtlb += 591 ((config4 & MIPS_CONF4_VTLBSIZEEXT) >> 592 MIPS_CONF4_VTLBSIZEEXT_SHIFT) * 0x40; 593 c->tlbsize = c->tlbsizevtlb; 594 ftlb_page = MIPS_CONF4_VFTLBPAGESIZE; 595 fallthrough; 596 case MIPS_CONF4_MMUEXTDEF_FTLBSIZEEXT: 597 if (mips_ftlb_disabled) 598 break; 599 newcf4 = (config4 & ~ftlb_page) | 600 (page_size_ftlb(mmuextdef) << 601 MIPS_CONF4_FTLBPAGESIZE_SHIFT); 602 write_c0_config4(newcf4); 603 back_to_back_c0_hazard(); 604 config4 = read_c0_config4(); 605 if (config4 != newcf4) { 606 pr_err("PAGE_SIZE 0x%lx is not supported by FTLB (config4=0x%x)\n", 607 PAGE_SIZE, config4); 608 /* Switch FTLB off */ 609 set_ftlb_enable(c, 0); 610 mips_ftlb_disabled = 1; 611 break; 612 } 613 c->tlbsizeftlbsets = 1 << 614 ((config4 & MIPS_CONF4_FTLBSETS) >> 615 MIPS_CONF4_FTLBSETS_SHIFT); 616 c->tlbsizeftlbways = ((config4 & MIPS_CONF4_FTLBWAYS) >> 617 MIPS_CONF4_FTLBWAYS_SHIFT) + 2; 618 c->tlbsize += c->tlbsizeftlbways * c->tlbsizeftlbsets; 619 mips_has_ftlb_configured = 1; 620 break; 621 } 622 } 623 624 c->kscratch_mask = (config4 & MIPS_CONF4_KSCREXIST) 625 >> MIPS_CONF4_KSCREXIST_SHIFT; 626 627 asid_mask = MIPS_ENTRYHI_ASID; 628 if (config4 & MIPS_CONF4_AE) 629 asid_mask |= MIPS_ENTRYHI_ASIDX; 630 set_cpu_asid_mask(c, asid_mask); 631 632 /* 633 * Warn if the computed ASID mask doesn't match the mask the kernel 634 * is built for. This may indicate either a serious problem or an 635 * easy optimisation opportunity, but either way should be addressed. 636 */ 637 WARN_ON(asid_mask != cpu_asid_mask(c)); 638 639 return config4 & MIPS_CONF_M; 640 } 641 642 static inline unsigned int decode_config5(struct cpuinfo_mips *c) 643 { 644 unsigned int config5, max_mmid_width; 645 unsigned long asid_mask; 646 647 config5 = read_c0_config5(); 648 config5 &= ~(MIPS_CONF5_UFR | MIPS_CONF5_UFE); 649 650 if (cpu_has_mips_r6) { 651 if (!mmid_disabled_quirk && (!__builtin_constant_p(cpu_has_mmid) || cpu_has_mmid)) 652 config5 |= MIPS_CONF5_MI; 653 else 654 config5 &= ~MIPS_CONF5_MI; 655 } 656 657 write_c0_config5(config5); 658 659 if (config5 & MIPS_CONF5_EVA) 660 c->options |= MIPS_CPU_EVA; 661 if (config5 & MIPS_CONF5_MRP) 662 c->options |= MIPS_CPU_MAAR; 663 if (config5 & MIPS_CONF5_LLB) 664 c->options |= MIPS_CPU_RW_LLB; 665 if (config5 & MIPS_CONF5_MVH) 666 c->options |= MIPS_CPU_MVH; 667 if (cpu_has_mips_r6 && (config5 & MIPS_CONF5_VP)) 668 c->options |= MIPS_CPU_VP; 669 if (config5 & MIPS_CONF5_CA2) 670 c->ases |= MIPS_ASE_MIPS16E2; 671 672 if (config5 & MIPS_CONF5_CRCP) 673 elf_hwcap |= HWCAP_MIPS_CRC32; 674 675 if (cpu_has_mips_r6) { 676 /* Ensure the write to config5 above takes effect */ 677 back_to_back_c0_hazard(); 678 679 /* Check whether we successfully enabled MMID support */ 680 config5 = read_c0_config5(); 681 if (config5 & MIPS_CONF5_MI) 682 c->options |= MIPS_CPU_MMID; 683 684 /* 685 * Warn if we've hardcoded cpu_has_mmid to a value unsuitable 686 * for the CPU we're running on, or if CPUs in an SMP system 687 * have inconsistent MMID support. 688 */ 689 WARN_ON(!!cpu_has_mmid != !!(config5 & MIPS_CONF5_MI)); 690 691 if (cpu_has_mmid) { 692 write_c0_memorymapid(~0ul); 693 back_to_back_c0_hazard(); 694 asid_mask = read_c0_memorymapid(); 695 696 /* 697 * We maintain a bitmap to track MMID allocation, and 698 * need a sensible upper bound on the size of that 699 * bitmap. The initial CPU with MMID support (I6500) 700 * supports 16 bit MMIDs, which gives us an 8KiB 701 * bitmap. The architecture recommends that hardware 702 * support 32 bit MMIDs, which would give us a 512MiB 703 * bitmap - that's too big in most cases. 704 * 705 * Cap MMID width at 16 bits for now & we can revisit 706 * this if & when hardware supports anything wider. 707 */ 708 max_mmid_width = 16; 709 if (asid_mask > GENMASK(max_mmid_width - 1, 0)) { 710 pr_info("Capping MMID width at %d bits", 711 max_mmid_width); 712 asid_mask = GENMASK(max_mmid_width - 1, 0); 713 } 714 set_cpu_asid_mask(c, asid_mask); 715 } 716 } 717 718 return config5 & MIPS_CONF_M; 719 } 720 721 static void decode_configs(struct cpuinfo_mips *c) 722 { 723 int ok; 724 725 /* MIPS32 or MIPS64 compliant CPU. */ 726 c->options = MIPS_CPU_4KEX | MIPS_CPU_4K_CACHE | MIPS_CPU_COUNTER | 727 MIPS_CPU_DIVEC | MIPS_CPU_LLSC | MIPS_CPU_MCHECK; 728 729 c->scache.flags = MIPS_CACHE_NOT_PRESENT; 730 731 /* Enable FTLB if present and not disabled */ 732 set_ftlb_enable(c, mips_ftlb_disabled ? 0 : FTLB_EN); 733 734 ok = decode_config0(c); /* Read Config registers. */ 735 BUG_ON(!ok); /* Arch spec violation! */ 736 if (ok) 737 ok = decode_config1(c); 738 if (ok) 739 ok = decode_config2(c); 740 if (ok) 741 ok = decode_config3(c); 742 if (ok) 743 ok = decode_config4(c); 744 if (ok) 745 ok = decode_config5(c); 746 747 /* Probe the EBase.WG bit */ 748 if (cpu_has_mips_r2_r6) { 749 u64 ebase; 750 unsigned int status; 751 752 /* {read,write}_c0_ebase_64() may be UNDEFINED prior to r6 */ 753 ebase = cpu_has_mips64r6 ? read_c0_ebase_64() 754 : (s32)read_c0_ebase(); 755 if (ebase & MIPS_EBASE_WG) { 756 /* WG bit already set, we can avoid the clumsy probe */ 757 c->options |= MIPS_CPU_EBASE_WG; 758 } else { 759 /* Its UNDEFINED to change EBase while BEV=0 */ 760 status = read_c0_status(); 761 write_c0_status(status | ST0_BEV); 762 irq_enable_hazard(); 763 /* 764 * On pre-r6 cores, this may well clobber the upper bits 765 * of EBase. This is hard to avoid without potentially 766 * hitting UNDEFINED dm*c0 behaviour if EBase is 32-bit. 767 */ 768 if (cpu_has_mips64r6) 769 write_c0_ebase_64(ebase | MIPS_EBASE_WG); 770 else 771 write_c0_ebase(ebase | MIPS_EBASE_WG); 772 back_to_back_c0_hazard(); 773 /* Restore BEV */ 774 write_c0_status(status); 775 if (read_c0_ebase() & MIPS_EBASE_WG) { 776 c->options |= MIPS_CPU_EBASE_WG; 777 write_c0_ebase(ebase); 778 } 779 } 780 } 781 782 /* configure the FTLB write probability */ 783 set_ftlb_enable(c, (mips_ftlb_disabled ? 0 : FTLB_EN) | FTLB_SET_PROB); 784 785 mips_probe_watch_registers(c); 786 787 #ifndef CONFIG_MIPS_CPS 788 if (cpu_has_mips_r2_r6) { 789 unsigned int core; 790 791 core = get_ebase_cpunum(); 792 if (cpu_has_mipsmt) 793 core >>= fls(core_nvpes()) - 1; 794 cpu_set_core(c, core); 795 } 796 #endif 797 } 798 799 /* 800 * Probe for certain guest capabilities by writing config bits and reading back. 801 * Finally write back the original value. 802 */ 803 #define probe_gc0_config(name, maxconf, bits) \ 804 do { \ 805 unsigned int tmp; \ 806 tmp = read_gc0_##name(); \ 807 write_gc0_##name(tmp | (bits)); \ 808 back_to_back_c0_hazard(); \ 809 maxconf = read_gc0_##name(); \ 810 write_gc0_##name(tmp); \ 811 } while (0) 812 813 /* 814 * Probe for dynamic guest capabilities by changing certain config bits and 815 * reading back to see if they change. Finally write back the original value. 816 */ 817 #define probe_gc0_config_dyn(name, maxconf, dynconf, bits) \ 818 do { \ 819 maxconf = read_gc0_##name(); \ 820 write_gc0_##name(maxconf ^ (bits)); \ 821 back_to_back_c0_hazard(); \ 822 dynconf = maxconf ^ read_gc0_##name(); \ 823 write_gc0_##name(maxconf); \ 824 maxconf |= dynconf; \ 825 } while (0) 826 827 static inline unsigned int decode_guest_config0(struct cpuinfo_mips *c) 828 { 829 unsigned int config0; 830 831 probe_gc0_config(config, config0, MIPS_CONF_M); 832 833 if (config0 & MIPS_CONF_M) 834 c->guest.conf |= BIT(1); 835 return config0 & MIPS_CONF_M; 836 } 837 838 static inline unsigned int decode_guest_config1(struct cpuinfo_mips *c) 839 { 840 unsigned int config1, config1_dyn; 841 842 probe_gc0_config_dyn(config1, config1, config1_dyn, 843 MIPS_CONF_M | MIPS_CONF1_PC | MIPS_CONF1_WR | 844 MIPS_CONF1_FP); 845 846 if (config1 & MIPS_CONF1_FP) 847 c->guest.options |= MIPS_CPU_FPU; 848 if (config1_dyn & MIPS_CONF1_FP) 849 c->guest.options_dyn |= MIPS_CPU_FPU; 850 851 if (config1 & MIPS_CONF1_WR) 852 c->guest.options |= MIPS_CPU_WATCH; 853 if (config1_dyn & MIPS_CONF1_WR) 854 c->guest.options_dyn |= MIPS_CPU_WATCH; 855 856 if (config1 & MIPS_CONF1_PC) 857 c->guest.options |= MIPS_CPU_PERF; 858 if (config1_dyn & MIPS_CONF1_PC) 859 c->guest.options_dyn |= MIPS_CPU_PERF; 860 861 if (config1 & MIPS_CONF_M) 862 c->guest.conf |= BIT(2); 863 return config1 & MIPS_CONF_M; 864 } 865 866 static inline unsigned int decode_guest_config2(struct cpuinfo_mips *c) 867 { 868 unsigned int config2; 869 870 probe_gc0_config(config2, config2, MIPS_CONF_M); 871 872 if (config2 & MIPS_CONF_M) 873 c->guest.conf |= BIT(3); 874 return config2 & MIPS_CONF_M; 875 } 876 877 static inline unsigned int decode_guest_config3(struct cpuinfo_mips *c) 878 { 879 unsigned int config3, config3_dyn; 880 881 probe_gc0_config_dyn(config3, config3, config3_dyn, 882 MIPS_CONF_M | MIPS_CONF3_MSA | MIPS_CONF3_ULRI | 883 MIPS_CONF3_CTXTC); 884 885 if (config3 & MIPS_CONF3_CTXTC) 886 c->guest.options |= MIPS_CPU_CTXTC; 887 if (config3_dyn & MIPS_CONF3_CTXTC) 888 c->guest.options_dyn |= MIPS_CPU_CTXTC; 889 890 if (config3 & MIPS_CONF3_PW) 891 c->guest.options |= MIPS_CPU_HTW; 892 893 if (config3 & MIPS_CONF3_ULRI) 894 c->guest.options |= MIPS_CPU_ULRI; 895 896 if (config3 & MIPS_CONF3_SC) 897 c->guest.options |= MIPS_CPU_SEGMENTS; 898 899 if (config3 & MIPS_CONF3_BI) 900 c->guest.options |= MIPS_CPU_BADINSTR; 901 if (config3 & MIPS_CONF3_BP) 902 c->guest.options |= MIPS_CPU_BADINSTRP; 903 904 if (config3 & MIPS_CONF3_MSA) 905 c->guest.ases |= MIPS_ASE_MSA; 906 if (config3_dyn & MIPS_CONF3_MSA) 907 c->guest.ases_dyn |= MIPS_ASE_MSA; 908 909 if (config3 & MIPS_CONF_M) 910 c->guest.conf |= BIT(4); 911 return config3 & MIPS_CONF_M; 912 } 913 914 static inline unsigned int decode_guest_config4(struct cpuinfo_mips *c) 915 { 916 unsigned int config4; 917 918 probe_gc0_config(config4, config4, 919 MIPS_CONF_M | MIPS_CONF4_KSCREXIST); 920 921 c->guest.kscratch_mask = (config4 & MIPS_CONF4_KSCREXIST) 922 >> MIPS_CONF4_KSCREXIST_SHIFT; 923 924 if (config4 & MIPS_CONF_M) 925 c->guest.conf |= BIT(5); 926 return config4 & MIPS_CONF_M; 927 } 928 929 static inline unsigned int decode_guest_config5(struct cpuinfo_mips *c) 930 { 931 unsigned int config5, config5_dyn; 932 933 probe_gc0_config_dyn(config5, config5, config5_dyn, 934 MIPS_CONF_M | MIPS_CONF5_MVH | MIPS_CONF5_MRP); 935 936 if (config5 & MIPS_CONF5_MRP) 937 c->guest.options |= MIPS_CPU_MAAR; 938 if (config5_dyn & MIPS_CONF5_MRP) 939 c->guest.options_dyn |= MIPS_CPU_MAAR; 940 941 if (config5 & MIPS_CONF5_LLB) 942 c->guest.options |= MIPS_CPU_RW_LLB; 943 944 if (config5 & MIPS_CONF5_MVH) 945 c->guest.options |= MIPS_CPU_MVH; 946 947 if (config5 & MIPS_CONF_M) 948 c->guest.conf |= BIT(6); 949 return config5 & MIPS_CONF_M; 950 } 951 952 static inline void decode_guest_configs(struct cpuinfo_mips *c) 953 { 954 unsigned int ok; 955 956 ok = decode_guest_config0(c); 957 if (ok) 958 ok = decode_guest_config1(c); 959 if (ok) 960 ok = decode_guest_config2(c); 961 if (ok) 962 ok = decode_guest_config3(c); 963 if (ok) 964 ok = decode_guest_config4(c); 965 if (ok) 966 decode_guest_config5(c); 967 } 968 969 static inline void cpu_probe_guestctl0(struct cpuinfo_mips *c) 970 { 971 unsigned int guestctl0, temp; 972 973 guestctl0 = read_c0_guestctl0(); 974 975 if (guestctl0 & MIPS_GCTL0_G0E) 976 c->options |= MIPS_CPU_GUESTCTL0EXT; 977 if (guestctl0 & MIPS_GCTL0_G1) 978 c->options |= MIPS_CPU_GUESTCTL1; 979 if (guestctl0 & MIPS_GCTL0_G2) 980 c->options |= MIPS_CPU_GUESTCTL2; 981 if (!(guestctl0 & MIPS_GCTL0_RAD)) { 982 c->options |= MIPS_CPU_GUESTID; 983 984 /* 985 * Probe for Direct Root to Guest (DRG). Set GuestCtl1.RID = 0 986 * first, otherwise all data accesses will be fully virtualised 987 * as if they were performed by guest mode. 988 */ 989 write_c0_guestctl1(0); 990 tlbw_use_hazard(); 991 992 write_c0_guestctl0(guestctl0 | MIPS_GCTL0_DRG); 993 back_to_back_c0_hazard(); 994 temp = read_c0_guestctl0(); 995 996 if (temp & MIPS_GCTL0_DRG) { 997 write_c0_guestctl0(guestctl0); 998 c->options |= MIPS_CPU_DRG; 999 } 1000 } 1001 } 1002 1003 static inline void cpu_probe_guestctl1(struct cpuinfo_mips *c) 1004 { 1005 if (cpu_has_guestid) { 1006 /* determine the number of bits of GuestID available */ 1007 write_c0_guestctl1(MIPS_GCTL1_ID); 1008 back_to_back_c0_hazard(); 1009 c->guestid_mask = (read_c0_guestctl1() & MIPS_GCTL1_ID) 1010 >> MIPS_GCTL1_ID_SHIFT; 1011 write_c0_guestctl1(0); 1012 } 1013 } 1014 1015 static inline void cpu_probe_gtoffset(struct cpuinfo_mips *c) 1016 { 1017 /* determine the number of bits of GTOffset available */ 1018 write_c0_gtoffset(0xffffffff); 1019 back_to_back_c0_hazard(); 1020 c->gtoffset_mask = read_c0_gtoffset(); 1021 write_c0_gtoffset(0); 1022 } 1023 1024 static inline void cpu_probe_vz(struct cpuinfo_mips *c) 1025 { 1026 cpu_probe_guestctl0(c); 1027 if (cpu_has_guestctl1) 1028 cpu_probe_guestctl1(c); 1029 1030 cpu_probe_gtoffset(c); 1031 1032 decode_guest_configs(c); 1033 } 1034 1035 #define R4K_OPTS (MIPS_CPU_TLB | MIPS_CPU_4KEX | MIPS_CPU_4K_CACHE \ 1036 | MIPS_CPU_COUNTER) 1037 1038 static inline void cpu_probe_legacy(struct cpuinfo_mips *c, unsigned int cpu) 1039 { 1040 switch (c->processor_id & PRID_IMP_MASK) { 1041 case PRID_IMP_R2000: 1042 c->cputype = CPU_R2000; 1043 __cpu_name[cpu] = "R2000"; 1044 c->fpu_msk31 |= FPU_CSR_CONDX | FPU_CSR_FS; 1045 c->options = MIPS_CPU_TLB | MIPS_CPU_3K_CACHE | 1046 MIPS_CPU_NOFPUEX; 1047 if (__cpu_has_fpu()) 1048 c->options |= MIPS_CPU_FPU; 1049 c->tlbsize = 64; 1050 break; 1051 case PRID_IMP_R3000: 1052 if ((c->processor_id & PRID_REV_MASK) == PRID_REV_R3000A) { 1053 if (cpu_has_confreg()) { 1054 c->cputype = CPU_R3081E; 1055 __cpu_name[cpu] = "R3081"; 1056 } else { 1057 c->cputype = CPU_R3000A; 1058 __cpu_name[cpu] = "R3000A"; 1059 } 1060 } else { 1061 c->cputype = CPU_R3000; 1062 __cpu_name[cpu] = "R3000"; 1063 } 1064 c->fpu_msk31 |= FPU_CSR_CONDX | FPU_CSR_FS; 1065 c->options = MIPS_CPU_TLB | MIPS_CPU_3K_CACHE | 1066 MIPS_CPU_NOFPUEX; 1067 if (__cpu_has_fpu()) 1068 c->options |= MIPS_CPU_FPU; 1069 c->tlbsize = 64; 1070 break; 1071 case PRID_IMP_R4000: 1072 if (read_c0_config() & CONF_SC) { 1073 if ((c->processor_id & PRID_REV_MASK) >= 1074 PRID_REV_R4400) { 1075 c->cputype = CPU_R4400PC; 1076 __cpu_name[cpu] = "R4400PC"; 1077 } else { 1078 c->cputype = CPU_R4000PC; 1079 __cpu_name[cpu] = "R4000PC"; 1080 } 1081 } else { 1082 int cca = read_c0_config() & CONF_CM_CMASK; 1083 int mc; 1084 1085 /* 1086 * SC and MC versions can't be reliably told apart, 1087 * but only the latter support coherent caching 1088 * modes so assume the firmware has set the KSEG0 1089 * coherency attribute reasonably (if uncached, we 1090 * assume SC). 1091 */ 1092 switch (cca) { 1093 case CONF_CM_CACHABLE_CE: 1094 case CONF_CM_CACHABLE_COW: 1095 case CONF_CM_CACHABLE_CUW: 1096 mc = 1; 1097 break; 1098 default: 1099 mc = 0; 1100 break; 1101 } 1102 if ((c->processor_id & PRID_REV_MASK) >= 1103 PRID_REV_R4400) { 1104 c->cputype = mc ? CPU_R4400MC : CPU_R4400SC; 1105 __cpu_name[cpu] = mc ? "R4400MC" : "R4400SC"; 1106 } else { 1107 c->cputype = mc ? CPU_R4000MC : CPU_R4000SC; 1108 __cpu_name[cpu] = mc ? "R4000MC" : "R4000SC"; 1109 } 1110 } 1111 1112 set_isa(c, MIPS_CPU_ISA_III); 1113 c->fpu_msk31 |= FPU_CSR_CONDX; 1114 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR | 1115 MIPS_CPU_WATCH | MIPS_CPU_VCE | 1116 MIPS_CPU_LLSC; 1117 c->tlbsize = 48; 1118 break; 1119 case PRID_IMP_R4300: 1120 c->cputype = CPU_R4300; 1121 __cpu_name[cpu] = "R4300"; 1122 set_isa(c, MIPS_CPU_ISA_III); 1123 c->fpu_msk31 |= FPU_CSR_CONDX; 1124 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR | 1125 MIPS_CPU_LLSC; 1126 c->tlbsize = 32; 1127 break; 1128 case PRID_IMP_R4600: 1129 c->cputype = CPU_R4600; 1130 __cpu_name[cpu] = "R4600"; 1131 set_isa(c, MIPS_CPU_ISA_III); 1132 c->fpu_msk31 |= FPU_CSR_CONDX; 1133 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR | 1134 MIPS_CPU_LLSC; 1135 c->tlbsize = 48; 1136 break; 1137 #if 0 1138 case PRID_IMP_R4650: 1139 /* 1140 * This processor doesn't have an MMU, so it's not 1141 * "real easy" to run Linux on it. It is left purely 1142 * for documentation. Commented out because it shares 1143 * its c0_prid id number with the TX3900. 1144 */ 1145 c->cputype = CPU_R4650; 1146 __cpu_name[cpu] = "R4650"; 1147 set_isa(c, MIPS_CPU_ISA_III); 1148 c->fpu_msk31 |= FPU_CSR_CONDX; 1149 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_LLSC; 1150 c->tlbsize = 48; 1151 break; 1152 #endif 1153 case PRID_IMP_R4700: 1154 c->cputype = CPU_R4700; 1155 __cpu_name[cpu] = "R4700"; 1156 set_isa(c, MIPS_CPU_ISA_III); 1157 c->fpu_msk31 |= FPU_CSR_CONDX; 1158 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR | 1159 MIPS_CPU_LLSC; 1160 c->tlbsize = 48; 1161 break; 1162 case PRID_IMP_TX49: 1163 c->cputype = CPU_TX49XX; 1164 __cpu_name[cpu] = "R49XX"; 1165 set_isa(c, MIPS_CPU_ISA_III); 1166 c->fpu_msk31 |= FPU_CSR_CONDX; 1167 c->options = R4K_OPTS | MIPS_CPU_LLSC; 1168 if (!(c->processor_id & 0x08)) 1169 c->options |= MIPS_CPU_FPU | MIPS_CPU_32FPR; 1170 c->tlbsize = 48; 1171 break; 1172 case PRID_IMP_R5000: 1173 c->cputype = CPU_R5000; 1174 __cpu_name[cpu] = "R5000"; 1175 set_isa(c, MIPS_CPU_ISA_IV); 1176 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR | 1177 MIPS_CPU_LLSC; 1178 c->tlbsize = 48; 1179 break; 1180 case PRID_IMP_R5500: 1181 c->cputype = CPU_R5500; 1182 __cpu_name[cpu] = "R5500"; 1183 set_isa(c, MIPS_CPU_ISA_IV); 1184 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR | 1185 MIPS_CPU_WATCH | MIPS_CPU_LLSC; 1186 c->tlbsize = 48; 1187 break; 1188 case PRID_IMP_NEVADA: 1189 c->cputype = CPU_NEVADA; 1190 __cpu_name[cpu] = "Nevada"; 1191 set_isa(c, MIPS_CPU_ISA_IV); 1192 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR | 1193 MIPS_CPU_DIVEC | MIPS_CPU_LLSC; 1194 c->tlbsize = 48; 1195 break; 1196 case PRID_IMP_RM7000: 1197 c->cputype = CPU_RM7000; 1198 __cpu_name[cpu] = "RM7000"; 1199 set_isa(c, MIPS_CPU_ISA_IV); 1200 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR | 1201 MIPS_CPU_LLSC; 1202 /* 1203 * Undocumented RM7000: Bit 29 in the info register of 1204 * the RM7000 v2.0 indicates if the TLB has 48 or 64 1205 * entries. 1206 * 1207 * 29 1 => 64 entry JTLB 1208 * 0 => 48 entry JTLB 1209 */ 1210 c->tlbsize = (read_c0_info() & (1 << 29)) ? 64 : 48; 1211 break; 1212 case PRID_IMP_R10000: 1213 c->cputype = CPU_R10000; 1214 __cpu_name[cpu] = "R10000"; 1215 set_isa(c, MIPS_CPU_ISA_IV); 1216 c->options = MIPS_CPU_TLB | MIPS_CPU_4K_CACHE | MIPS_CPU_4KEX | 1217 MIPS_CPU_FPU | MIPS_CPU_32FPR | 1218 MIPS_CPU_COUNTER | MIPS_CPU_WATCH | 1219 MIPS_CPU_LLSC; 1220 c->tlbsize = 64; 1221 break; 1222 case PRID_IMP_R12000: 1223 c->cputype = CPU_R12000; 1224 __cpu_name[cpu] = "R12000"; 1225 set_isa(c, MIPS_CPU_ISA_IV); 1226 c->options = MIPS_CPU_TLB | MIPS_CPU_4K_CACHE | MIPS_CPU_4KEX | 1227 MIPS_CPU_FPU | MIPS_CPU_32FPR | 1228 MIPS_CPU_COUNTER | MIPS_CPU_WATCH | 1229 MIPS_CPU_LLSC; 1230 c->tlbsize = 64; 1231 write_c0_r10k_diag(read_c0_r10k_diag() | R10K_DIAG_E_GHIST); 1232 break; 1233 case PRID_IMP_R14000: 1234 if (((c->processor_id >> 4) & 0x0f) > 2) { 1235 c->cputype = CPU_R16000; 1236 __cpu_name[cpu] = "R16000"; 1237 } else { 1238 c->cputype = CPU_R14000; 1239 __cpu_name[cpu] = "R14000"; 1240 } 1241 set_isa(c, MIPS_CPU_ISA_IV); 1242 c->options = MIPS_CPU_TLB | MIPS_CPU_4K_CACHE | MIPS_CPU_4KEX | 1243 MIPS_CPU_FPU | MIPS_CPU_32FPR | 1244 MIPS_CPU_COUNTER | MIPS_CPU_WATCH | 1245 MIPS_CPU_LLSC; 1246 c->tlbsize = 64; 1247 write_c0_r10k_diag(read_c0_r10k_diag() | R10K_DIAG_E_GHIST); 1248 break; 1249 case PRID_IMP_LOONGSON_64C: /* Loongson-2/3 */ 1250 switch (c->processor_id & PRID_REV_MASK) { 1251 case PRID_REV_LOONGSON2E: 1252 c->cputype = CPU_LOONGSON2EF; 1253 __cpu_name[cpu] = "ICT Loongson-2"; 1254 set_elf_platform(cpu, "loongson2e"); 1255 set_isa(c, MIPS_CPU_ISA_III); 1256 c->fpu_msk31 |= FPU_CSR_CONDX; 1257 break; 1258 case PRID_REV_LOONGSON2F: 1259 c->cputype = CPU_LOONGSON2EF; 1260 __cpu_name[cpu] = "ICT Loongson-2"; 1261 set_elf_platform(cpu, "loongson2f"); 1262 set_isa(c, MIPS_CPU_ISA_III); 1263 c->fpu_msk31 |= FPU_CSR_CONDX; 1264 break; 1265 case PRID_REV_LOONGSON3A_R1: 1266 c->cputype = CPU_LOONGSON64; 1267 __cpu_name[cpu] = "ICT Loongson-3"; 1268 set_elf_platform(cpu, "loongson3a"); 1269 set_isa(c, MIPS_CPU_ISA_M64R1); 1270 c->ases |= (MIPS_ASE_LOONGSON_MMI | MIPS_ASE_LOONGSON_CAM | 1271 MIPS_ASE_LOONGSON_EXT); 1272 break; 1273 case PRID_REV_LOONGSON3B_R1: 1274 case PRID_REV_LOONGSON3B_R2: 1275 c->cputype = CPU_LOONGSON64; 1276 __cpu_name[cpu] = "ICT Loongson-3"; 1277 set_elf_platform(cpu, "loongson3b"); 1278 set_isa(c, MIPS_CPU_ISA_M64R1); 1279 c->ases |= (MIPS_ASE_LOONGSON_MMI | MIPS_ASE_LOONGSON_CAM | 1280 MIPS_ASE_LOONGSON_EXT); 1281 break; 1282 } 1283 1284 c->options = R4K_OPTS | 1285 MIPS_CPU_FPU | MIPS_CPU_LLSC | 1286 MIPS_CPU_32FPR; 1287 c->tlbsize = 64; 1288 set_cpu_asid_mask(c, MIPS_ENTRYHI_ASID); 1289 c->writecombine = _CACHE_UNCACHED_ACCELERATED; 1290 break; 1291 case PRID_IMP_LOONGSON_32: /* Loongson-1 */ 1292 decode_configs(c); 1293 1294 c->cputype = CPU_LOONGSON32; 1295 1296 switch (c->processor_id & PRID_REV_MASK) { 1297 case PRID_REV_LOONGSON1B: 1298 __cpu_name[cpu] = "Loongson 1B"; 1299 break; 1300 } 1301 1302 break; 1303 } 1304 } 1305 1306 static inline void cpu_probe_mips(struct cpuinfo_mips *c, unsigned int cpu) 1307 { 1308 c->writecombine = _CACHE_UNCACHED_ACCELERATED; 1309 switch (c->processor_id & PRID_IMP_MASK) { 1310 case PRID_IMP_QEMU_GENERIC: 1311 c->writecombine = _CACHE_UNCACHED; 1312 c->cputype = CPU_QEMU_GENERIC; 1313 __cpu_name[cpu] = "MIPS GENERIC QEMU"; 1314 break; 1315 case PRID_IMP_4KC: 1316 c->cputype = CPU_4KC; 1317 c->writecombine = _CACHE_UNCACHED; 1318 __cpu_name[cpu] = "MIPS 4Kc"; 1319 break; 1320 case PRID_IMP_4KEC: 1321 case PRID_IMP_4KECR2: 1322 c->cputype = CPU_4KEC; 1323 c->writecombine = _CACHE_UNCACHED; 1324 __cpu_name[cpu] = "MIPS 4KEc"; 1325 break; 1326 case PRID_IMP_4KSC: 1327 case PRID_IMP_4KSD: 1328 c->cputype = CPU_4KSC; 1329 c->writecombine = _CACHE_UNCACHED; 1330 __cpu_name[cpu] = "MIPS 4KSc"; 1331 break; 1332 case PRID_IMP_5KC: 1333 c->cputype = CPU_5KC; 1334 c->writecombine = _CACHE_UNCACHED; 1335 __cpu_name[cpu] = "MIPS 5Kc"; 1336 break; 1337 case PRID_IMP_5KE: 1338 c->cputype = CPU_5KE; 1339 c->writecombine = _CACHE_UNCACHED; 1340 __cpu_name[cpu] = "MIPS 5KE"; 1341 break; 1342 case PRID_IMP_20KC: 1343 c->cputype = CPU_20KC; 1344 c->writecombine = _CACHE_UNCACHED; 1345 __cpu_name[cpu] = "MIPS 20Kc"; 1346 break; 1347 case PRID_IMP_24K: 1348 c->cputype = CPU_24K; 1349 c->writecombine = _CACHE_UNCACHED; 1350 __cpu_name[cpu] = "MIPS 24Kc"; 1351 break; 1352 case PRID_IMP_24KE: 1353 c->cputype = CPU_24K; 1354 c->writecombine = _CACHE_UNCACHED; 1355 __cpu_name[cpu] = "MIPS 24KEc"; 1356 break; 1357 case PRID_IMP_25KF: 1358 c->cputype = CPU_25KF; 1359 c->writecombine = _CACHE_UNCACHED; 1360 __cpu_name[cpu] = "MIPS 25Kc"; 1361 break; 1362 case PRID_IMP_34K: 1363 c->cputype = CPU_34K; 1364 c->writecombine = _CACHE_UNCACHED; 1365 __cpu_name[cpu] = "MIPS 34Kc"; 1366 cpu_set_mt_per_tc_perf(c); 1367 break; 1368 case PRID_IMP_74K: 1369 c->cputype = CPU_74K; 1370 c->writecombine = _CACHE_UNCACHED; 1371 __cpu_name[cpu] = "MIPS 74Kc"; 1372 break; 1373 case PRID_IMP_M14KC: 1374 c->cputype = CPU_M14KC; 1375 c->writecombine = _CACHE_UNCACHED; 1376 __cpu_name[cpu] = "MIPS M14Kc"; 1377 break; 1378 case PRID_IMP_M14KEC: 1379 c->cputype = CPU_M14KEC; 1380 c->writecombine = _CACHE_UNCACHED; 1381 __cpu_name[cpu] = "MIPS M14KEc"; 1382 break; 1383 case PRID_IMP_1004K: 1384 c->cputype = CPU_1004K; 1385 c->writecombine = _CACHE_UNCACHED; 1386 __cpu_name[cpu] = "MIPS 1004Kc"; 1387 cpu_set_mt_per_tc_perf(c); 1388 break; 1389 case PRID_IMP_1074K: 1390 c->cputype = CPU_1074K; 1391 c->writecombine = _CACHE_UNCACHED; 1392 __cpu_name[cpu] = "MIPS 1074Kc"; 1393 break; 1394 case PRID_IMP_INTERAPTIV_UP: 1395 c->cputype = CPU_INTERAPTIV; 1396 __cpu_name[cpu] = "MIPS interAptiv"; 1397 cpu_set_mt_per_tc_perf(c); 1398 break; 1399 case PRID_IMP_INTERAPTIV_MP: 1400 c->cputype = CPU_INTERAPTIV; 1401 __cpu_name[cpu] = "MIPS interAptiv (multi)"; 1402 cpu_set_mt_per_tc_perf(c); 1403 break; 1404 case PRID_IMP_PROAPTIV_UP: 1405 c->cputype = CPU_PROAPTIV; 1406 __cpu_name[cpu] = "MIPS proAptiv"; 1407 break; 1408 case PRID_IMP_PROAPTIV_MP: 1409 c->cputype = CPU_PROAPTIV; 1410 __cpu_name[cpu] = "MIPS proAptiv (multi)"; 1411 break; 1412 case PRID_IMP_P5600: 1413 c->cputype = CPU_P5600; 1414 __cpu_name[cpu] = "MIPS P5600"; 1415 break; 1416 case PRID_IMP_P6600: 1417 c->cputype = CPU_P6600; 1418 __cpu_name[cpu] = "MIPS P6600"; 1419 break; 1420 case PRID_IMP_I6400: 1421 c->cputype = CPU_I6400; 1422 __cpu_name[cpu] = "MIPS I6400"; 1423 break; 1424 case PRID_IMP_I6500: 1425 c->cputype = CPU_I6500; 1426 __cpu_name[cpu] = "MIPS I6500"; 1427 break; 1428 case PRID_IMP_M5150: 1429 c->cputype = CPU_M5150; 1430 __cpu_name[cpu] = "MIPS M5150"; 1431 break; 1432 case PRID_IMP_M6250: 1433 c->cputype = CPU_M6250; 1434 __cpu_name[cpu] = "MIPS M6250"; 1435 break; 1436 } 1437 1438 decode_configs(c); 1439 1440 spram_config(); 1441 1442 mm_config(c); 1443 1444 switch (__get_cpu_type(c->cputype)) { 1445 case CPU_M5150: 1446 case CPU_P5600: 1447 set_isa(c, MIPS_CPU_ISA_M32R5); 1448 break; 1449 case CPU_I6500: 1450 c->options |= MIPS_CPU_SHARED_FTLB_ENTRIES; 1451 fallthrough; 1452 case CPU_I6400: 1453 c->options |= MIPS_CPU_SHARED_FTLB_RAM; 1454 fallthrough; 1455 default: 1456 break; 1457 } 1458 1459 /* Recent MIPS cores use the implementation-dependent ExcCode 16 for 1460 * cache/FTLB parity exceptions. 1461 */ 1462 switch (__get_cpu_type(c->cputype)) { 1463 case CPU_PROAPTIV: 1464 case CPU_P5600: 1465 case CPU_P6600: 1466 case CPU_I6400: 1467 case CPU_I6500: 1468 c->options |= MIPS_CPU_FTLBPAREX; 1469 break; 1470 } 1471 } 1472 1473 static inline void cpu_probe_alchemy(struct cpuinfo_mips *c, unsigned int cpu) 1474 { 1475 decode_configs(c); 1476 switch (c->processor_id & PRID_IMP_MASK) { 1477 case PRID_IMP_AU1_REV1: 1478 case PRID_IMP_AU1_REV2: 1479 c->cputype = CPU_ALCHEMY; 1480 switch ((c->processor_id >> 24) & 0xff) { 1481 case 0: 1482 __cpu_name[cpu] = "Au1000"; 1483 break; 1484 case 1: 1485 __cpu_name[cpu] = "Au1500"; 1486 break; 1487 case 2: 1488 __cpu_name[cpu] = "Au1100"; 1489 break; 1490 case 3: 1491 __cpu_name[cpu] = "Au1550"; 1492 break; 1493 case 4: 1494 __cpu_name[cpu] = "Au1200"; 1495 if ((c->processor_id & PRID_REV_MASK) == 2) 1496 __cpu_name[cpu] = "Au1250"; 1497 break; 1498 case 5: 1499 __cpu_name[cpu] = "Au1210"; 1500 break; 1501 default: 1502 __cpu_name[cpu] = "Au1xxx"; 1503 break; 1504 } 1505 break; 1506 case PRID_IMP_NETLOGIC_AU13XX: 1507 c->cputype = CPU_ALCHEMY; 1508 __cpu_name[cpu] = "Au1300"; 1509 break; 1510 } 1511 } 1512 1513 static inline void cpu_probe_sibyte(struct cpuinfo_mips *c, unsigned int cpu) 1514 { 1515 decode_configs(c); 1516 1517 c->writecombine = _CACHE_UNCACHED_ACCELERATED; 1518 switch (c->processor_id & PRID_IMP_MASK) { 1519 case PRID_IMP_SB1: 1520 c->cputype = CPU_SB1; 1521 __cpu_name[cpu] = "SiByte SB1"; 1522 /* FPU in pass1 is known to have issues. */ 1523 if ((c->processor_id & PRID_REV_MASK) < 0x02) 1524 c->options &= ~(MIPS_CPU_FPU | MIPS_CPU_32FPR); 1525 break; 1526 case PRID_IMP_SB1A: 1527 c->cputype = CPU_SB1A; 1528 __cpu_name[cpu] = "SiByte SB1A"; 1529 break; 1530 } 1531 } 1532 1533 static inline void cpu_probe_sandcraft(struct cpuinfo_mips *c, unsigned int cpu) 1534 { 1535 decode_configs(c); 1536 switch (c->processor_id & PRID_IMP_MASK) { 1537 case PRID_IMP_SR71000: 1538 c->cputype = CPU_SR71000; 1539 __cpu_name[cpu] = "Sandcraft SR71000"; 1540 c->scache.ways = 8; 1541 c->tlbsize = 64; 1542 break; 1543 } 1544 } 1545 1546 static inline void cpu_probe_nxp(struct cpuinfo_mips *c, unsigned int cpu) 1547 { 1548 decode_configs(c); 1549 switch (c->processor_id & PRID_IMP_MASK) { 1550 case PRID_IMP_PR4450: 1551 c->cputype = CPU_PR4450; 1552 __cpu_name[cpu] = "Philips PR4450"; 1553 set_isa(c, MIPS_CPU_ISA_M32R1); 1554 break; 1555 } 1556 } 1557 1558 static inline void cpu_probe_broadcom(struct cpuinfo_mips *c, unsigned int cpu) 1559 { 1560 decode_configs(c); 1561 switch (c->processor_id & PRID_IMP_MASK) { 1562 case PRID_IMP_BMIPS32_REV4: 1563 case PRID_IMP_BMIPS32_REV8: 1564 c->cputype = CPU_BMIPS32; 1565 __cpu_name[cpu] = "Broadcom BMIPS32"; 1566 set_elf_platform(cpu, "bmips32"); 1567 break; 1568 case PRID_IMP_BMIPS3300: 1569 case PRID_IMP_BMIPS3300_ALT: 1570 case PRID_IMP_BMIPS3300_BUG: 1571 c->cputype = CPU_BMIPS3300; 1572 __cpu_name[cpu] = "Broadcom BMIPS3300"; 1573 set_elf_platform(cpu, "bmips3300"); 1574 reserve_exception_space(0x400, VECTORSPACING * 64); 1575 break; 1576 case PRID_IMP_BMIPS43XX: { 1577 int rev = c->processor_id & PRID_REV_MASK; 1578 1579 if (rev >= PRID_REV_BMIPS4380_LO && 1580 rev <= PRID_REV_BMIPS4380_HI) { 1581 c->cputype = CPU_BMIPS4380; 1582 __cpu_name[cpu] = "Broadcom BMIPS4380"; 1583 set_elf_platform(cpu, "bmips4380"); 1584 c->options |= MIPS_CPU_RIXI; 1585 reserve_exception_space(0x400, VECTORSPACING * 64); 1586 } else { 1587 c->cputype = CPU_BMIPS4350; 1588 __cpu_name[cpu] = "Broadcom BMIPS4350"; 1589 set_elf_platform(cpu, "bmips4350"); 1590 } 1591 break; 1592 } 1593 case PRID_IMP_BMIPS5000: 1594 case PRID_IMP_BMIPS5200: 1595 c->cputype = CPU_BMIPS5000; 1596 if ((c->processor_id & PRID_IMP_MASK) == PRID_IMP_BMIPS5200) 1597 __cpu_name[cpu] = "Broadcom BMIPS5200"; 1598 else 1599 __cpu_name[cpu] = "Broadcom BMIPS5000"; 1600 set_elf_platform(cpu, "bmips5000"); 1601 c->options |= MIPS_CPU_ULRI | MIPS_CPU_RIXI; 1602 reserve_exception_space(0x1000, VECTORSPACING * 64); 1603 break; 1604 } 1605 } 1606 1607 static inline void cpu_probe_cavium(struct cpuinfo_mips *c, unsigned int cpu) 1608 { 1609 decode_configs(c); 1610 /* Octeon has different cache interface */ 1611 c->options &= ~MIPS_CPU_4K_CACHE; 1612 switch (c->processor_id & PRID_IMP_MASK) { 1613 case PRID_IMP_CAVIUM_CN38XX: 1614 case PRID_IMP_CAVIUM_CN31XX: 1615 case PRID_IMP_CAVIUM_CN30XX: 1616 c->cputype = CPU_CAVIUM_OCTEON; 1617 __cpu_name[cpu] = "Cavium Octeon"; 1618 goto platform; 1619 case PRID_IMP_CAVIUM_CN58XX: 1620 case PRID_IMP_CAVIUM_CN56XX: 1621 case PRID_IMP_CAVIUM_CN50XX: 1622 case PRID_IMP_CAVIUM_CN52XX: 1623 c->cputype = CPU_CAVIUM_OCTEON_PLUS; 1624 __cpu_name[cpu] = "Cavium Octeon+"; 1625 platform: 1626 set_elf_platform(cpu, "octeon"); 1627 break; 1628 case PRID_IMP_CAVIUM_CN61XX: 1629 case PRID_IMP_CAVIUM_CN63XX: 1630 case PRID_IMP_CAVIUM_CN66XX: 1631 case PRID_IMP_CAVIUM_CN68XX: 1632 case PRID_IMP_CAVIUM_CNF71XX: 1633 c->cputype = CPU_CAVIUM_OCTEON2; 1634 __cpu_name[cpu] = "Cavium Octeon II"; 1635 set_elf_platform(cpu, "octeon2"); 1636 break; 1637 case PRID_IMP_CAVIUM_CN70XX: 1638 case PRID_IMP_CAVIUM_CN73XX: 1639 case PRID_IMP_CAVIUM_CNF75XX: 1640 case PRID_IMP_CAVIUM_CN78XX: 1641 c->cputype = CPU_CAVIUM_OCTEON3; 1642 __cpu_name[cpu] = "Cavium Octeon III"; 1643 set_elf_platform(cpu, "octeon3"); 1644 break; 1645 default: 1646 printk(KERN_INFO "Unknown Octeon chip!\n"); 1647 c->cputype = CPU_UNKNOWN; 1648 break; 1649 } 1650 } 1651 1652 #ifdef CONFIG_CPU_LOONGSON64 1653 #include <loongson_regs.h> 1654 1655 static inline void decode_cpucfg(struct cpuinfo_mips *c) 1656 { 1657 u32 cfg1 = read_cpucfg(LOONGSON_CFG1); 1658 u32 cfg2 = read_cpucfg(LOONGSON_CFG2); 1659 u32 cfg3 = read_cpucfg(LOONGSON_CFG3); 1660 1661 if (cfg1 & LOONGSON_CFG1_MMI) 1662 c->ases |= MIPS_ASE_LOONGSON_MMI; 1663 1664 if (cfg2 & LOONGSON_CFG2_LEXT1) 1665 c->ases |= MIPS_ASE_LOONGSON_EXT; 1666 1667 if (cfg2 & LOONGSON_CFG2_LEXT2) 1668 c->ases |= MIPS_ASE_LOONGSON_EXT2; 1669 1670 if (cfg2 & LOONGSON_CFG2_LSPW) { 1671 c->options |= MIPS_CPU_LDPTE; 1672 c->guest.options |= MIPS_CPU_LDPTE; 1673 } 1674 1675 if (cfg3 & LOONGSON_CFG3_LCAMP) 1676 c->ases |= MIPS_ASE_LOONGSON_CAM; 1677 } 1678 1679 static inline void cpu_probe_loongson(struct cpuinfo_mips *c, unsigned int cpu) 1680 { 1681 c->cputype = CPU_LOONGSON64; 1682 1683 /* All Loongson processors covered here define ExcCode 16 as GSExc. */ 1684 decode_configs(c); 1685 c->options |= MIPS_CPU_GSEXCEX; 1686 1687 switch (c->processor_id & PRID_IMP_MASK) { 1688 case PRID_IMP_LOONGSON_64R: /* Loongson-64 Reduced */ 1689 switch (c->processor_id & PRID_REV_MASK) { 1690 case PRID_REV_LOONGSON2K_R1_0: 1691 case PRID_REV_LOONGSON2K_R1_1: 1692 case PRID_REV_LOONGSON2K_R1_2: 1693 case PRID_REV_LOONGSON2K_R1_3: 1694 __cpu_name[cpu] = "Loongson-2K"; 1695 set_elf_platform(cpu, "gs264e"); 1696 set_isa(c, MIPS_CPU_ISA_M64R2); 1697 break; 1698 } 1699 c->ases |= (MIPS_ASE_LOONGSON_MMI | MIPS_ASE_LOONGSON_EXT | 1700 MIPS_ASE_LOONGSON_EXT2); 1701 break; 1702 case PRID_IMP_LOONGSON_64C: /* Loongson-3 Classic */ 1703 switch (c->processor_id & PRID_REV_MASK) { 1704 case PRID_REV_LOONGSON3A_R2_0: 1705 case PRID_REV_LOONGSON3A_R2_1: 1706 __cpu_name[cpu] = "ICT Loongson-3"; 1707 set_elf_platform(cpu, "loongson3a"); 1708 set_isa(c, MIPS_CPU_ISA_M64R2); 1709 break; 1710 case PRID_REV_LOONGSON3A_R3_0: 1711 case PRID_REV_LOONGSON3A_R3_1: 1712 __cpu_name[cpu] = "ICT Loongson-3"; 1713 set_elf_platform(cpu, "loongson3a"); 1714 set_isa(c, MIPS_CPU_ISA_M64R2); 1715 break; 1716 } 1717 /* 1718 * Loongson-3 Classic did not implement MIPS standard TLBINV 1719 * but implemented TLBINVF and EHINV. As currently we're only 1720 * using these two features, enable MIPS_CPU_TLBINV as well. 1721 * 1722 * Also some early Loongson-3A2000 had wrong TLB type in Config 1723 * register, we correct it here. 1724 */ 1725 c->options |= MIPS_CPU_FTLB | MIPS_CPU_TLBINV | MIPS_CPU_LDPTE; 1726 c->ases |= (MIPS_ASE_LOONGSON_MMI | MIPS_ASE_LOONGSON_CAM | 1727 MIPS_ASE_LOONGSON_EXT | MIPS_ASE_LOONGSON_EXT2); 1728 c->ases &= ~MIPS_ASE_VZ; /* VZ of Loongson-3A2000/3000 is incomplete */ 1729 change_c0_config6(LOONGSON_CONF6_EXTIMER | LOONGSON_CONF6_INTIMER, 1730 LOONGSON_CONF6_INTIMER); 1731 break; 1732 case PRID_IMP_LOONGSON_64G: 1733 __cpu_name[cpu] = "ICT Loongson-3"; 1734 set_elf_platform(cpu, "loongson3a"); 1735 set_isa(c, MIPS_CPU_ISA_M64R2); 1736 decode_cpucfg(c); 1737 change_c0_config6(LOONGSON_CONF6_EXTIMER | LOONGSON_CONF6_INTIMER, 1738 LOONGSON_CONF6_INTIMER); 1739 break; 1740 default: 1741 panic("Unknown Loongson Processor ID!"); 1742 break; 1743 } 1744 } 1745 #else 1746 static inline void cpu_probe_loongson(struct cpuinfo_mips *c, unsigned int cpu) { } 1747 #endif 1748 1749 static inline void cpu_probe_ingenic(struct cpuinfo_mips *c, unsigned int cpu) 1750 { 1751 decode_configs(c); 1752 1753 /* 1754 * XBurst misses a config2 register, so config3 decode was skipped in 1755 * decode_configs(). 1756 */ 1757 decode_config3(c); 1758 1759 /* XBurst does not implement the CP0 counter. */ 1760 c->options &= ~MIPS_CPU_COUNTER; 1761 BUG_ON(__builtin_constant_p(cpu_has_counter) && cpu_has_counter); 1762 1763 /* XBurst has virtually tagged icache */ 1764 c->icache.flags |= MIPS_CACHE_VTAG; 1765 1766 switch (c->processor_id & PRID_IMP_MASK) { 1767 1768 /* XBurst®1 with MXU1.0/MXU1.1 SIMD ISA */ 1769 case PRID_IMP_XBURST_REV1: 1770 1771 /* 1772 * The XBurst core by default attempts to avoid branch target 1773 * buffer lookups by detecting & special casing loops. This 1774 * feature will cause BogoMIPS and lpj calculate in error. 1775 * Set cp0 config7 bit 4 to disable this feature. 1776 */ 1777 set_c0_config7(MIPS_CONF7_BTB_LOOP_EN); 1778 1779 switch (c->processor_id & PRID_COMP_MASK) { 1780 1781 /* 1782 * The config0 register in the XBurst CPUs with a processor ID of 1783 * PRID_COMP_INGENIC_D0 report themselves as MIPS32r2 compatible, 1784 * but they don't actually support this ISA. 1785 */ 1786 case PRID_COMP_INGENIC_D0: 1787 c->isa_level &= ~MIPS_CPU_ISA_M32R2; 1788 1789 /* FPU is not properly detected on JZ4760(B). */ 1790 if (c->processor_id == 0x2ed0024f) 1791 c->options |= MIPS_CPU_FPU; 1792 1793 fallthrough; 1794 1795 /* 1796 * The config0 register in the XBurst CPUs with a processor ID of 1797 * PRID_COMP_INGENIC_D0 or PRID_COMP_INGENIC_D1 has an abandoned 1798 * huge page tlb mode, this mode is not compatible with the MIPS 1799 * standard, it will cause tlbmiss and into an infinite loop 1800 * (line 21 in the tlb-funcs.S) when starting the init process. 1801 * After chip reset, the default is HPTLB mode, Write 0xa9000000 1802 * to cp0 register 5 sel 4 to switch back to VTLB mode to prevent 1803 * getting stuck. 1804 */ 1805 case PRID_COMP_INGENIC_D1: 1806 write_c0_page_ctrl(XBURST_PAGECTRL_HPTLB_DIS); 1807 break; 1808 1809 default: 1810 break; 1811 } 1812 fallthrough; 1813 1814 /* XBurst®1 with MXU2.0 SIMD ISA */ 1815 case PRID_IMP_XBURST_REV2: 1816 /* Ingenic uses the WA bit to achieve write-combine memory writes */ 1817 c->writecombine = _CACHE_CACHABLE_WA; 1818 c->cputype = CPU_XBURST; 1819 __cpu_name[cpu] = "Ingenic XBurst"; 1820 break; 1821 1822 /* XBurst®2 with MXU2.1 SIMD ISA */ 1823 case PRID_IMP_XBURST2: 1824 c->cputype = CPU_XBURST; 1825 __cpu_name[cpu] = "Ingenic XBurst II"; 1826 break; 1827 1828 default: 1829 panic("Unknown Ingenic Processor ID!"); 1830 break; 1831 } 1832 } 1833 1834 #ifdef CONFIG_64BIT 1835 /* For use by uaccess.h */ 1836 u64 __ua_limit; 1837 EXPORT_SYMBOL(__ua_limit); 1838 #endif 1839 1840 const char *__cpu_name[NR_CPUS]; 1841 const char *__elf_platform; 1842 const char *__elf_base_platform; 1843 1844 void cpu_probe(void) 1845 { 1846 struct cpuinfo_mips *c = ¤t_cpu_data; 1847 unsigned int cpu = smp_processor_id(); 1848 1849 /* 1850 * Set a default elf platform, cpu probe may later 1851 * overwrite it with a more precise value 1852 */ 1853 set_elf_platform(cpu, "mips"); 1854 1855 c->processor_id = PRID_IMP_UNKNOWN; 1856 c->fpu_id = FPIR_IMP_NONE; 1857 c->cputype = CPU_UNKNOWN; 1858 c->writecombine = _CACHE_UNCACHED; 1859 1860 c->fpu_csr31 = FPU_CSR_RN; 1861 c->fpu_msk31 = FPU_CSR_RSVD | FPU_CSR_ABS2008 | FPU_CSR_NAN2008; 1862 1863 c->processor_id = read_c0_prid(); 1864 switch (c->processor_id & PRID_COMP_MASK) { 1865 case PRID_COMP_LEGACY: 1866 cpu_probe_legacy(c, cpu); 1867 break; 1868 case PRID_COMP_MIPS: 1869 cpu_probe_mips(c, cpu); 1870 break; 1871 case PRID_COMP_ALCHEMY: 1872 case PRID_COMP_NETLOGIC: 1873 cpu_probe_alchemy(c, cpu); 1874 break; 1875 case PRID_COMP_SIBYTE: 1876 cpu_probe_sibyte(c, cpu); 1877 break; 1878 case PRID_COMP_BROADCOM: 1879 cpu_probe_broadcom(c, cpu); 1880 break; 1881 case PRID_COMP_SANDCRAFT: 1882 cpu_probe_sandcraft(c, cpu); 1883 break; 1884 case PRID_COMP_NXP: 1885 cpu_probe_nxp(c, cpu); 1886 break; 1887 case PRID_COMP_CAVIUM: 1888 cpu_probe_cavium(c, cpu); 1889 break; 1890 case PRID_COMP_LOONGSON: 1891 cpu_probe_loongson(c, cpu); 1892 break; 1893 case PRID_COMP_INGENIC_13: 1894 case PRID_COMP_INGENIC_D0: 1895 case PRID_COMP_INGENIC_D1: 1896 case PRID_COMP_INGENIC_E1: 1897 cpu_probe_ingenic(c, cpu); 1898 break; 1899 } 1900 1901 BUG_ON(!__cpu_name[cpu]); 1902 BUG_ON(c->cputype == CPU_UNKNOWN); 1903 1904 /* 1905 * Platform code can force the cpu type to optimize code 1906 * generation. In that case be sure the cpu type is correctly 1907 * manually setup otherwise it could trigger some nasty bugs. 1908 */ 1909 BUG_ON(current_cpu_type() != c->cputype); 1910 1911 if (cpu_has_rixi) { 1912 /* Enable the RIXI exceptions */ 1913 set_c0_pagegrain(PG_IEC); 1914 back_to_back_c0_hazard(); 1915 /* Verify the IEC bit is set */ 1916 if (read_c0_pagegrain() & PG_IEC) 1917 c->options |= MIPS_CPU_RIXIEX; 1918 } 1919 1920 if (mips_fpu_disabled) 1921 c->options &= ~MIPS_CPU_FPU; 1922 1923 if (mips_dsp_disabled) 1924 c->ases &= ~(MIPS_ASE_DSP | MIPS_ASE_DSP2P); 1925 1926 if (mips_htw_disabled) { 1927 c->options &= ~MIPS_CPU_HTW; 1928 write_c0_pwctl(read_c0_pwctl() & 1929 ~(1 << MIPS_PWCTL_PWEN_SHIFT)); 1930 } 1931 1932 if (c->options & MIPS_CPU_FPU) 1933 cpu_set_fpu_opts(c); 1934 else 1935 cpu_set_nofpu_opts(c); 1936 1937 if (cpu_has_mips_r2_r6) { 1938 c->srsets = ((read_c0_srsctl() >> 26) & 0x0f) + 1; 1939 /* R2 has Performance Counter Interrupt indicator */ 1940 c->options |= MIPS_CPU_PCI; 1941 } 1942 else 1943 c->srsets = 1; 1944 1945 if (cpu_has_mips_r6) 1946 elf_hwcap |= HWCAP_MIPS_R6; 1947 1948 if (cpu_has_msa) { 1949 c->msa_id = cpu_get_msa_id(); 1950 WARN(c->msa_id & MSA_IR_WRPF, 1951 "Vector register partitioning unimplemented!"); 1952 elf_hwcap |= HWCAP_MIPS_MSA; 1953 } 1954 1955 if (cpu_has_mips16) 1956 elf_hwcap |= HWCAP_MIPS_MIPS16; 1957 1958 if (cpu_has_mdmx) 1959 elf_hwcap |= HWCAP_MIPS_MDMX; 1960 1961 if (cpu_has_mips3d) 1962 elf_hwcap |= HWCAP_MIPS_MIPS3D; 1963 1964 if (cpu_has_smartmips) 1965 elf_hwcap |= HWCAP_MIPS_SMARTMIPS; 1966 1967 if (cpu_has_dsp) 1968 elf_hwcap |= HWCAP_MIPS_DSP; 1969 1970 if (cpu_has_dsp2) 1971 elf_hwcap |= HWCAP_MIPS_DSP2; 1972 1973 if (cpu_has_dsp3) 1974 elf_hwcap |= HWCAP_MIPS_DSP3; 1975 1976 if (cpu_has_mips16e2) 1977 elf_hwcap |= HWCAP_MIPS_MIPS16E2; 1978 1979 if (cpu_has_loongson_mmi) 1980 elf_hwcap |= HWCAP_LOONGSON_MMI; 1981 1982 if (cpu_has_loongson_ext) 1983 elf_hwcap |= HWCAP_LOONGSON_EXT; 1984 1985 if (cpu_has_loongson_ext2) 1986 elf_hwcap |= HWCAP_LOONGSON_EXT2; 1987 1988 if (cpu_has_vz) 1989 cpu_probe_vz(c); 1990 1991 cpu_probe_vmbits(c); 1992 1993 /* Synthesize CPUCFG data if running on Loongson processors; 1994 * no-op otherwise. 1995 * 1996 * This looks at previously probed features, so keep this at bottom. 1997 */ 1998 loongson3_cpucfg_synthesize_data(c); 1999 2000 #ifdef CONFIG_64BIT 2001 if (cpu == 0) 2002 __ua_limit = ~((1ull << cpu_vmbits) - 1); 2003 #endif 2004 2005 reserve_exception_space(0, 0x1000); 2006 } 2007 2008 void cpu_report(void) 2009 { 2010 struct cpuinfo_mips *c = ¤t_cpu_data; 2011 2012 pr_info("CPU%d revision is: %08x (%s)\n", 2013 smp_processor_id(), c->processor_id, cpu_name_string()); 2014 if (c->options & MIPS_CPU_FPU) 2015 printk(KERN_INFO "FPU revision is: %08x\n", c->fpu_id); 2016 if (cpu_has_msa) 2017 pr_info("MSA revision is: %08x\n", c->msa_id); 2018 } 2019 2020 void cpu_set_cluster(struct cpuinfo_mips *cpuinfo, unsigned int cluster) 2021 { 2022 /* Ensure the core number fits in the field */ 2023 WARN_ON(cluster > (MIPS_GLOBALNUMBER_CLUSTER >> 2024 MIPS_GLOBALNUMBER_CLUSTER_SHF)); 2025 2026 cpuinfo->globalnumber &= ~MIPS_GLOBALNUMBER_CLUSTER; 2027 cpuinfo->globalnumber |= cluster << MIPS_GLOBALNUMBER_CLUSTER_SHF; 2028 } 2029 2030 void cpu_set_core(struct cpuinfo_mips *cpuinfo, unsigned int core) 2031 { 2032 /* Ensure the core number fits in the field */ 2033 WARN_ON(core > (MIPS_GLOBALNUMBER_CORE >> MIPS_GLOBALNUMBER_CORE_SHF)); 2034 2035 cpuinfo->globalnumber &= ~MIPS_GLOBALNUMBER_CORE; 2036 cpuinfo->globalnumber |= core << MIPS_GLOBALNUMBER_CORE_SHF; 2037 } 2038 2039 void cpu_set_vpe_id(struct cpuinfo_mips *cpuinfo, unsigned int vpe) 2040 { 2041 /* Ensure the VP(E) ID fits in the field */ 2042 WARN_ON(vpe > (MIPS_GLOBALNUMBER_VP >> MIPS_GLOBALNUMBER_VP_SHF)); 2043 2044 /* Ensure we're not using VP(E)s without support */ 2045 WARN_ON(vpe && !IS_ENABLED(CONFIG_MIPS_MT_SMP) && 2046 !IS_ENABLED(CONFIG_CPU_MIPSR6)); 2047 2048 cpuinfo->globalnumber &= ~MIPS_GLOBALNUMBER_VP; 2049 cpuinfo->globalnumber |= vpe << MIPS_GLOBALNUMBER_VP_SHF; 2050 } 2051 2052 void cpu_disable_mmid(void) 2053 { 2054 int i; 2055 unsigned long asid_mask; 2056 unsigned int cpu = smp_processor_id(); 2057 struct cpuinfo_mips *c = ¤t_cpu_data; 2058 unsigned int config4 = read_c0_config4(); 2059 unsigned int config5 = read_c0_config5(); 2060 2061 /* Setup the initial ASID mask based on config4 */ 2062 asid_mask = MIPS_ENTRYHI_ASID; 2063 if (config4 & MIPS_CONF4_AE) 2064 asid_mask |= MIPS_ENTRYHI_ASIDX; 2065 set_cpu_asid_mask(c, asid_mask); 2066 2067 /* Disable MMID in the C0 and update cpuinfo_mips accordingly */ 2068 config5 &= ~(MIPS_CONF5_UFR | MIPS_CONF5_UFE); 2069 config5 &= ~MIPS_CONF5_MI; 2070 write_c0_config5(config5); 2071 /* Ensure the write to config5 above takes effect */ 2072 back_to_back_c0_hazard(); 2073 c->options &= ~MIPS_CPU_MMID; 2074 2075 /* Setup asid cache value cleared in per_cpu_trap_init() */ 2076 cpu_data[cpu].asid_cache = asid_first_version(cpu); 2077 2078 /* Reinit context for each CPU */ 2079 for_each_possible_cpu(i) 2080 set_cpu_context(i, &init_mm, 0); 2081 2082 /* Ensure that now MMID will be seen as disable */ 2083 mmid_disabled_quirk = true; 2084 2085 pr_info("MMID support disabled due to hardware support issue\n"); 2086 } 2087