1 /* 2 * Processor capabilities determination functions. 3 * 4 * Copyright (C) xxxx the Anonymous 5 * Copyright (C) 2003 Maciej W. Rozycki 6 * Copyright (C) 1994 - 2003 Ralf Baechle 7 * Copyright (C) 2001 MIPS Inc. 8 * 9 * This program is free software; you can redistribute it and/or 10 * modify it under the terms of the GNU General Public License 11 * as published by the Free Software Foundation; either version 12 * 2 of the License, or (at your option) any later version. 13 */ 14 #include <linux/config.h> 15 #include <linux/init.h> 16 #include <linux/kernel.h> 17 #include <linux/ptrace.h> 18 #include <linux/stddef.h> 19 20 #include <asm/bugs.h> 21 #include <asm/cpu.h> 22 #include <asm/fpu.h> 23 #include <asm/mipsregs.h> 24 #include <asm/system.h> 25 26 /* 27 * Not all of the MIPS CPUs have the "wait" instruction available. Moreover, 28 * the implementation of the "wait" feature differs between CPU families. This 29 * points to the function that implements CPU specific wait. 30 * The wait instruction stops the pipeline and reduces the power consumption of 31 * the CPU very much. 32 */ 33 void (*cpu_wait)(void) = NULL; 34 35 static void r3081_wait(void) 36 { 37 unsigned long cfg = read_c0_conf(); 38 write_c0_conf(cfg | R30XX_CONF_HALT); 39 } 40 41 static void r39xx_wait(void) 42 { 43 unsigned long cfg = read_c0_conf(); 44 write_c0_conf(cfg | TX39_CONF_HALT); 45 } 46 47 static void r4k_wait(void) 48 { 49 __asm__(".set\tmips3\n\t" 50 "wait\n\t" 51 ".set\tmips0"); 52 } 53 54 /* 55 * The Au1xxx wait is available only if we run CONFIG_PM and 56 * the timer setup found we had a 32KHz counter available. 57 * There are still problems with functions that may call au1k_wait 58 * directly, but that will be discovered pretty quickly. 59 */ 60 extern void (*au1k_wait_ptr)(void); 61 62 void au1k_wait(void) 63 { 64 #ifdef CONFIG_PM 65 /* using the wait instruction makes CP0 counter unusable */ 66 __asm__(".set\tmips3\n\t" 67 "wait\n\t" 68 "nop\n\t" 69 "nop\n\t" 70 "nop\n\t" 71 "nop\n\t" 72 ".set\tmips0"); 73 #else 74 __asm__("nop\n\t" 75 "nop"); 76 #endif 77 } 78 79 static inline void check_wait(void) 80 { 81 struct cpuinfo_mips *c = ¤t_cpu_data; 82 83 printk("Checking for 'wait' instruction... "); 84 switch (c->cputype) { 85 case CPU_R3081: 86 case CPU_R3081E: 87 cpu_wait = r3081_wait; 88 printk(" available.\n"); 89 break; 90 case CPU_TX3927: 91 cpu_wait = r39xx_wait; 92 printk(" available.\n"); 93 break; 94 case CPU_R4200: 95 /* case CPU_R4300: */ 96 case CPU_R4600: 97 case CPU_R4640: 98 case CPU_R4650: 99 case CPU_R4700: 100 case CPU_R5000: 101 case CPU_NEVADA: 102 case CPU_RM7000: 103 case CPU_RM9000: 104 case CPU_TX49XX: 105 case CPU_4KC: 106 case CPU_4KEC: 107 case CPU_4KSC: 108 case CPU_5KC: 109 /* case CPU_20KC:*/ 110 case CPU_24K: 111 case CPU_25KF: 112 cpu_wait = r4k_wait; 113 printk(" available.\n"); 114 break; 115 #ifdef CONFIG_PM 116 case CPU_AU1000: 117 case CPU_AU1100: 118 case CPU_AU1500: 119 if (au1k_wait_ptr != NULL) { 120 cpu_wait = au1k_wait_ptr; 121 printk(" available.\n"); 122 } 123 else { 124 printk(" unavailable.\n"); 125 } 126 break; 127 #endif 128 default: 129 printk(" unavailable.\n"); 130 break; 131 } 132 } 133 134 void __init check_bugs32(void) 135 { 136 check_wait(); 137 } 138 139 /* 140 * Probe whether cpu has config register by trying to play with 141 * alternate cache bit and see whether it matters. 142 * It's used by cpu_probe to distinguish between R3000A and R3081. 143 */ 144 static inline int cpu_has_confreg(void) 145 { 146 #ifdef CONFIG_CPU_R3000 147 extern unsigned long r3k_cache_size(unsigned long); 148 unsigned long size1, size2; 149 unsigned long cfg = read_c0_conf(); 150 151 size1 = r3k_cache_size(ST0_ISC); 152 write_c0_conf(cfg ^ R30XX_CONF_AC); 153 size2 = r3k_cache_size(ST0_ISC); 154 write_c0_conf(cfg); 155 return size1 != size2; 156 #else 157 return 0; 158 #endif 159 } 160 161 /* 162 * Get the FPU Implementation/Revision. 163 */ 164 static inline unsigned long cpu_get_fpu_id(void) 165 { 166 unsigned long tmp, fpu_id; 167 168 tmp = read_c0_status(); 169 __enable_fpu(); 170 fpu_id = read_32bit_cp1_register(CP1_REVISION); 171 write_c0_status(tmp); 172 return fpu_id; 173 } 174 175 /* 176 * Check the CPU has an FPU the official way. 177 */ 178 static inline int __cpu_has_fpu(void) 179 { 180 return ((cpu_get_fpu_id() & 0xff00) != FPIR_IMP_NONE); 181 } 182 183 #define R4K_OPTS (MIPS_CPU_TLB | MIPS_CPU_4KEX | MIPS_CPU_4KTLB \ 184 | MIPS_CPU_COUNTER) 185 186 static inline void cpu_probe_legacy(struct cpuinfo_mips *c) 187 { 188 switch (c->processor_id & 0xff00) { 189 case PRID_IMP_R2000: 190 c->cputype = CPU_R2000; 191 c->isa_level = MIPS_CPU_ISA_I; 192 c->options = MIPS_CPU_TLB | MIPS_CPU_NOFPUEX; 193 if (__cpu_has_fpu()) 194 c->options |= MIPS_CPU_FPU; 195 c->tlbsize = 64; 196 break; 197 case PRID_IMP_R3000: 198 if ((c->processor_id & 0xff) == PRID_REV_R3000A) 199 if (cpu_has_confreg()) 200 c->cputype = CPU_R3081E; 201 else 202 c->cputype = CPU_R3000A; 203 else 204 c->cputype = CPU_R3000; 205 c->isa_level = MIPS_CPU_ISA_I; 206 c->options = MIPS_CPU_TLB | MIPS_CPU_NOFPUEX; 207 if (__cpu_has_fpu()) 208 c->options |= MIPS_CPU_FPU; 209 c->tlbsize = 64; 210 break; 211 case PRID_IMP_R4000: 212 if (read_c0_config() & CONF_SC) { 213 if ((c->processor_id & 0xff) >= PRID_REV_R4400) 214 c->cputype = CPU_R4400PC; 215 else 216 c->cputype = CPU_R4000PC; 217 } else { 218 if ((c->processor_id & 0xff) >= PRID_REV_R4400) 219 c->cputype = CPU_R4400SC; 220 else 221 c->cputype = CPU_R4000SC; 222 } 223 224 c->isa_level = MIPS_CPU_ISA_III; 225 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR | 226 MIPS_CPU_WATCH | MIPS_CPU_VCE | 227 MIPS_CPU_LLSC; 228 c->tlbsize = 48; 229 break; 230 case PRID_IMP_VR41XX: 231 switch (c->processor_id & 0xf0) { 232 case PRID_REV_VR4111: 233 c->cputype = CPU_VR4111; 234 break; 235 case PRID_REV_VR4121: 236 c->cputype = CPU_VR4121; 237 break; 238 case PRID_REV_VR4122: 239 if ((c->processor_id & 0xf) < 0x3) 240 c->cputype = CPU_VR4122; 241 else 242 c->cputype = CPU_VR4181A; 243 break; 244 case PRID_REV_VR4130: 245 if ((c->processor_id & 0xf) < 0x4) 246 c->cputype = CPU_VR4131; 247 else 248 c->cputype = CPU_VR4133; 249 break; 250 default: 251 printk(KERN_INFO "Unexpected CPU of NEC VR4100 series\n"); 252 c->cputype = CPU_VR41XX; 253 break; 254 } 255 c->isa_level = MIPS_CPU_ISA_III; 256 c->options = R4K_OPTS; 257 c->tlbsize = 32; 258 break; 259 case PRID_IMP_R4300: 260 c->cputype = CPU_R4300; 261 c->isa_level = MIPS_CPU_ISA_III; 262 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR | 263 MIPS_CPU_LLSC; 264 c->tlbsize = 32; 265 break; 266 case PRID_IMP_R4600: 267 c->cputype = CPU_R4600; 268 c->isa_level = MIPS_CPU_ISA_III; 269 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_LLSC; 270 c->tlbsize = 48; 271 break; 272 #if 0 273 case PRID_IMP_R4650: 274 /* 275 * This processor doesn't have an MMU, so it's not 276 * "real easy" to run Linux on it. It is left purely 277 * for documentation. Commented out because it shares 278 * it's c0_prid id number with the TX3900. 279 */ 280 c->cputype = CPU_R4650; 281 c->isa_level = MIPS_CPU_ISA_III; 282 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_LLSC; 283 c->tlbsize = 48; 284 break; 285 #endif 286 case PRID_IMP_TX39: 287 c->isa_level = MIPS_CPU_ISA_I; 288 c->options = MIPS_CPU_TLB; 289 290 if ((c->processor_id & 0xf0) == (PRID_REV_TX3927 & 0xf0)) { 291 c->cputype = CPU_TX3927; 292 c->tlbsize = 64; 293 } else { 294 switch (c->processor_id & 0xff) { 295 case PRID_REV_TX3912: 296 c->cputype = CPU_TX3912; 297 c->tlbsize = 32; 298 break; 299 case PRID_REV_TX3922: 300 c->cputype = CPU_TX3922; 301 c->tlbsize = 64; 302 break; 303 default: 304 c->cputype = CPU_UNKNOWN; 305 break; 306 } 307 } 308 break; 309 case PRID_IMP_R4700: 310 c->cputype = CPU_R4700; 311 c->isa_level = MIPS_CPU_ISA_III; 312 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR | 313 MIPS_CPU_LLSC; 314 c->tlbsize = 48; 315 break; 316 case PRID_IMP_TX49: 317 c->cputype = CPU_TX49XX; 318 c->isa_level = MIPS_CPU_ISA_III; 319 c->options = R4K_OPTS | MIPS_CPU_LLSC; 320 if (!(c->processor_id & 0x08)) 321 c->options |= MIPS_CPU_FPU | MIPS_CPU_32FPR; 322 c->tlbsize = 48; 323 break; 324 case PRID_IMP_R5000: 325 c->cputype = CPU_R5000; 326 c->isa_level = MIPS_CPU_ISA_IV; 327 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR | 328 MIPS_CPU_LLSC; 329 c->tlbsize = 48; 330 break; 331 case PRID_IMP_R5432: 332 c->cputype = CPU_R5432; 333 c->isa_level = MIPS_CPU_ISA_IV; 334 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR | 335 MIPS_CPU_WATCH | MIPS_CPU_LLSC; 336 c->tlbsize = 48; 337 break; 338 case PRID_IMP_R5500: 339 c->cputype = CPU_R5500; 340 c->isa_level = MIPS_CPU_ISA_IV; 341 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR | 342 MIPS_CPU_WATCH | MIPS_CPU_LLSC; 343 c->tlbsize = 48; 344 break; 345 case PRID_IMP_NEVADA: 346 c->cputype = CPU_NEVADA; 347 c->isa_level = MIPS_CPU_ISA_IV; 348 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR | 349 MIPS_CPU_DIVEC | MIPS_CPU_LLSC; 350 c->tlbsize = 48; 351 break; 352 case PRID_IMP_R6000: 353 c->cputype = CPU_R6000; 354 c->isa_level = MIPS_CPU_ISA_II; 355 c->options = MIPS_CPU_TLB | MIPS_CPU_FPU | 356 MIPS_CPU_LLSC; 357 c->tlbsize = 32; 358 break; 359 case PRID_IMP_R6000A: 360 c->cputype = CPU_R6000A; 361 c->isa_level = MIPS_CPU_ISA_II; 362 c->options = MIPS_CPU_TLB | MIPS_CPU_FPU | 363 MIPS_CPU_LLSC; 364 c->tlbsize = 32; 365 break; 366 case PRID_IMP_RM7000: 367 c->cputype = CPU_RM7000; 368 c->isa_level = MIPS_CPU_ISA_IV; 369 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR | 370 MIPS_CPU_LLSC; 371 /* 372 * Undocumented RM7000: Bit 29 in the info register of 373 * the RM7000 v2.0 indicates if the TLB has 48 or 64 374 * entries. 375 * 376 * 29 1 => 64 entry JTLB 377 * 0 => 48 entry JTLB 378 */ 379 c->tlbsize = (read_c0_info() & (1 << 29)) ? 64 : 48; 380 break; 381 case PRID_IMP_RM9000: 382 c->cputype = CPU_RM9000; 383 c->isa_level = MIPS_CPU_ISA_IV; 384 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR | 385 MIPS_CPU_LLSC; 386 /* 387 * Bit 29 in the info register of the RM9000 388 * indicates if the TLB has 48 or 64 entries. 389 * 390 * 29 1 => 64 entry JTLB 391 * 0 => 48 entry JTLB 392 */ 393 c->tlbsize = (read_c0_info() & (1 << 29)) ? 64 : 48; 394 break; 395 case PRID_IMP_R8000: 396 c->cputype = CPU_R8000; 397 c->isa_level = MIPS_CPU_ISA_IV; 398 c->options = MIPS_CPU_TLB | MIPS_CPU_4KEX | 399 MIPS_CPU_FPU | MIPS_CPU_32FPR | 400 MIPS_CPU_LLSC; 401 c->tlbsize = 384; /* has weird TLB: 3-way x 128 */ 402 break; 403 case PRID_IMP_R10000: 404 c->cputype = CPU_R10000; 405 c->isa_level = MIPS_CPU_ISA_IV; 406 c->options = MIPS_CPU_TLB | MIPS_CPU_4KEX | 407 MIPS_CPU_FPU | MIPS_CPU_32FPR | 408 MIPS_CPU_COUNTER | MIPS_CPU_WATCH | 409 MIPS_CPU_LLSC; 410 c->tlbsize = 64; 411 break; 412 case PRID_IMP_R12000: 413 c->cputype = CPU_R12000; 414 c->isa_level = MIPS_CPU_ISA_IV; 415 c->options = MIPS_CPU_TLB | MIPS_CPU_4KEX | 416 MIPS_CPU_FPU | MIPS_CPU_32FPR | 417 MIPS_CPU_COUNTER | MIPS_CPU_WATCH | 418 MIPS_CPU_LLSC; 419 c->tlbsize = 64; 420 break; 421 } 422 } 423 424 static inline void decode_config1(struct cpuinfo_mips *c) 425 { 426 unsigned long config0 = read_c0_config(); 427 unsigned long config1; 428 429 if ((config0 & (1 << 31)) == 0) 430 return; /* actually wort a panic() */ 431 432 /* MIPS32 or MIPS64 compliant CPU. Read Config 1 register. */ 433 c->options = MIPS_CPU_TLB | MIPS_CPU_4KEX | 434 MIPS_CPU_4KTLB | MIPS_CPU_COUNTER | MIPS_CPU_DIVEC | 435 MIPS_CPU_LLSC | MIPS_CPU_MCHECK; 436 config1 = read_c0_config1(); 437 if (config1 & (1 << 3)) 438 c->options |= MIPS_CPU_WATCH; 439 if (config1 & (1 << 2)) 440 c->options |= MIPS_CPU_MIPS16; 441 if (config1 & (1 << 1)) 442 c->options |= MIPS_CPU_EJTAG; 443 if (config1 & 1) { 444 c->options |= MIPS_CPU_FPU; 445 c->options |= MIPS_CPU_32FPR; 446 } 447 c->scache.flags = MIPS_CACHE_NOT_PRESENT; 448 449 c->tlbsize = ((config1 >> 25) & 0x3f) + 1; 450 } 451 452 static inline void cpu_probe_mips(struct cpuinfo_mips *c) 453 { 454 decode_config1(c); 455 switch (c->processor_id & 0xff00) { 456 case PRID_IMP_4KC: 457 c->cputype = CPU_4KC; 458 c->isa_level = MIPS_CPU_ISA_M32; 459 break; 460 case PRID_IMP_4KEC: 461 c->cputype = CPU_4KEC; 462 c->isa_level = MIPS_CPU_ISA_M32; 463 break; 464 case PRID_IMP_4KSC: 465 c->cputype = CPU_4KSC; 466 c->isa_level = MIPS_CPU_ISA_M32; 467 break; 468 case PRID_IMP_5KC: 469 c->cputype = CPU_5KC; 470 c->isa_level = MIPS_CPU_ISA_M64; 471 break; 472 case PRID_IMP_20KC: 473 c->cputype = CPU_20KC; 474 c->isa_level = MIPS_CPU_ISA_M64; 475 break; 476 case PRID_IMP_24K: 477 c->cputype = CPU_24K; 478 c->isa_level = MIPS_CPU_ISA_M32; 479 break; 480 case PRID_IMP_25KF: 481 c->cputype = CPU_25KF; 482 c->isa_level = MIPS_CPU_ISA_M64; 483 /* Probe for L2 cache */ 484 c->scache.flags &= ~MIPS_CACHE_NOT_PRESENT; 485 break; 486 } 487 } 488 489 static inline void cpu_probe_alchemy(struct cpuinfo_mips *c) 490 { 491 decode_config1(c); 492 switch (c->processor_id & 0xff00) { 493 case PRID_IMP_AU1_REV1: 494 case PRID_IMP_AU1_REV2: 495 switch ((c->processor_id >> 24) & 0xff) { 496 case 0: 497 c->cputype = CPU_AU1000; 498 break; 499 case 1: 500 c->cputype = CPU_AU1500; 501 break; 502 case 2: 503 c->cputype = CPU_AU1100; 504 break; 505 case 3: 506 c->cputype = CPU_AU1550; 507 break; 508 default: 509 panic("Unknown Au Core!"); 510 break; 511 } 512 c->isa_level = MIPS_CPU_ISA_M32; 513 break; 514 } 515 } 516 517 static inline void cpu_probe_sibyte(struct cpuinfo_mips *c) 518 { 519 decode_config1(c); 520 switch (c->processor_id & 0xff00) { 521 case PRID_IMP_SB1: 522 c->cputype = CPU_SB1; 523 c->isa_level = MIPS_CPU_ISA_M64; 524 c->options = MIPS_CPU_TLB | MIPS_CPU_4KEX | 525 MIPS_CPU_COUNTER | MIPS_CPU_DIVEC | 526 MIPS_CPU_MCHECK | MIPS_CPU_EJTAG | 527 MIPS_CPU_WATCH | MIPS_CPU_LLSC; 528 #ifndef CONFIG_SB1_PASS_1_WORKAROUNDS 529 /* FPU in pass1 is known to have issues. */ 530 c->options |= MIPS_CPU_FPU | MIPS_CPU_32FPR; 531 #endif 532 break; 533 } 534 } 535 536 static inline void cpu_probe_sandcraft(struct cpuinfo_mips *c) 537 { 538 decode_config1(c); 539 switch (c->processor_id & 0xff00) { 540 case PRID_IMP_SR71000: 541 c->cputype = CPU_SR71000; 542 c->isa_level = MIPS_CPU_ISA_M64; 543 c->options = MIPS_CPU_TLB | MIPS_CPU_4KEX | 544 MIPS_CPU_4KTLB | MIPS_CPU_FPU | 545 MIPS_CPU_COUNTER | MIPS_CPU_MCHECK; 546 c->scache.ways = 8; 547 c->tlbsize = 64; 548 break; 549 } 550 } 551 552 __init void cpu_probe(void) 553 { 554 struct cpuinfo_mips *c = ¤t_cpu_data; 555 556 c->processor_id = PRID_IMP_UNKNOWN; 557 c->fpu_id = FPIR_IMP_NONE; 558 c->cputype = CPU_UNKNOWN; 559 560 c->processor_id = read_c0_prid(); 561 switch (c->processor_id & 0xff0000) { 562 case PRID_COMP_LEGACY: 563 cpu_probe_legacy(c); 564 break; 565 case PRID_COMP_MIPS: 566 cpu_probe_mips(c); 567 break; 568 case PRID_COMP_ALCHEMY: 569 cpu_probe_alchemy(c); 570 break; 571 case PRID_COMP_SIBYTE: 572 cpu_probe_sibyte(c); 573 break; 574 575 case PRID_COMP_SANDCRAFT: 576 cpu_probe_sandcraft(c); 577 break; 578 default: 579 c->cputype = CPU_UNKNOWN; 580 } 581 if (c->options & MIPS_CPU_FPU) 582 c->fpu_id = cpu_get_fpu_id(); 583 } 584 585 __init void cpu_report(void) 586 { 587 struct cpuinfo_mips *c = ¤t_cpu_data; 588 589 printk("CPU revision is: %08x\n", c->processor_id); 590 if (c->options & MIPS_CPU_FPU) 591 printk("FPU revision is: %08x\n", c->fpu_id); 592 } 593