1 /* 2 * Processor capabilities determination functions. 3 * 4 * Copyright (C) xxxx the Anonymous 5 * Copyright (C) 1994 - 2006 Ralf Baechle 6 * Copyright (C) 2003, 2004 Maciej W. Rozycki 7 * Copyright (C) 2001, 2004, 2011, 2012 MIPS Technologies, Inc. 8 * 9 * This program is free software; you can redistribute it and/or 10 * modify it under the terms of the GNU General Public License 11 * as published by the Free Software Foundation; either version 12 * 2 of the License, or (at your option) any later version. 13 */ 14 #include <linux/init.h> 15 #include <linux/kernel.h> 16 #include <linux/ptrace.h> 17 #include <linux/smp.h> 18 #include <linux/stddef.h> 19 #include <linux/export.h> 20 21 #include <asm/bugs.h> 22 #include <asm/cpu.h> 23 #include <asm/fpu.h> 24 #include <asm/mipsregs.h> 25 #include <asm/watch.h> 26 #include <asm/elf.h> 27 #include <asm/spram.h> 28 #include <asm/uaccess.h> 29 30 /* 31 * Not all of the MIPS CPUs have the "wait" instruction available. Moreover, 32 * the implementation of the "wait" feature differs between CPU families. This 33 * points to the function that implements CPU specific wait. 34 * The wait instruction stops the pipeline and reduces the power consumption of 35 * the CPU very much. 36 */ 37 void (*cpu_wait)(void); 38 EXPORT_SYMBOL(cpu_wait); 39 40 static void r3081_wait(void) 41 { 42 unsigned long cfg = read_c0_conf(); 43 write_c0_conf(cfg | R30XX_CONF_HALT); 44 } 45 46 static void r39xx_wait(void) 47 { 48 local_irq_disable(); 49 if (!need_resched()) 50 write_c0_conf(read_c0_conf() | TX39_CONF_HALT); 51 local_irq_enable(); 52 } 53 54 extern void r4k_wait(void); 55 56 /* 57 * This variant is preferable as it allows testing need_resched and going to 58 * sleep depending on the outcome atomically. Unfortunately the "It is 59 * implementation-dependent whether the pipeline restarts when a non-enabled 60 * interrupt is requested" restriction in the MIPS32/MIPS64 architecture makes 61 * using this version a gamble. 62 */ 63 void r4k_wait_irqoff(void) 64 { 65 local_irq_disable(); 66 if (!need_resched()) 67 __asm__(" .set push \n" 68 " .set mips3 \n" 69 " wait \n" 70 " .set pop \n"); 71 local_irq_enable(); 72 __asm__(" .globl __pastwait \n" 73 "__pastwait: \n"); 74 } 75 76 /* 77 * The RM7000 variant has to handle erratum 38. The workaround is to not 78 * have any pending stores when the WAIT instruction is executed. 79 */ 80 static void rm7k_wait_irqoff(void) 81 { 82 local_irq_disable(); 83 if (!need_resched()) 84 __asm__( 85 " .set push \n" 86 " .set mips3 \n" 87 " .set noat \n" 88 " mfc0 $1, $12 \n" 89 " sync \n" 90 " mtc0 $1, $12 # stalls until W stage \n" 91 " wait \n" 92 " mtc0 $1, $12 # stalls until W stage \n" 93 " .set pop \n"); 94 local_irq_enable(); 95 } 96 97 /* 98 * The Au1xxx wait is available only if using 32khz counter or 99 * external timer source, but specifically not CP0 Counter. 100 * alchemy/common/time.c may override cpu_wait! 101 */ 102 static void au1k_wait(void) 103 { 104 __asm__(" .set mips3 \n" 105 " cache 0x14, 0(%0) \n" 106 " cache 0x14, 32(%0) \n" 107 " sync \n" 108 " nop \n" 109 " wait \n" 110 " nop \n" 111 " nop \n" 112 " nop \n" 113 " nop \n" 114 " .set mips0 \n" 115 : : "r" (au1k_wait)); 116 } 117 118 static int __initdata nowait; 119 120 static int __init wait_disable(char *s) 121 { 122 nowait = 1; 123 124 return 1; 125 } 126 127 __setup("nowait", wait_disable); 128 129 static int __cpuinitdata mips_fpu_disabled; 130 131 static int __init fpu_disable(char *s) 132 { 133 cpu_data[0].options &= ~MIPS_CPU_FPU; 134 mips_fpu_disabled = 1; 135 136 return 1; 137 } 138 139 __setup("nofpu", fpu_disable); 140 141 int __cpuinitdata mips_dsp_disabled; 142 143 static int __init dsp_disable(char *s) 144 { 145 cpu_data[0].ases &= ~(MIPS_ASE_DSP | MIPS_ASE_DSP2P); 146 mips_dsp_disabled = 1; 147 148 return 1; 149 } 150 151 __setup("nodsp", dsp_disable); 152 153 void __init check_wait(void) 154 { 155 struct cpuinfo_mips *c = ¤t_cpu_data; 156 157 if (nowait) { 158 printk("Wait instruction disabled.\n"); 159 return; 160 } 161 162 switch (c->cputype) { 163 case CPU_R3081: 164 case CPU_R3081E: 165 cpu_wait = r3081_wait; 166 break; 167 case CPU_TX3927: 168 cpu_wait = r39xx_wait; 169 break; 170 case CPU_R4200: 171 /* case CPU_R4300: */ 172 case CPU_R4600: 173 case CPU_R4640: 174 case CPU_R4650: 175 case CPU_R4700: 176 case CPU_R5000: 177 case CPU_R5500: 178 case CPU_NEVADA: 179 case CPU_4KC: 180 case CPU_4KEC: 181 case CPU_4KSC: 182 case CPU_5KC: 183 case CPU_25KF: 184 case CPU_PR4450: 185 case CPU_BMIPS3300: 186 case CPU_BMIPS4350: 187 case CPU_BMIPS4380: 188 case CPU_BMIPS5000: 189 case CPU_CAVIUM_OCTEON: 190 case CPU_CAVIUM_OCTEON_PLUS: 191 case CPU_CAVIUM_OCTEON2: 192 case CPU_JZRISC: 193 case CPU_LOONGSON1: 194 case CPU_XLR: 195 case CPU_XLP: 196 cpu_wait = r4k_wait; 197 break; 198 199 case CPU_RM7000: 200 cpu_wait = rm7k_wait_irqoff; 201 break; 202 203 case CPU_M14KC: 204 case CPU_24K: 205 case CPU_34K: 206 case CPU_1004K: 207 cpu_wait = r4k_wait; 208 if (read_c0_config7() & MIPS_CONF7_WII) 209 cpu_wait = r4k_wait_irqoff; 210 break; 211 212 case CPU_74K: 213 cpu_wait = r4k_wait; 214 if ((c->processor_id & 0xff) >= PRID_REV_ENCODE_332(2, 1, 0)) 215 cpu_wait = r4k_wait_irqoff; 216 break; 217 218 case CPU_TX49XX: 219 cpu_wait = r4k_wait_irqoff; 220 break; 221 case CPU_ALCHEMY: 222 cpu_wait = au1k_wait; 223 break; 224 case CPU_20KC: 225 /* 226 * WAIT on Rev1.0 has E1, E2, E3 and E16. 227 * WAIT on Rev2.0 and Rev3.0 has E16. 228 * Rev3.1 WAIT is nop, why bother 229 */ 230 if ((c->processor_id & 0xff) <= 0x64) 231 break; 232 233 /* 234 * Another rev is incremeting c0_count at a reduced clock 235 * rate while in WAIT mode. So we basically have the choice 236 * between using the cp0 timer as clocksource or avoiding 237 * the WAIT instruction. Until more details are known, 238 * disable the use of WAIT for 20Kc entirely. 239 cpu_wait = r4k_wait; 240 */ 241 break; 242 case CPU_RM9000: 243 if ((c->processor_id & 0x00ff) >= 0x40) 244 cpu_wait = r4k_wait; 245 break; 246 default: 247 break; 248 } 249 } 250 251 static inline void check_errata(void) 252 { 253 struct cpuinfo_mips *c = ¤t_cpu_data; 254 255 switch (c->cputype) { 256 case CPU_34K: 257 /* 258 * Erratum "RPS May Cause Incorrect Instruction Execution" 259 * This code only handles VPE0, any SMP/SMTC/RTOS code 260 * making use of VPE1 will be responsable for that VPE. 261 */ 262 if ((c->processor_id & PRID_REV_MASK) <= PRID_REV_34K_V1_0_2) 263 write_c0_config7(read_c0_config7() | MIPS_CONF7_RPS); 264 break; 265 default: 266 break; 267 } 268 } 269 270 void __init check_bugs32(void) 271 { 272 check_errata(); 273 } 274 275 /* 276 * Probe whether cpu has config register by trying to play with 277 * alternate cache bit and see whether it matters. 278 * It's used by cpu_probe to distinguish between R3000A and R3081. 279 */ 280 static inline int cpu_has_confreg(void) 281 { 282 #ifdef CONFIG_CPU_R3000 283 extern unsigned long r3k_cache_size(unsigned long); 284 unsigned long size1, size2; 285 unsigned long cfg = read_c0_conf(); 286 287 size1 = r3k_cache_size(ST0_ISC); 288 write_c0_conf(cfg ^ R30XX_CONF_AC); 289 size2 = r3k_cache_size(ST0_ISC); 290 write_c0_conf(cfg); 291 return size1 != size2; 292 #else 293 return 0; 294 #endif 295 } 296 297 static inline void set_elf_platform(int cpu, const char *plat) 298 { 299 if (cpu == 0) 300 __elf_platform = plat; 301 } 302 303 /* 304 * Get the FPU Implementation/Revision. 305 */ 306 static inline unsigned long cpu_get_fpu_id(void) 307 { 308 unsigned long tmp, fpu_id; 309 310 tmp = read_c0_status(); 311 __enable_fpu(); 312 fpu_id = read_32bit_cp1_register(CP1_REVISION); 313 write_c0_status(tmp); 314 return fpu_id; 315 } 316 317 /* 318 * Check the CPU has an FPU the official way. 319 */ 320 static inline int __cpu_has_fpu(void) 321 { 322 return ((cpu_get_fpu_id() & 0xff00) != FPIR_IMP_NONE); 323 } 324 325 static inline void cpu_probe_vmbits(struct cpuinfo_mips *c) 326 { 327 #ifdef __NEED_VMBITS_PROBE 328 write_c0_entryhi(0x3fffffffffffe000ULL); 329 back_to_back_c0_hazard(); 330 c->vmbits = fls64(read_c0_entryhi() & 0x3fffffffffffe000ULL); 331 #endif 332 } 333 334 static char unknown_isa[] __cpuinitdata = KERN_ERR \ 335 "Unsupported ISA type, c0.config0: %d."; 336 337 static inline unsigned int decode_config0(struct cpuinfo_mips *c) 338 { 339 unsigned int config0; 340 int isa; 341 342 config0 = read_c0_config(); 343 344 if (((config0 & MIPS_CONF_MT) >> 7) == 1) 345 c->options |= MIPS_CPU_TLB; 346 isa = (config0 & MIPS_CONF_AT) >> 13; 347 switch (isa) { 348 case 0: 349 switch ((config0 & MIPS_CONF_AR) >> 10) { 350 case 0: 351 c->isa_level = MIPS_CPU_ISA_M32R1; 352 break; 353 case 1: 354 c->isa_level = MIPS_CPU_ISA_M32R2; 355 break; 356 default: 357 goto unknown; 358 } 359 break; 360 case 2: 361 switch ((config0 & MIPS_CONF_AR) >> 10) { 362 case 0: 363 c->isa_level = MIPS_CPU_ISA_M64R1; 364 break; 365 case 1: 366 c->isa_level = MIPS_CPU_ISA_M64R2; 367 break; 368 default: 369 goto unknown; 370 } 371 break; 372 default: 373 goto unknown; 374 } 375 376 return config0 & MIPS_CONF_M; 377 378 unknown: 379 panic(unknown_isa, config0); 380 } 381 382 static inline unsigned int decode_config1(struct cpuinfo_mips *c) 383 { 384 unsigned int config1; 385 386 config1 = read_c0_config1(); 387 388 if (config1 & MIPS_CONF1_MD) 389 c->ases |= MIPS_ASE_MDMX; 390 if (config1 & MIPS_CONF1_WR) 391 c->options |= MIPS_CPU_WATCH; 392 if (config1 & MIPS_CONF1_CA) 393 c->ases |= MIPS_ASE_MIPS16; 394 if (config1 & MIPS_CONF1_EP) 395 c->options |= MIPS_CPU_EJTAG; 396 if (config1 & MIPS_CONF1_FP) { 397 c->options |= MIPS_CPU_FPU; 398 c->options |= MIPS_CPU_32FPR; 399 } 400 if (cpu_has_tlb) 401 c->tlbsize = ((config1 & MIPS_CONF1_TLBS) >> 25) + 1; 402 403 return config1 & MIPS_CONF_M; 404 } 405 406 static inline unsigned int decode_config2(struct cpuinfo_mips *c) 407 { 408 unsigned int config2; 409 410 config2 = read_c0_config2(); 411 412 if (config2 & MIPS_CONF2_SL) 413 c->scache.flags &= ~MIPS_CACHE_NOT_PRESENT; 414 415 return config2 & MIPS_CONF_M; 416 } 417 418 static inline unsigned int decode_config3(struct cpuinfo_mips *c) 419 { 420 unsigned int config3; 421 422 config3 = read_c0_config3(); 423 424 if (config3 & MIPS_CONF3_SM) { 425 c->ases |= MIPS_ASE_SMARTMIPS; 426 c->options |= MIPS_CPU_RIXI; 427 } 428 if (config3 & MIPS_CONF3_RXI) 429 c->options |= MIPS_CPU_RIXI; 430 if (config3 & MIPS_CONF3_DSP) 431 c->ases |= MIPS_ASE_DSP; 432 if (config3 & MIPS_CONF3_DSP2P) 433 c->ases |= MIPS_ASE_DSP2P; 434 if (config3 & MIPS_CONF3_VINT) 435 c->options |= MIPS_CPU_VINT; 436 if (config3 & MIPS_CONF3_VEIC) 437 c->options |= MIPS_CPU_VEIC; 438 if (config3 & MIPS_CONF3_MT) 439 c->ases |= MIPS_ASE_MIPSMT; 440 if (config3 & MIPS_CONF3_ULRI) 441 c->options |= MIPS_CPU_ULRI; 442 443 return config3 & MIPS_CONF_M; 444 } 445 446 static inline unsigned int decode_config4(struct cpuinfo_mips *c) 447 { 448 unsigned int config4; 449 450 config4 = read_c0_config4(); 451 452 if ((config4 & MIPS_CONF4_MMUEXTDEF) == MIPS_CONF4_MMUEXTDEF_MMUSIZEEXT 453 && cpu_has_tlb) 454 c->tlbsize += (config4 & MIPS_CONF4_MMUSIZEEXT) * 0x40; 455 456 c->kscratch_mask = (config4 >> 16) & 0xff; 457 458 return config4 & MIPS_CONF_M; 459 } 460 461 static void __cpuinit decode_configs(struct cpuinfo_mips *c) 462 { 463 int ok; 464 465 /* MIPS32 or MIPS64 compliant CPU. */ 466 c->options = MIPS_CPU_4KEX | MIPS_CPU_4K_CACHE | MIPS_CPU_COUNTER | 467 MIPS_CPU_DIVEC | MIPS_CPU_LLSC | MIPS_CPU_MCHECK; 468 469 c->scache.flags = MIPS_CACHE_NOT_PRESENT; 470 471 ok = decode_config0(c); /* Read Config registers. */ 472 BUG_ON(!ok); /* Arch spec violation! */ 473 if (ok) 474 ok = decode_config1(c); 475 if (ok) 476 ok = decode_config2(c); 477 if (ok) 478 ok = decode_config3(c); 479 if (ok) 480 ok = decode_config4(c); 481 482 mips_probe_watch_registers(c); 483 484 if (cpu_has_mips_r2) 485 c->core = read_c0_ebase() & 0x3ff; 486 } 487 488 #define R4K_OPTS (MIPS_CPU_TLB | MIPS_CPU_4KEX | MIPS_CPU_4K_CACHE \ 489 | MIPS_CPU_COUNTER) 490 491 static inline void cpu_probe_legacy(struct cpuinfo_mips *c, unsigned int cpu) 492 { 493 switch (c->processor_id & 0xff00) { 494 case PRID_IMP_R2000: 495 c->cputype = CPU_R2000; 496 __cpu_name[cpu] = "R2000"; 497 c->isa_level = MIPS_CPU_ISA_I; 498 c->options = MIPS_CPU_TLB | MIPS_CPU_3K_CACHE | 499 MIPS_CPU_NOFPUEX; 500 if (__cpu_has_fpu()) 501 c->options |= MIPS_CPU_FPU; 502 c->tlbsize = 64; 503 break; 504 case PRID_IMP_R3000: 505 if ((c->processor_id & 0xff) == PRID_REV_R3000A) { 506 if (cpu_has_confreg()) { 507 c->cputype = CPU_R3081E; 508 __cpu_name[cpu] = "R3081"; 509 } else { 510 c->cputype = CPU_R3000A; 511 __cpu_name[cpu] = "R3000A"; 512 } 513 } else { 514 c->cputype = CPU_R3000; 515 __cpu_name[cpu] = "R3000"; 516 } 517 c->isa_level = MIPS_CPU_ISA_I; 518 c->options = MIPS_CPU_TLB | MIPS_CPU_3K_CACHE | 519 MIPS_CPU_NOFPUEX; 520 if (__cpu_has_fpu()) 521 c->options |= MIPS_CPU_FPU; 522 c->tlbsize = 64; 523 break; 524 case PRID_IMP_R4000: 525 if (read_c0_config() & CONF_SC) { 526 if ((c->processor_id & 0xff) >= PRID_REV_R4400) { 527 c->cputype = CPU_R4400PC; 528 __cpu_name[cpu] = "R4400PC"; 529 } else { 530 c->cputype = CPU_R4000PC; 531 __cpu_name[cpu] = "R4000PC"; 532 } 533 } else { 534 if ((c->processor_id & 0xff) >= PRID_REV_R4400) { 535 c->cputype = CPU_R4400SC; 536 __cpu_name[cpu] = "R4400SC"; 537 } else { 538 c->cputype = CPU_R4000SC; 539 __cpu_name[cpu] = "R4000SC"; 540 } 541 } 542 543 c->isa_level = MIPS_CPU_ISA_III; 544 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR | 545 MIPS_CPU_WATCH | MIPS_CPU_VCE | 546 MIPS_CPU_LLSC; 547 c->tlbsize = 48; 548 break; 549 case PRID_IMP_VR41XX: 550 switch (c->processor_id & 0xf0) { 551 case PRID_REV_VR4111: 552 c->cputype = CPU_VR4111; 553 __cpu_name[cpu] = "NEC VR4111"; 554 break; 555 case PRID_REV_VR4121: 556 c->cputype = CPU_VR4121; 557 __cpu_name[cpu] = "NEC VR4121"; 558 break; 559 case PRID_REV_VR4122: 560 if ((c->processor_id & 0xf) < 0x3) { 561 c->cputype = CPU_VR4122; 562 __cpu_name[cpu] = "NEC VR4122"; 563 } else { 564 c->cputype = CPU_VR4181A; 565 __cpu_name[cpu] = "NEC VR4181A"; 566 } 567 break; 568 case PRID_REV_VR4130: 569 if ((c->processor_id & 0xf) < 0x4) { 570 c->cputype = CPU_VR4131; 571 __cpu_name[cpu] = "NEC VR4131"; 572 } else { 573 c->cputype = CPU_VR4133; 574 __cpu_name[cpu] = "NEC VR4133"; 575 } 576 break; 577 default: 578 printk(KERN_INFO "Unexpected CPU of NEC VR4100 series\n"); 579 c->cputype = CPU_VR41XX; 580 __cpu_name[cpu] = "NEC Vr41xx"; 581 break; 582 } 583 c->isa_level = MIPS_CPU_ISA_III; 584 c->options = R4K_OPTS; 585 c->tlbsize = 32; 586 break; 587 case PRID_IMP_R4300: 588 c->cputype = CPU_R4300; 589 __cpu_name[cpu] = "R4300"; 590 c->isa_level = MIPS_CPU_ISA_III; 591 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR | 592 MIPS_CPU_LLSC; 593 c->tlbsize = 32; 594 break; 595 case PRID_IMP_R4600: 596 c->cputype = CPU_R4600; 597 __cpu_name[cpu] = "R4600"; 598 c->isa_level = MIPS_CPU_ISA_III; 599 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR | 600 MIPS_CPU_LLSC; 601 c->tlbsize = 48; 602 break; 603 #if 0 604 case PRID_IMP_R4650: 605 /* 606 * This processor doesn't have an MMU, so it's not 607 * "real easy" to run Linux on it. It is left purely 608 * for documentation. Commented out because it shares 609 * it's c0_prid id number with the TX3900. 610 */ 611 c->cputype = CPU_R4650; 612 __cpu_name[cpu] = "R4650"; 613 c->isa_level = MIPS_CPU_ISA_III; 614 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_LLSC; 615 c->tlbsize = 48; 616 break; 617 #endif 618 case PRID_IMP_TX39: 619 c->isa_level = MIPS_CPU_ISA_I; 620 c->options = MIPS_CPU_TLB | MIPS_CPU_TX39_CACHE; 621 622 if ((c->processor_id & 0xf0) == (PRID_REV_TX3927 & 0xf0)) { 623 c->cputype = CPU_TX3927; 624 __cpu_name[cpu] = "TX3927"; 625 c->tlbsize = 64; 626 } else { 627 switch (c->processor_id & 0xff) { 628 case PRID_REV_TX3912: 629 c->cputype = CPU_TX3912; 630 __cpu_name[cpu] = "TX3912"; 631 c->tlbsize = 32; 632 break; 633 case PRID_REV_TX3922: 634 c->cputype = CPU_TX3922; 635 __cpu_name[cpu] = "TX3922"; 636 c->tlbsize = 64; 637 break; 638 } 639 } 640 break; 641 case PRID_IMP_R4700: 642 c->cputype = CPU_R4700; 643 __cpu_name[cpu] = "R4700"; 644 c->isa_level = MIPS_CPU_ISA_III; 645 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR | 646 MIPS_CPU_LLSC; 647 c->tlbsize = 48; 648 break; 649 case PRID_IMP_TX49: 650 c->cputype = CPU_TX49XX; 651 __cpu_name[cpu] = "R49XX"; 652 c->isa_level = MIPS_CPU_ISA_III; 653 c->options = R4K_OPTS | MIPS_CPU_LLSC; 654 if (!(c->processor_id & 0x08)) 655 c->options |= MIPS_CPU_FPU | MIPS_CPU_32FPR; 656 c->tlbsize = 48; 657 break; 658 case PRID_IMP_R5000: 659 c->cputype = CPU_R5000; 660 __cpu_name[cpu] = "R5000"; 661 c->isa_level = MIPS_CPU_ISA_IV; 662 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR | 663 MIPS_CPU_LLSC; 664 c->tlbsize = 48; 665 break; 666 case PRID_IMP_R5432: 667 c->cputype = CPU_R5432; 668 __cpu_name[cpu] = "R5432"; 669 c->isa_level = MIPS_CPU_ISA_IV; 670 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR | 671 MIPS_CPU_WATCH | MIPS_CPU_LLSC; 672 c->tlbsize = 48; 673 break; 674 case PRID_IMP_R5500: 675 c->cputype = CPU_R5500; 676 __cpu_name[cpu] = "R5500"; 677 c->isa_level = MIPS_CPU_ISA_IV; 678 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR | 679 MIPS_CPU_WATCH | MIPS_CPU_LLSC; 680 c->tlbsize = 48; 681 break; 682 case PRID_IMP_NEVADA: 683 c->cputype = CPU_NEVADA; 684 __cpu_name[cpu] = "Nevada"; 685 c->isa_level = MIPS_CPU_ISA_IV; 686 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR | 687 MIPS_CPU_DIVEC | MIPS_CPU_LLSC; 688 c->tlbsize = 48; 689 break; 690 case PRID_IMP_R6000: 691 c->cputype = CPU_R6000; 692 __cpu_name[cpu] = "R6000"; 693 c->isa_level = MIPS_CPU_ISA_II; 694 c->options = MIPS_CPU_TLB | MIPS_CPU_FPU | 695 MIPS_CPU_LLSC; 696 c->tlbsize = 32; 697 break; 698 case PRID_IMP_R6000A: 699 c->cputype = CPU_R6000A; 700 __cpu_name[cpu] = "R6000A"; 701 c->isa_level = MIPS_CPU_ISA_II; 702 c->options = MIPS_CPU_TLB | MIPS_CPU_FPU | 703 MIPS_CPU_LLSC; 704 c->tlbsize = 32; 705 break; 706 case PRID_IMP_RM7000: 707 c->cputype = CPU_RM7000; 708 __cpu_name[cpu] = "RM7000"; 709 c->isa_level = MIPS_CPU_ISA_IV; 710 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR | 711 MIPS_CPU_LLSC; 712 /* 713 * Undocumented RM7000: Bit 29 in the info register of 714 * the RM7000 v2.0 indicates if the TLB has 48 or 64 715 * entries. 716 * 717 * 29 1 => 64 entry JTLB 718 * 0 => 48 entry JTLB 719 */ 720 c->tlbsize = (read_c0_info() & (1 << 29)) ? 64 : 48; 721 break; 722 case PRID_IMP_RM9000: 723 c->cputype = CPU_RM9000; 724 __cpu_name[cpu] = "RM9000"; 725 c->isa_level = MIPS_CPU_ISA_IV; 726 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR | 727 MIPS_CPU_LLSC; 728 /* 729 * Bit 29 in the info register of the RM9000 730 * indicates if the TLB has 48 or 64 entries. 731 * 732 * 29 1 => 64 entry JTLB 733 * 0 => 48 entry JTLB 734 */ 735 c->tlbsize = (read_c0_info() & (1 << 29)) ? 64 : 48; 736 break; 737 case PRID_IMP_R8000: 738 c->cputype = CPU_R8000; 739 __cpu_name[cpu] = "RM8000"; 740 c->isa_level = MIPS_CPU_ISA_IV; 741 c->options = MIPS_CPU_TLB | MIPS_CPU_4KEX | 742 MIPS_CPU_FPU | MIPS_CPU_32FPR | 743 MIPS_CPU_LLSC; 744 c->tlbsize = 384; /* has weird TLB: 3-way x 128 */ 745 break; 746 case PRID_IMP_R10000: 747 c->cputype = CPU_R10000; 748 __cpu_name[cpu] = "R10000"; 749 c->isa_level = MIPS_CPU_ISA_IV; 750 c->options = MIPS_CPU_TLB | MIPS_CPU_4K_CACHE | MIPS_CPU_4KEX | 751 MIPS_CPU_FPU | MIPS_CPU_32FPR | 752 MIPS_CPU_COUNTER | MIPS_CPU_WATCH | 753 MIPS_CPU_LLSC; 754 c->tlbsize = 64; 755 break; 756 case PRID_IMP_R12000: 757 c->cputype = CPU_R12000; 758 __cpu_name[cpu] = "R12000"; 759 c->isa_level = MIPS_CPU_ISA_IV; 760 c->options = MIPS_CPU_TLB | MIPS_CPU_4K_CACHE | MIPS_CPU_4KEX | 761 MIPS_CPU_FPU | MIPS_CPU_32FPR | 762 MIPS_CPU_COUNTER | MIPS_CPU_WATCH | 763 MIPS_CPU_LLSC; 764 c->tlbsize = 64; 765 break; 766 case PRID_IMP_R14000: 767 c->cputype = CPU_R14000; 768 __cpu_name[cpu] = "R14000"; 769 c->isa_level = MIPS_CPU_ISA_IV; 770 c->options = MIPS_CPU_TLB | MIPS_CPU_4K_CACHE | MIPS_CPU_4KEX | 771 MIPS_CPU_FPU | MIPS_CPU_32FPR | 772 MIPS_CPU_COUNTER | MIPS_CPU_WATCH | 773 MIPS_CPU_LLSC; 774 c->tlbsize = 64; 775 break; 776 case PRID_IMP_LOONGSON2: 777 c->cputype = CPU_LOONGSON2; 778 __cpu_name[cpu] = "ICT Loongson-2"; 779 780 switch (c->processor_id & PRID_REV_MASK) { 781 case PRID_REV_LOONGSON2E: 782 set_elf_platform(cpu, "loongson2e"); 783 break; 784 case PRID_REV_LOONGSON2F: 785 set_elf_platform(cpu, "loongson2f"); 786 break; 787 } 788 789 c->isa_level = MIPS_CPU_ISA_III; 790 c->options = R4K_OPTS | 791 MIPS_CPU_FPU | MIPS_CPU_LLSC | 792 MIPS_CPU_32FPR; 793 c->tlbsize = 64; 794 break; 795 case PRID_IMP_LOONGSON1: 796 decode_configs(c); 797 798 c->cputype = CPU_LOONGSON1; 799 800 switch (c->processor_id & PRID_REV_MASK) { 801 case PRID_REV_LOONGSON1B: 802 __cpu_name[cpu] = "Loongson 1B"; 803 break; 804 } 805 806 break; 807 } 808 } 809 810 static inline void cpu_probe_mips(struct cpuinfo_mips *c, unsigned int cpu) 811 { 812 decode_configs(c); 813 switch (c->processor_id & 0xff00) { 814 case PRID_IMP_4KC: 815 c->cputype = CPU_4KC; 816 __cpu_name[cpu] = "MIPS 4Kc"; 817 break; 818 case PRID_IMP_4KEC: 819 case PRID_IMP_4KECR2: 820 c->cputype = CPU_4KEC; 821 __cpu_name[cpu] = "MIPS 4KEc"; 822 break; 823 case PRID_IMP_4KSC: 824 case PRID_IMP_4KSD: 825 c->cputype = CPU_4KSC; 826 __cpu_name[cpu] = "MIPS 4KSc"; 827 break; 828 case PRID_IMP_5KC: 829 c->cputype = CPU_5KC; 830 __cpu_name[cpu] = "MIPS 5Kc"; 831 break; 832 case PRID_IMP_5KE: 833 c->cputype = CPU_5KE; 834 __cpu_name[cpu] = "MIPS 5KE"; 835 break; 836 case PRID_IMP_20KC: 837 c->cputype = CPU_20KC; 838 __cpu_name[cpu] = "MIPS 20Kc"; 839 break; 840 case PRID_IMP_24K: 841 case PRID_IMP_24KE: 842 c->cputype = CPU_24K; 843 __cpu_name[cpu] = "MIPS 24Kc"; 844 break; 845 case PRID_IMP_25KF: 846 c->cputype = CPU_25KF; 847 __cpu_name[cpu] = "MIPS 25Kc"; 848 break; 849 case PRID_IMP_34K: 850 c->cputype = CPU_34K; 851 __cpu_name[cpu] = "MIPS 34Kc"; 852 break; 853 case PRID_IMP_74K: 854 c->cputype = CPU_74K; 855 __cpu_name[cpu] = "MIPS 74Kc"; 856 break; 857 case PRID_IMP_M14KC: 858 c->cputype = CPU_M14KC; 859 __cpu_name[cpu] = "MIPS M14Kc"; 860 break; 861 case PRID_IMP_1004K: 862 c->cputype = CPU_1004K; 863 __cpu_name[cpu] = "MIPS 1004Kc"; 864 break; 865 case PRID_IMP_1074K: 866 c->cputype = CPU_74K; 867 __cpu_name[cpu] = "MIPS 1074Kc"; 868 break; 869 } 870 871 spram_config(); 872 } 873 874 static inline void cpu_probe_alchemy(struct cpuinfo_mips *c, unsigned int cpu) 875 { 876 decode_configs(c); 877 switch (c->processor_id & 0xff00) { 878 case PRID_IMP_AU1_REV1: 879 case PRID_IMP_AU1_REV2: 880 c->cputype = CPU_ALCHEMY; 881 switch ((c->processor_id >> 24) & 0xff) { 882 case 0: 883 __cpu_name[cpu] = "Au1000"; 884 break; 885 case 1: 886 __cpu_name[cpu] = "Au1500"; 887 break; 888 case 2: 889 __cpu_name[cpu] = "Au1100"; 890 break; 891 case 3: 892 __cpu_name[cpu] = "Au1550"; 893 break; 894 case 4: 895 __cpu_name[cpu] = "Au1200"; 896 if ((c->processor_id & 0xff) == 2) 897 __cpu_name[cpu] = "Au1250"; 898 break; 899 case 5: 900 __cpu_name[cpu] = "Au1210"; 901 break; 902 default: 903 __cpu_name[cpu] = "Au1xxx"; 904 break; 905 } 906 break; 907 } 908 } 909 910 static inline void cpu_probe_sibyte(struct cpuinfo_mips *c, unsigned int cpu) 911 { 912 decode_configs(c); 913 914 switch (c->processor_id & 0xff00) { 915 case PRID_IMP_SB1: 916 c->cputype = CPU_SB1; 917 __cpu_name[cpu] = "SiByte SB1"; 918 /* FPU in pass1 is known to have issues. */ 919 if ((c->processor_id & 0xff) < 0x02) 920 c->options &= ~(MIPS_CPU_FPU | MIPS_CPU_32FPR); 921 break; 922 case PRID_IMP_SB1A: 923 c->cputype = CPU_SB1A; 924 __cpu_name[cpu] = "SiByte SB1A"; 925 break; 926 } 927 } 928 929 static inline void cpu_probe_sandcraft(struct cpuinfo_mips *c, unsigned int cpu) 930 { 931 decode_configs(c); 932 switch (c->processor_id & 0xff00) { 933 case PRID_IMP_SR71000: 934 c->cputype = CPU_SR71000; 935 __cpu_name[cpu] = "Sandcraft SR71000"; 936 c->scache.ways = 8; 937 c->tlbsize = 64; 938 break; 939 } 940 } 941 942 static inline void cpu_probe_nxp(struct cpuinfo_mips *c, unsigned int cpu) 943 { 944 decode_configs(c); 945 switch (c->processor_id & 0xff00) { 946 case PRID_IMP_PR4450: 947 c->cputype = CPU_PR4450; 948 __cpu_name[cpu] = "Philips PR4450"; 949 c->isa_level = MIPS_CPU_ISA_M32R1; 950 break; 951 } 952 } 953 954 static inline void cpu_probe_broadcom(struct cpuinfo_mips *c, unsigned int cpu) 955 { 956 decode_configs(c); 957 switch (c->processor_id & 0xff00) { 958 case PRID_IMP_BMIPS32_REV4: 959 case PRID_IMP_BMIPS32_REV8: 960 c->cputype = CPU_BMIPS32; 961 __cpu_name[cpu] = "Broadcom BMIPS32"; 962 set_elf_platform(cpu, "bmips32"); 963 break; 964 case PRID_IMP_BMIPS3300: 965 case PRID_IMP_BMIPS3300_ALT: 966 case PRID_IMP_BMIPS3300_BUG: 967 c->cputype = CPU_BMIPS3300; 968 __cpu_name[cpu] = "Broadcom BMIPS3300"; 969 set_elf_platform(cpu, "bmips3300"); 970 break; 971 case PRID_IMP_BMIPS43XX: { 972 int rev = c->processor_id & 0xff; 973 974 if (rev >= PRID_REV_BMIPS4380_LO && 975 rev <= PRID_REV_BMIPS4380_HI) { 976 c->cputype = CPU_BMIPS4380; 977 __cpu_name[cpu] = "Broadcom BMIPS4380"; 978 set_elf_platform(cpu, "bmips4380"); 979 } else { 980 c->cputype = CPU_BMIPS4350; 981 __cpu_name[cpu] = "Broadcom BMIPS4350"; 982 set_elf_platform(cpu, "bmips4350"); 983 } 984 break; 985 } 986 case PRID_IMP_BMIPS5000: 987 c->cputype = CPU_BMIPS5000; 988 __cpu_name[cpu] = "Broadcom BMIPS5000"; 989 set_elf_platform(cpu, "bmips5000"); 990 c->options |= MIPS_CPU_ULRI; 991 break; 992 } 993 } 994 995 static inline void cpu_probe_cavium(struct cpuinfo_mips *c, unsigned int cpu) 996 { 997 decode_configs(c); 998 switch (c->processor_id & 0xff00) { 999 case PRID_IMP_CAVIUM_CN38XX: 1000 case PRID_IMP_CAVIUM_CN31XX: 1001 case PRID_IMP_CAVIUM_CN30XX: 1002 c->cputype = CPU_CAVIUM_OCTEON; 1003 __cpu_name[cpu] = "Cavium Octeon"; 1004 goto platform; 1005 case PRID_IMP_CAVIUM_CN58XX: 1006 case PRID_IMP_CAVIUM_CN56XX: 1007 case PRID_IMP_CAVIUM_CN50XX: 1008 case PRID_IMP_CAVIUM_CN52XX: 1009 c->cputype = CPU_CAVIUM_OCTEON_PLUS; 1010 __cpu_name[cpu] = "Cavium Octeon+"; 1011 platform: 1012 set_elf_platform(cpu, "octeon"); 1013 break; 1014 case PRID_IMP_CAVIUM_CN61XX: 1015 case PRID_IMP_CAVIUM_CN63XX: 1016 case PRID_IMP_CAVIUM_CN66XX: 1017 case PRID_IMP_CAVIUM_CN68XX: 1018 c->cputype = CPU_CAVIUM_OCTEON2; 1019 __cpu_name[cpu] = "Cavium Octeon II"; 1020 set_elf_platform(cpu, "octeon2"); 1021 break; 1022 default: 1023 printk(KERN_INFO "Unknown Octeon chip!\n"); 1024 c->cputype = CPU_UNKNOWN; 1025 break; 1026 } 1027 } 1028 1029 static inline void cpu_probe_ingenic(struct cpuinfo_mips *c, unsigned int cpu) 1030 { 1031 decode_configs(c); 1032 /* JZRISC does not implement the CP0 counter. */ 1033 c->options &= ~MIPS_CPU_COUNTER; 1034 switch (c->processor_id & 0xff00) { 1035 case PRID_IMP_JZRISC: 1036 c->cputype = CPU_JZRISC; 1037 __cpu_name[cpu] = "Ingenic JZRISC"; 1038 break; 1039 default: 1040 panic("Unknown Ingenic Processor ID!"); 1041 break; 1042 } 1043 } 1044 1045 static inline void cpu_probe_netlogic(struct cpuinfo_mips *c, int cpu) 1046 { 1047 decode_configs(c); 1048 1049 if ((c->processor_id & 0xff00) == PRID_IMP_NETLOGIC_AU13XX) { 1050 c->cputype = CPU_ALCHEMY; 1051 __cpu_name[cpu] = "Au1300"; 1052 /* following stuff is not for Alchemy */ 1053 return; 1054 } 1055 1056 c->options = (MIPS_CPU_TLB | 1057 MIPS_CPU_4KEX | 1058 MIPS_CPU_COUNTER | 1059 MIPS_CPU_DIVEC | 1060 MIPS_CPU_WATCH | 1061 MIPS_CPU_EJTAG | 1062 MIPS_CPU_LLSC); 1063 1064 switch (c->processor_id & 0xff00) { 1065 case PRID_IMP_NETLOGIC_XLP8XX: 1066 case PRID_IMP_NETLOGIC_XLP3XX: 1067 c->cputype = CPU_XLP; 1068 __cpu_name[cpu] = "Netlogic XLP"; 1069 break; 1070 1071 case PRID_IMP_NETLOGIC_XLR732: 1072 case PRID_IMP_NETLOGIC_XLR716: 1073 case PRID_IMP_NETLOGIC_XLR532: 1074 case PRID_IMP_NETLOGIC_XLR308: 1075 case PRID_IMP_NETLOGIC_XLR532C: 1076 case PRID_IMP_NETLOGIC_XLR516C: 1077 case PRID_IMP_NETLOGIC_XLR508C: 1078 case PRID_IMP_NETLOGIC_XLR308C: 1079 c->cputype = CPU_XLR; 1080 __cpu_name[cpu] = "Netlogic XLR"; 1081 break; 1082 1083 case PRID_IMP_NETLOGIC_XLS608: 1084 case PRID_IMP_NETLOGIC_XLS408: 1085 case PRID_IMP_NETLOGIC_XLS404: 1086 case PRID_IMP_NETLOGIC_XLS208: 1087 case PRID_IMP_NETLOGIC_XLS204: 1088 case PRID_IMP_NETLOGIC_XLS108: 1089 case PRID_IMP_NETLOGIC_XLS104: 1090 case PRID_IMP_NETLOGIC_XLS616B: 1091 case PRID_IMP_NETLOGIC_XLS608B: 1092 case PRID_IMP_NETLOGIC_XLS416B: 1093 case PRID_IMP_NETLOGIC_XLS412B: 1094 case PRID_IMP_NETLOGIC_XLS408B: 1095 case PRID_IMP_NETLOGIC_XLS404B: 1096 c->cputype = CPU_XLR; 1097 __cpu_name[cpu] = "Netlogic XLS"; 1098 break; 1099 1100 default: 1101 pr_info("Unknown Netlogic chip id [%02x]!\n", 1102 c->processor_id); 1103 c->cputype = CPU_XLR; 1104 break; 1105 } 1106 1107 if (c->cputype == CPU_XLP) { 1108 c->isa_level = MIPS_CPU_ISA_M64R2; 1109 c->options |= (MIPS_CPU_FPU | MIPS_CPU_ULRI | MIPS_CPU_MCHECK); 1110 /* This will be updated again after all threads are woken up */ 1111 c->tlbsize = ((read_c0_config6() >> 16) & 0xffff) + 1; 1112 } else { 1113 c->isa_level = MIPS_CPU_ISA_M64R1; 1114 c->tlbsize = ((read_c0_config1() >> 25) & 0x3f) + 1; 1115 } 1116 } 1117 1118 #ifdef CONFIG_64BIT 1119 /* For use by uaccess.h */ 1120 u64 __ua_limit; 1121 EXPORT_SYMBOL(__ua_limit); 1122 #endif 1123 1124 const char *__cpu_name[NR_CPUS]; 1125 const char *__elf_platform; 1126 1127 __cpuinit void cpu_probe(void) 1128 { 1129 struct cpuinfo_mips *c = ¤t_cpu_data; 1130 unsigned int cpu = smp_processor_id(); 1131 1132 c->processor_id = PRID_IMP_UNKNOWN; 1133 c->fpu_id = FPIR_IMP_NONE; 1134 c->cputype = CPU_UNKNOWN; 1135 1136 c->processor_id = read_c0_prid(); 1137 switch (c->processor_id & 0xff0000) { 1138 case PRID_COMP_LEGACY: 1139 cpu_probe_legacy(c, cpu); 1140 break; 1141 case PRID_COMP_MIPS: 1142 cpu_probe_mips(c, cpu); 1143 break; 1144 case PRID_COMP_ALCHEMY: 1145 cpu_probe_alchemy(c, cpu); 1146 break; 1147 case PRID_COMP_SIBYTE: 1148 cpu_probe_sibyte(c, cpu); 1149 break; 1150 case PRID_COMP_BROADCOM: 1151 cpu_probe_broadcom(c, cpu); 1152 break; 1153 case PRID_COMP_SANDCRAFT: 1154 cpu_probe_sandcraft(c, cpu); 1155 break; 1156 case PRID_COMP_NXP: 1157 cpu_probe_nxp(c, cpu); 1158 break; 1159 case PRID_COMP_CAVIUM: 1160 cpu_probe_cavium(c, cpu); 1161 break; 1162 case PRID_COMP_INGENIC: 1163 cpu_probe_ingenic(c, cpu); 1164 break; 1165 case PRID_COMP_NETLOGIC: 1166 cpu_probe_netlogic(c, cpu); 1167 break; 1168 } 1169 1170 BUG_ON(!__cpu_name[cpu]); 1171 BUG_ON(c->cputype == CPU_UNKNOWN); 1172 1173 /* 1174 * Platform code can force the cpu type to optimize code 1175 * generation. In that case be sure the cpu type is correctly 1176 * manually setup otherwise it could trigger some nasty bugs. 1177 */ 1178 BUG_ON(current_cpu_type() != c->cputype); 1179 1180 if (mips_fpu_disabled) 1181 c->options &= ~MIPS_CPU_FPU; 1182 1183 if (mips_dsp_disabled) 1184 c->ases &= ~(MIPS_ASE_DSP | MIPS_ASE_DSP2P); 1185 1186 if (c->options & MIPS_CPU_FPU) { 1187 c->fpu_id = cpu_get_fpu_id(); 1188 1189 if (c->isa_level == MIPS_CPU_ISA_M32R1 || 1190 c->isa_level == MIPS_CPU_ISA_M32R2 || 1191 c->isa_level == MIPS_CPU_ISA_M64R1 || 1192 c->isa_level == MIPS_CPU_ISA_M64R2) { 1193 if (c->fpu_id & MIPS_FPIR_3D) 1194 c->ases |= MIPS_ASE_MIPS3D; 1195 } 1196 } 1197 1198 if (cpu_has_mips_r2) { 1199 c->srsets = ((read_c0_srsctl() >> 26) & 0x0f) + 1; 1200 /* R2 has Performance Counter Interrupt indicator */ 1201 c->options |= MIPS_CPU_PCI; 1202 } 1203 else 1204 c->srsets = 1; 1205 1206 cpu_probe_vmbits(c); 1207 1208 #ifdef CONFIG_64BIT 1209 if (cpu == 0) 1210 __ua_limit = ~((1ull << cpu_vmbits) - 1); 1211 #endif 1212 } 1213 1214 __cpuinit void cpu_report(void) 1215 { 1216 struct cpuinfo_mips *c = ¤t_cpu_data; 1217 1218 printk(KERN_INFO "CPU revision is: %08x (%s)\n", 1219 c->processor_id, cpu_name_string()); 1220 if (c->options & MIPS_CPU_FPU) 1221 printk(KERN_INFO "FPU revision is: %08x\n", c->fpu_id); 1222 } 1223