1 /* 2 * This file is subject to the terms and conditions of the GNU General Public 3 * License. See the file "COPYING" in the main directory of this archive 4 * for more details. 5 * 6 * Copyright (C) 2007 MIPS Technologies, Inc. 7 * Copyright (C) 2007 Ralf Baechle <ralf@linux-mips.org> 8 */ 9 #include <linux/clockchips.h> 10 #include <linux/interrupt.h> 11 #include <linux/percpu.h> 12 #include <linux/smp.h> 13 #include <linux/irq.h> 14 15 #include <asm/time.h> 16 #include <asm/cevt-r4k.h> 17 18 static int mips_next_event(unsigned long delta, 19 struct clock_event_device *evt) 20 { 21 unsigned int cnt; 22 int res; 23 24 cnt = read_c0_count(); 25 cnt += delta; 26 write_c0_compare(cnt); 27 res = ((int)(read_c0_count() - cnt) >= 0) ? -ETIME : 0; 28 return res; 29 } 30 31 void mips_set_clock_mode(enum clock_event_mode mode, 32 struct clock_event_device *evt) 33 { 34 /* Nothing to do ... */ 35 } 36 37 DEFINE_PER_CPU(struct clock_event_device, mips_clockevent_device); 38 int cp0_timer_irq_installed; 39 40 /* 41 * Possibly handle a performance counter interrupt. 42 * Return true if the timer interrupt should not be checked 43 */ 44 static inline int handle_perf_irq(int r2) 45 { 46 /* 47 * The performance counter overflow interrupt may be shared with the 48 * timer interrupt (cp0_perfcount_irq < 0). If it is and a 49 * performance counter has overflowed (perf_irq() == IRQ_HANDLED) 50 * and we can't reliably determine if a counter interrupt has also 51 * happened (!r2) then don't check for a timer interrupt. 52 */ 53 return (cp0_perfcount_irq < 0) && 54 perf_irq() == IRQ_HANDLED && 55 !r2; 56 } 57 58 irqreturn_t c0_compare_interrupt(int irq, void *dev_id) 59 { 60 const int r2 = cpu_has_mips_r2_r6; 61 struct clock_event_device *cd; 62 int cpu = smp_processor_id(); 63 64 /* 65 * Suckage alert: 66 * Before R2 of the architecture there was no way to see if a 67 * performance counter interrupt was pending, so we have to run 68 * the performance counter interrupt handler anyway. 69 */ 70 if (handle_perf_irq(r2)) 71 return IRQ_HANDLED; 72 73 /* 74 * The same applies to performance counter interrupts. But with the 75 * above we now know that the reason we got here must be a timer 76 * interrupt. Being the paranoiacs we are we check anyway. 77 */ 78 if (!r2 || (read_c0_cause() & CAUSEF_TI)) { 79 /* Clear Count/Compare Interrupt */ 80 write_c0_compare(read_c0_compare()); 81 cd = &per_cpu(mips_clockevent_device, cpu); 82 cd->event_handler(cd); 83 84 return IRQ_HANDLED; 85 } 86 87 return IRQ_NONE; 88 } 89 90 struct irqaction c0_compare_irqaction = { 91 .handler = c0_compare_interrupt, 92 /* 93 * IRQF_SHARED: The timer interrupt may be shared with other interrupts 94 * such as perf counter and FDC interrupts. 95 */ 96 .flags = IRQF_PERCPU | IRQF_TIMER | IRQF_SHARED, 97 .name = "timer", 98 }; 99 100 101 void mips_event_handler(struct clock_event_device *dev) 102 { 103 } 104 105 /* 106 * FIXME: This doesn't hold for the relocated E9000 compare interrupt. 107 */ 108 static int c0_compare_int_pending(void) 109 { 110 /* When cpu_has_mips_r2, this checks Cause.TI instead of Cause.IP7 */ 111 return (read_c0_cause() >> cp0_compare_irq_shift) & (1ul << CAUSEB_IP); 112 } 113 114 /* 115 * Compare interrupt can be routed and latched outside the core, 116 * so wait up to worst case number of cycle counter ticks for timer interrupt 117 * changes to propagate to the cause register. 118 */ 119 #define COMPARE_INT_SEEN_TICKS 50 120 121 int c0_compare_int_usable(void) 122 { 123 unsigned int delta; 124 unsigned int cnt; 125 126 #ifdef CONFIG_KVM_GUEST 127 return 1; 128 #endif 129 130 /* 131 * IP7 already pending? Try to clear it by acking the timer. 132 */ 133 if (c0_compare_int_pending()) { 134 cnt = read_c0_count(); 135 write_c0_compare(cnt); 136 back_to_back_c0_hazard(); 137 while (read_c0_count() < (cnt + COMPARE_INT_SEEN_TICKS)) 138 if (!c0_compare_int_pending()) 139 break; 140 if (c0_compare_int_pending()) 141 return 0; 142 } 143 144 for (delta = 0x10; delta <= 0x400000; delta <<= 1) { 145 cnt = read_c0_count(); 146 cnt += delta; 147 write_c0_compare(cnt); 148 back_to_back_c0_hazard(); 149 if ((int)(read_c0_count() - cnt) < 0) 150 break; 151 /* increase delta if the timer was already expired */ 152 } 153 154 while ((int)(read_c0_count() - cnt) <= 0) 155 ; /* Wait for expiry */ 156 157 while (read_c0_count() < (cnt + COMPARE_INT_SEEN_TICKS)) 158 if (c0_compare_int_pending()) 159 break; 160 if (!c0_compare_int_pending()) 161 return 0; 162 cnt = read_c0_count(); 163 write_c0_compare(cnt); 164 back_to_back_c0_hazard(); 165 while (read_c0_count() < (cnt + COMPARE_INT_SEEN_TICKS)) 166 if (!c0_compare_int_pending()) 167 break; 168 if (c0_compare_int_pending()) 169 return 0; 170 171 /* 172 * Feels like a real count / compare timer. 173 */ 174 return 1; 175 } 176 177 int r4k_clockevent_init(void) 178 { 179 unsigned int cpu = smp_processor_id(); 180 struct clock_event_device *cd; 181 unsigned int irq; 182 183 if (!cpu_has_counter || !mips_hpt_frequency) 184 return -ENXIO; 185 186 if (!c0_compare_int_usable()) 187 return -ENXIO; 188 189 /* 190 * With vectored interrupts things are getting platform specific. 191 * get_c0_compare_int is a hook to allow a platform to return the 192 * interrupt number of it's liking. 193 */ 194 irq = MIPS_CPU_IRQ_BASE + cp0_compare_irq; 195 if (get_c0_compare_int) 196 irq = get_c0_compare_int(); 197 198 cd = &per_cpu(mips_clockevent_device, cpu); 199 200 cd->name = "MIPS"; 201 cd->features = CLOCK_EVT_FEAT_ONESHOT | 202 CLOCK_EVT_FEAT_C3STOP | 203 CLOCK_EVT_FEAT_PERCPU; 204 205 clockevent_set_clock(cd, mips_hpt_frequency); 206 207 /* Calculate the min / max delta */ 208 cd->max_delta_ns = clockevent_delta2ns(0x7fffffff, cd); 209 cd->min_delta_ns = clockevent_delta2ns(0x300, cd); 210 211 cd->rating = 300; 212 cd->irq = irq; 213 cd->cpumask = cpumask_of(cpu); 214 cd->set_next_event = mips_next_event; 215 cd->set_mode = mips_set_clock_mode; 216 cd->event_handler = mips_event_handler; 217 218 clockevents_register_device(cd); 219 220 if (cp0_timer_irq_installed) 221 return 0; 222 223 cp0_timer_irq_installed = 1; 224 225 setup_irq(irq, &c0_compare_irqaction); 226 227 return 0; 228 } 229 230