1/* 2 * This file is subject to the terms and conditions of the GNU General Public 3 * License. See the file "COPYING" in the main directory of this archive 4 * for more details. 5 * 6 * Copyright (C) 2011 by Kevin Cernekee (cernekee@gmail.com) 7 * 8 * Reset/NMI/re-entry vectors for BMIPS processors 9 */ 10 11#include <linux/init.h> 12 13#include <asm/asm.h> 14#include <asm/asmmacro.h> 15#include <asm/cacheops.h> 16#include <asm/regdef.h> 17#include <asm/mipsregs.h> 18#include <asm/stackframe.h> 19#include <asm/addrspace.h> 20#include <asm/hazards.h> 21#include <asm/bmips.h> 22 23 .macro BARRIER 24 .set mips32 25 _ssnop 26 _ssnop 27 _ssnop 28 .set mips0 29 .endm 30 31/*********************************************************************** 32 * Alternate CPU1 startup vector for BMIPS4350 33 * 34 * On some systems the bootloader has already started CPU1 and configured 35 * it to resume execution at 0x8000_0200 (!BEV IV vector) when it is 36 * triggered by the SW1 interrupt. If that is the case we try to move 37 * it to a more convenient place: BMIPS_WARM_RESTART_VEC @ 0x8000_0380. 38 ***********************************************************************/ 39 40LEAF(bmips_smp_movevec) 41 la k0, 1f 42 li k1, CKSEG1 43 or k0, k1 44 jr k0 45 461: 47 /* clear IV, pending IPIs */ 48 mtc0 zero, CP0_CAUSE 49 50 /* re-enable IRQs to wait for SW1 */ 51 li k0, ST0_IE | ST0_BEV | STATUSF_IP1 52 mtc0 k0, CP0_STATUS 53 54 /* set up CPU1 CBR; move BASE to 0xa000_0000 */ 55 li k0, 0xff400000 56 mtc0 k0, $22, 6 57 li k1, CKSEG1 | BMIPS_RELO_VECTOR_CONTROL_1 58 or k0, k1 59 li k1, 0xa0080000 60 sw k1, 0(k0) 61 62 /* wait here for SW1 interrupt from bmips_boot_secondary() */ 63 wait 64 65 la k0, bmips_reset_nmi_vec 66 li k1, CKSEG1 67 or k0, k1 68 jr k0 69END(bmips_smp_movevec) 70 71/*********************************************************************** 72 * Reset/NMI vector 73 * For BMIPS processors that can relocate their exception vectors, this 74 * entire function gets copied to 0x8000_0000. 75 ***********************************************************************/ 76 77NESTED(bmips_reset_nmi_vec, PT_SIZE, sp) 78 .set push 79 .set noat 80 .align 4 81 82#ifdef CONFIG_SMP 83 /* if the NMI bit is clear, assume this is a CPU1 reset instead */ 84 li k1, (1 << 19) 85 mfc0 k0, CP0_STATUS 86 and k0, k1 87 beqz k0, bmips_smp_entry 88 89#if defined(CONFIG_CPU_BMIPS5000) 90 /* if we're not on core 0, this must be the SMP boot signal */ 91 li k1, (3 << 25) 92 mfc0 k0, $22 93 and k0, k1 94 bnez k0, bmips_smp_entry 95#endif 96#endif /* CONFIG_SMP */ 97 98 /* nope, it's just a regular NMI */ 99 SAVE_ALL 100 move a0, sp 101 102 /* clear EXL, ERL, BEV so that TLB refills still work */ 103 mfc0 k0, CP0_STATUS 104 li k1, ST0_ERL | ST0_EXL | ST0_BEV | ST0_IE 105 or k0, k1 106 xor k0, k1 107 mtc0 k0, CP0_STATUS 108 BARRIER 109 110 /* jump to the NMI handler function */ 111 la k0, nmi_handler 112 jr k0 113 114 RESTORE_ALL 115 .set mips3 116 eret 117 118/*********************************************************************** 119 * CPU1 reset vector (used for the initial boot only) 120 * This is still part of bmips_reset_nmi_vec(). 121 ***********************************************************************/ 122 123#ifdef CONFIG_SMP 124 125bmips_smp_entry: 126 127 /* set up CP0 STATUS; enable FPU */ 128 li k0, 0x30000000 129 mtc0 k0, CP0_STATUS 130 BARRIER 131 132 /* set local CP0 CONFIG to make kseg0 cacheable, write-back */ 133 mfc0 k0, CP0_CONFIG 134 ori k0, 0x07 135 xori k0, 0x04 136 mtc0 k0, CP0_CONFIG 137 138#if defined(CONFIG_CPU_BMIPS4350) || defined(CONFIG_CPU_BMIPS4380) 139 /* initialize CPU1's local I-cache */ 140 li k0, 0x80000000 141 li k1, 0x80010000 142 mtc0 zero, $28 143 mtc0 zero, $28, 1 144 BARRIER 145 1461: cache Index_Store_Tag_I, 0(k0) 147 addiu k0, 16 148 bne k0, k1, 1b 149#elif defined(CONFIG_CPU_BMIPS5000) 150 /* set exception vector base */ 151 la k0, ebase 152 lw k0, 0(k0) 153 mtc0 k0, $15, 1 154 BARRIER 155#endif 156 157 /* jump back to kseg0 in case we need to remap the kseg1 area */ 158 la k0, 1f 159 jr k0 1601: 161 la k0, bmips_enable_xks01 162 jalr k0 163 164 /* use temporary stack to set up upper memory TLB */ 165 li sp, BMIPS_WARM_RESTART_VEC 166 la k0, plat_wired_tlb_setup 167 jalr k0 168 169 /* switch to permanent stack and continue booting */ 170 171 .global bmips_secondary_reentry 172bmips_secondary_reentry: 173 la k0, bmips_smp_boot_sp 174 lw sp, 0(k0) 175 la k0, bmips_smp_boot_gp 176 lw gp, 0(k0) 177 la k0, start_secondary 178 jr k0 179 180#endif /* CONFIG_SMP */ 181 182 .align 4 183 .global bmips_reset_nmi_vec_end 184bmips_reset_nmi_vec_end: 185 186END(bmips_reset_nmi_vec) 187 188 .set pop 189 .previous 190 191/*********************************************************************** 192 * CPU1 warm restart vector (used for second and subsequent boots). 193 * Also used for S2 standby recovery (PM). 194 * This entire function gets copied to (BMIPS_WARM_RESTART_VEC) 195 ***********************************************************************/ 196 197LEAF(bmips_smp_int_vec) 198 199 .align 4 200 mfc0 k0, CP0_STATUS 201 ori k0, 0x01 202 xori k0, 0x01 203 mtc0 k0, CP0_STATUS 204 eret 205 206 .align 4 207 .global bmips_smp_int_vec_end 208bmips_smp_int_vec_end: 209 210END(bmips_smp_int_vec) 211 212/*********************************************************************** 213 * XKS01 support 214 * Certain CPUs support extending kseg0 to 1024MB. 215 ***********************************************************************/ 216 217LEAF(bmips_enable_xks01) 218 219#if defined(CONFIG_XKS01) 220 221#if defined(CONFIG_CPU_BMIPS4380) 222 mfc0 t0, $22, 3 223 li t1, 0x1ff0 224 li t2, (1 << 12) | (1 << 9) 225 or t0, t1 226 xor t0, t1 227 or t0, t2 228 mtc0 t0, $22, 3 229 BARRIER 230#elif defined(CONFIG_CPU_BMIPS5000) 231 mfc0 t0, $22, 5 232 li t1, 0x01ff 233 li t2, (1 << 8) | (1 << 5) 234 or t0, t1 235 xor t0, t1 236 or t0, t2 237 mtc0 t0, $22, 5 238 BARRIER 239#else 240 241#error Missing XKS01 setup 242 243#endif 244 245#endif /* defined(CONFIG_XKS01) */ 246 247 jr ra 248 249END(bmips_enable_xks01) 250 251 .previous 252