1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * asm-offsets.c: Calculate pt_regs and task_struct offsets. 4 * 5 * Copyright (C) 1996 David S. Miller 6 * Copyright (C) 1997, 1998, 1999, 2000, 2001, 2002, 2003 Ralf Baechle 7 * Copyright (C) 1999, 2000 Silicon Graphics, Inc. 8 * 9 * Kevin Kissell, kevink@mips.com and Carsten Langgaard, carstenl@mips.com 10 * Copyright (C) 2000 MIPS Technologies, Inc. 11 */ 12 #include <linux/compat.h> 13 #include <linux/types.h> 14 #include <linux/sched.h> 15 #include <linux/mm.h> 16 #include <linux/kbuild.h> 17 #include <linux/suspend.h> 18 #include <asm/cpu-info.h> 19 #include <asm/pm.h> 20 #include <asm/ptrace.h> 21 #include <asm/processor.h> 22 #include <asm/smp-cps.h> 23 24 #include <linux/kvm_host.h> 25 26 void output_ptreg_defines(void); 27 void output_ptreg_defines(void) 28 { 29 COMMENT("MIPS pt_regs offsets."); 30 OFFSET(PT_R0, pt_regs, regs[0]); 31 OFFSET(PT_R1, pt_regs, regs[1]); 32 OFFSET(PT_R2, pt_regs, regs[2]); 33 OFFSET(PT_R3, pt_regs, regs[3]); 34 OFFSET(PT_R4, pt_regs, regs[4]); 35 OFFSET(PT_R5, pt_regs, regs[5]); 36 OFFSET(PT_R6, pt_regs, regs[6]); 37 OFFSET(PT_R7, pt_regs, regs[7]); 38 OFFSET(PT_R8, pt_regs, regs[8]); 39 OFFSET(PT_R9, pt_regs, regs[9]); 40 OFFSET(PT_R10, pt_regs, regs[10]); 41 OFFSET(PT_R11, pt_regs, regs[11]); 42 OFFSET(PT_R12, pt_regs, regs[12]); 43 OFFSET(PT_R13, pt_regs, regs[13]); 44 OFFSET(PT_R14, pt_regs, regs[14]); 45 OFFSET(PT_R15, pt_regs, regs[15]); 46 OFFSET(PT_R16, pt_regs, regs[16]); 47 OFFSET(PT_R17, pt_regs, regs[17]); 48 OFFSET(PT_R18, pt_regs, regs[18]); 49 OFFSET(PT_R19, pt_regs, regs[19]); 50 OFFSET(PT_R20, pt_regs, regs[20]); 51 OFFSET(PT_R21, pt_regs, regs[21]); 52 OFFSET(PT_R22, pt_regs, regs[22]); 53 OFFSET(PT_R23, pt_regs, regs[23]); 54 OFFSET(PT_R24, pt_regs, regs[24]); 55 OFFSET(PT_R25, pt_regs, regs[25]); 56 OFFSET(PT_R26, pt_regs, regs[26]); 57 OFFSET(PT_R27, pt_regs, regs[27]); 58 OFFSET(PT_R28, pt_regs, regs[28]); 59 OFFSET(PT_R29, pt_regs, regs[29]); 60 OFFSET(PT_R30, pt_regs, regs[30]); 61 OFFSET(PT_R31, pt_regs, regs[31]); 62 OFFSET(PT_LO, pt_regs, lo); 63 OFFSET(PT_HI, pt_regs, hi); 64 #ifdef CONFIG_CPU_HAS_SMARTMIPS 65 OFFSET(PT_ACX, pt_regs, acx); 66 #endif 67 OFFSET(PT_EPC, pt_regs, cp0_epc); 68 OFFSET(PT_BVADDR, pt_regs, cp0_badvaddr); 69 OFFSET(PT_STATUS, pt_regs, cp0_status); 70 OFFSET(PT_CAUSE, pt_regs, cp0_cause); 71 #ifdef CONFIG_CPU_CAVIUM_OCTEON 72 OFFSET(PT_MPL, pt_regs, mpl); 73 OFFSET(PT_MTP, pt_regs, mtp); 74 #endif /* CONFIG_CPU_CAVIUM_OCTEON */ 75 DEFINE(PT_SIZE, sizeof(struct pt_regs)); 76 BLANK(); 77 } 78 79 void output_task_defines(void); 80 void output_task_defines(void) 81 { 82 COMMENT("MIPS task_struct offsets."); 83 OFFSET(TASK_THREAD_INFO, task_struct, stack); 84 OFFSET(TASK_FLAGS, task_struct, flags); 85 OFFSET(TASK_MM, task_struct, mm); 86 OFFSET(TASK_PID, task_struct, pid); 87 #if defined(CONFIG_STACKPROTECTOR) 88 OFFSET(TASK_STACK_CANARY, task_struct, stack_canary); 89 #endif 90 DEFINE(TASK_STRUCT_SIZE, sizeof(struct task_struct)); 91 BLANK(); 92 } 93 94 void output_thread_info_defines(void); 95 void output_thread_info_defines(void) 96 { 97 COMMENT("MIPS thread_info offsets."); 98 OFFSET(TI_TASK, thread_info, task); 99 OFFSET(TI_FLAGS, thread_info, flags); 100 OFFSET(TI_TP_VALUE, thread_info, tp_value); 101 OFFSET(TI_CPU, thread_info, cpu); 102 OFFSET(TI_PRE_COUNT, thread_info, preempt_count); 103 OFFSET(TI_REGS, thread_info, regs); 104 OFFSET(TI_SYSCALL, thread_info, syscall); 105 DEFINE(_THREAD_SIZE, THREAD_SIZE); 106 DEFINE(_THREAD_MASK, THREAD_MASK); 107 DEFINE(_IRQ_STACK_SIZE, IRQ_STACK_SIZE); 108 DEFINE(_IRQ_STACK_START, IRQ_STACK_START); 109 BLANK(); 110 } 111 112 void output_thread_defines(void); 113 void output_thread_defines(void) 114 { 115 COMMENT("MIPS specific thread_struct offsets."); 116 OFFSET(THREAD_REG16, task_struct, thread.reg16); 117 OFFSET(THREAD_REG17, task_struct, thread.reg17); 118 OFFSET(THREAD_REG18, task_struct, thread.reg18); 119 OFFSET(THREAD_REG19, task_struct, thread.reg19); 120 OFFSET(THREAD_REG20, task_struct, thread.reg20); 121 OFFSET(THREAD_REG21, task_struct, thread.reg21); 122 OFFSET(THREAD_REG22, task_struct, thread.reg22); 123 OFFSET(THREAD_REG23, task_struct, thread.reg23); 124 OFFSET(THREAD_REG29, task_struct, thread.reg29); 125 OFFSET(THREAD_REG30, task_struct, thread.reg30); 126 OFFSET(THREAD_REG31, task_struct, thread.reg31); 127 OFFSET(THREAD_STATUS, task_struct, 128 thread.cp0_status); 129 130 OFFSET(THREAD_BVADDR, task_struct, \ 131 thread.cp0_badvaddr); 132 OFFSET(THREAD_BUADDR, task_struct, \ 133 thread.cp0_baduaddr); 134 OFFSET(THREAD_ECODE, task_struct, \ 135 thread.error_code); 136 OFFSET(THREAD_TRAPNO, task_struct, thread.trap_nr); 137 BLANK(); 138 } 139 140 #ifdef CONFIG_MIPS_FP_SUPPORT 141 void output_thread_fpu_defines(void); 142 void output_thread_fpu_defines(void) 143 { 144 OFFSET(THREAD_FPU, task_struct, thread.fpu); 145 146 OFFSET(THREAD_FPR0, task_struct, thread.fpu.fpr[0]); 147 OFFSET(THREAD_FPR1, task_struct, thread.fpu.fpr[1]); 148 OFFSET(THREAD_FPR2, task_struct, thread.fpu.fpr[2]); 149 OFFSET(THREAD_FPR3, task_struct, thread.fpu.fpr[3]); 150 OFFSET(THREAD_FPR4, task_struct, thread.fpu.fpr[4]); 151 OFFSET(THREAD_FPR5, task_struct, thread.fpu.fpr[5]); 152 OFFSET(THREAD_FPR6, task_struct, thread.fpu.fpr[6]); 153 OFFSET(THREAD_FPR7, task_struct, thread.fpu.fpr[7]); 154 OFFSET(THREAD_FPR8, task_struct, thread.fpu.fpr[8]); 155 OFFSET(THREAD_FPR9, task_struct, thread.fpu.fpr[9]); 156 OFFSET(THREAD_FPR10, task_struct, thread.fpu.fpr[10]); 157 OFFSET(THREAD_FPR11, task_struct, thread.fpu.fpr[11]); 158 OFFSET(THREAD_FPR12, task_struct, thread.fpu.fpr[12]); 159 OFFSET(THREAD_FPR13, task_struct, thread.fpu.fpr[13]); 160 OFFSET(THREAD_FPR14, task_struct, thread.fpu.fpr[14]); 161 OFFSET(THREAD_FPR15, task_struct, thread.fpu.fpr[15]); 162 OFFSET(THREAD_FPR16, task_struct, thread.fpu.fpr[16]); 163 OFFSET(THREAD_FPR17, task_struct, thread.fpu.fpr[17]); 164 OFFSET(THREAD_FPR18, task_struct, thread.fpu.fpr[18]); 165 OFFSET(THREAD_FPR19, task_struct, thread.fpu.fpr[19]); 166 OFFSET(THREAD_FPR20, task_struct, thread.fpu.fpr[20]); 167 OFFSET(THREAD_FPR21, task_struct, thread.fpu.fpr[21]); 168 OFFSET(THREAD_FPR22, task_struct, thread.fpu.fpr[22]); 169 OFFSET(THREAD_FPR23, task_struct, thread.fpu.fpr[23]); 170 OFFSET(THREAD_FPR24, task_struct, thread.fpu.fpr[24]); 171 OFFSET(THREAD_FPR25, task_struct, thread.fpu.fpr[25]); 172 OFFSET(THREAD_FPR26, task_struct, thread.fpu.fpr[26]); 173 OFFSET(THREAD_FPR27, task_struct, thread.fpu.fpr[27]); 174 OFFSET(THREAD_FPR28, task_struct, thread.fpu.fpr[28]); 175 OFFSET(THREAD_FPR29, task_struct, thread.fpu.fpr[29]); 176 OFFSET(THREAD_FPR30, task_struct, thread.fpu.fpr[30]); 177 OFFSET(THREAD_FPR31, task_struct, thread.fpu.fpr[31]); 178 179 OFFSET(THREAD_FCR31, task_struct, thread.fpu.fcr31); 180 OFFSET(THREAD_MSA_CSR, task_struct, thread.fpu.msacsr); 181 BLANK(); 182 } 183 #endif 184 185 void output_mm_defines(void); 186 void output_mm_defines(void) 187 { 188 COMMENT("Size of struct page"); 189 DEFINE(STRUCT_PAGE_SIZE, sizeof(struct page)); 190 BLANK(); 191 COMMENT("Linux mm_struct offsets."); 192 OFFSET(MM_USERS, mm_struct, mm_users); 193 OFFSET(MM_PGD, mm_struct, pgd); 194 OFFSET(MM_CONTEXT, mm_struct, context); 195 BLANK(); 196 DEFINE(_PGD_T_SIZE, sizeof(pgd_t)); 197 DEFINE(_PMD_T_SIZE, sizeof(pmd_t)); 198 DEFINE(_PTE_T_SIZE, sizeof(pte_t)); 199 BLANK(); 200 DEFINE(_PGD_T_LOG2, PGD_T_LOG2); 201 #ifndef __PAGETABLE_PMD_FOLDED 202 DEFINE(_PMD_T_LOG2, PMD_T_LOG2); 203 #endif 204 DEFINE(_PTE_T_LOG2, PTE_T_LOG2); 205 BLANK(); 206 BLANK(); 207 DEFINE(_PMD_SHIFT, PMD_SHIFT); 208 DEFINE(_PGDIR_SHIFT, PGDIR_SHIFT); 209 BLANK(); 210 DEFINE(_PTRS_PER_PGD, PTRS_PER_PGD); 211 DEFINE(_PTRS_PER_PMD, PTRS_PER_PMD); 212 DEFINE(_PTRS_PER_PTE, PTRS_PER_PTE); 213 BLANK(); 214 DEFINE(_PAGE_SHIFT, PAGE_SHIFT); 215 DEFINE(_PAGE_SIZE, PAGE_SIZE); 216 BLANK(); 217 } 218 219 #ifdef CONFIG_32BIT 220 void output_sc_defines(void); 221 void output_sc_defines(void) 222 { 223 COMMENT("Linux sigcontext offsets."); 224 OFFSET(SC_REGS, sigcontext, sc_regs); 225 OFFSET(SC_FPREGS, sigcontext, sc_fpregs); 226 OFFSET(SC_ACX, sigcontext, sc_acx); 227 OFFSET(SC_MDHI, sigcontext, sc_mdhi); 228 OFFSET(SC_MDLO, sigcontext, sc_mdlo); 229 OFFSET(SC_PC, sigcontext, sc_pc); 230 OFFSET(SC_FPC_CSR, sigcontext, sc_fpc_csr); 231 OFFSET(SC_FPC_EIR, sigcontext, sc_fpc_eir); 232 OFFSET(SC_HI1, sigcontext, sc_hi1); 233 OFFSET(SC_LO1, sigcontext, sc_lo1); 234 OFFSET(SC_HI2, sigcontext, sc_hi2); 235 OFFSET(SC_LO2, sigcontext, sc_lo2); 236 OFFSET(SC_HI3, sigcontext, sc_hi3); 237 OFFSET(SC_LO3, sigcontext, sc_lo3); 238 BLANK(); 239 } 240 #endif 241 242 #ifdef CONFIG_64BIT 243 void output_sc_defines(void); 244 void output_sc_defines(void) 245 { 246 COMMENT("Linux sigcontext offsets."); 247 OFFSET(SC_REGS, sigcontext, sc_regs); 248 OFFSET(SC_FPREGS, sigcontext, sc_fpregs); 249 OFFSET(SC_MDHI, sigcontext, sc_mdhi); 250 OFFSET(SC_MDLO, sigcontext, sc_mdlo); 251 OFFSET(SC_PC, sigcontext, sc_pc); 252 OFFSET(SC_FPC_CSR, sigcontext, sc_fpc_csr); 253 BLANK(); 254 } 255 #endif 256 257 void output_signal_defined(void); 258 void output_signal_defined(void) 259 { 260 COMMENT("Linux signal numbers."); 261 DEFINE(_SIGHUP, SIGHUP); 262 DEFINE(_SIGINT, SIGINT); 263 DEFINE(_SIGQUIT, SIGQUIT); 264 DEFINE(_SIGILL, SIGILL); 265 DEFINE(_SIGTRAP, SIGTRAP); 266 DEFINE(_SIGIOT, SIGIOT); 267 DEFINE(_SIGABRT, SIGABRT); 268 DEFINE(_SIGEMT, SIGEMT); 269 DEFINE(_SIGFPE, SIGFPE); 270 DEFINE(_SIGKILL, SIGKILL); 271 DEFINE(_SIGBUS, SIGBUS); 272 DEFINE(_SIGSEGV, SIGSEGV); 273 DEFINE(_SIGSYS, SIGSYS); 274 DEFINE(_SIGPIPE, SIGPIPE); 275 DEFINE(_SIGALRM, SIGALRM); 276 DEFINE(_SIGTERM, SIGTERM); 277 DEFINE(_SIGUSR1, SIGUSR1); 278 DEFINE(_SIGUSR2, SIGUSR2); 279 DEFINE(_SIGCHLD, SIGCHLD); 280 DEFINE(_SIGPWR, SIGPWR); 281 DEFINE(_SIGWINCH, SIGWINCH); 282 DEFINE(_SIGURG, SIGURG); 283 DEFINE(_SIGIO, SIGIO); 284 DEFINE(_SIGSTOP, SIGSTOP); 285 DEFINE(_SIGTSTP, SIGTSTP); 286 DEFINE(_SIGCONT, SIGCONT); 287 DEFINE(_SIGTTIN, SIGTTIN); 288 DEFINE(_SIGTTOU, SIGTTOU); 289 DEFINE(_SIGVTALRM, SIGVTALRM); 290 DEFINE(_SIGPROF, SIGPROF); 291 DEFINE(_SIGXCPU, SIGXCPU); 292 DEFINE(_SIGXFSZ, SIGXFSZ); 293 BLANK(); 294 } 295 296 #ifdef CONFIG_CPU_CAVIUM_OCTEON 297 void output_octeon_cop2_state_defines(void); 298 void output_octeon_cop2_state_defines(void) 299 { 300 COMMENT("Octeon specific octeon_cop2_state offsets."); 301 OFFSET(OCTEON_CP2_CRC_IV, octeon_cop2_state, cop2_crc_iv); 302 OFFSET(OCTEON_CP2_CRC_LENGTH, octeon_cop2_state, cop2_crc_length); 303 OFFSET(OCTEON_CP2_CRC_POLY, octeon_cop2_state, cop2_crc_poly); 304 OFFSET(OCTEON_CP2_LLM_DAT, octeon_cop2_state, cop2_llm_dat); 305 OFFSET(OCTEON_CP2_3DES_IV, octeon_cop2_state, cop2_3des_iv); 306 OFFSET(OCTEON_CP2_3DES_KEY, octeon_cop2_state, cop2_3des_key); 307 OFFSET(OCTEON_CP2_3DES_RESULT, octeon_cop2_state, cop2_3des_result); 308 OFFSET(OCTEON_CP2_AES_INP0, octeon_cop2_state, cop2_aes_inp0); 309 OFFSET(OCTEON_CP2_AES_IV, octeon_cop2_state, cop2_aes_iv); 310 OFFSET(OCTEON_CP2_AES_KEY, octeon_cop2_state, cop2_aes_key); 311 OFFSET(OCTEON_CP2_AES_KEYLEN, octeon_cop2_state, cop2_aes_keylen); 312 OFFSET(OCTEON_CP2_AES_RESULT, octeon_cop2_state, cop2_aes_result); 313 OFFSET(OCTEON_CP2_GFM_MULT, octeon_cop2_state, cop2_gfm_mult); 314 OFFSET(OCTEON_CP2_GFM_POLY, octeon_cop2_state, cop2_gfm_poly); 315 OFFSET(OCTEON_CP2_GFM_RESULT, octeon_cop2_state, cop2_gfm_result); 316 OFFSET(OCTEON_CP2_HSH_DATW, octeon_cop2_state, cop2_hsh_datw); 317 OFFSET(OCTEON_CP2_HSH_IVW, octeon_cop2_state, cop2_hsh_ivw); 318 OFFSET(OCTEON_CP2_SHA3, octeon_cop2_state, cop2_sha3); 319 OFFSET(THREAD_CP2, task_struct, thread.cp2); 320 #if defined(CONFIG_CAVIUM_OCTEON_CVMSEG_SIZE) && \ 321 CONFIG_CAVIUM_OCTEON_CVMSEG_SIZE > 0 322 OFFSET(THREAD_CVMSEG, task_struct, thread.cvmseg.cvmseg); 323 #endif 324 BLANK(); 325 } 326 #endif 327 328 #ifdef CONFIG_HIBERNATION 329 void output_pbe_defines(void); 330 void output_pbe_defines(void) 331 { 332 COMMENT(" Linux struct pbe offsets. "); 333 OFFSET(PBE_ADDRESS, pbe, address); 334 OFFSET(PBE_ORIG_ADDRESS, pbe, orig_address); 335 OFFSET(PBE_NEXT, pbe, next); 336 DEFINE(PBE_SIZE, sizeof(struct pbe)); 337 BLANK(); 338 } 339 #endif 340 341 #ifdef CONFIG_CPU_PM 342 void output_pm_defines(void); 343 void output_pm_defines(void) 344 { 345 COMMENT(" PM offsets. "); 346 #ifdef CONFIG_EVA 347 OFFSET(SSS_SEGCTL0, mips_static_suspend_state, segctl[0]); 348 OFFSET(SSS_SEGCTL1, mips_static_suspend_state, segctl[1]); 349 OFFSET(SSS_SEGCTL2, mips_static_suspend_state, segctl[2]); 350 #endif 351 OFFSET(SSS_SP, mips_static_suspend_state, sp); 352 BLANK(); 353 } 354 #endif 355 356 #ifdef CONFIG_MIPS_FP_SUPPORT 357 void output_kvm_defines(void); 358 void output_kvm_defines(void) 359 { 360 COMMENT(" KVM/MIPS Specific offsets. "); 361 362 OFFSET(VCPU_FPR0, kvm_vcpu_arch, fpu.fpr[0]); 363 OFFSET(VCPU_FPR1, kvm_vcpu_arch, fpu.fpr[1]); 364 OFFSET(VCPU_FPR2, kvm_vcpu_arch, fpu.fpr[2]); 365 OFFSET(VCPU_FPR3, kvm_vcpu_arch, fpu.fpr[3]); 366 OFFSET(VCPU_FPR4, kvm_vcpu_arch, fpu.fpr[4]); 367 OFFSET(VCPU_FPR5, kvm_vcpu_arch, fpu.fpr[5]); 368 OFFSET(VCPU_FPR6, kvm_vcpu_arch, fpu.fpr[6]); 369 OFFSET(VCPU_FPR7, kvm_vcpu_arch, fpu.fpr[7]); 370 OFFSET(VCPU_FPR8, kvm_vcpu_arch, fpu.fpr[8]); 371 OFFSET(VCPU_FPR9, kvm_vcpu_arch, fpu.fpr[9]); 372 OFFSET(VCPU_FPR10, kvm_vcpu_arch, fpu.fpr[10]); 373 OFFSET(VCPU_FPR11, kvm_vcpu_arch, fpu.fpr[11]); 374 OFFSET(VCPU_FPR12, kvm_vcpu_arch, fpu.fpr[12]); 375 OFFSET(VCPU_FPR13, kvm_vcpu_arch, fpu.fpr[13]); 376 OFFSET(VCPU_FPR14, kvm_vcpu_arch, fpu.fpr[14]); 377 OFFSET(VCPU_FPR15, kvm_vcpu_arch, fpu.fpr[15]); 378 OFFSET(VCPU_FPR16, kvm_vcpu_arch, fpu.fpr[16]); 379 OFFSET(VCPU_FPR17, kvm_vcpu_arch, fpu.fpr[17]); 380 OFFSET(VCPU_FPR18, kvm_vcpu_arch, fpu.fpr[18]); 381 OFFSET(VCPU_FPR19, kvm_vcpu_arch, fpu.fpr[19]); 382 OFFSET(VCPU_FPR20, kvm_vcpu_arch, fpu.fpr[20]); 383 OFFSET(VCPU_FPR21, kvm_vcpu_arch, fpu.fpr[21]); 384 OFFSET(VCPU_FPR22, kvm_vcpu_arch, fpu.fpr[22]); 385 OFFSET(VCPU_FPR23, kvm_vcpu_arch, fpu.fpr[23]); 386 OFFSET(VCPU_FPR24, kvm_vcpu_arch, fpu.fpr[24]); 387 OFFSET(VCPU_FPR25, kvm_vcpu_arch, fpu.fpr[25]); 388 OFFSET(VCPU_FPR26, kvm_vcpu_arch, fpu.fpr[26]); 389 OFFSET(VCPU_FPR27, kvm_vcpu_arch, fpu.fpr[27]); 390 OFFSET(VCPU_FPR28, kvm_vcpu_arch, fpu.fpr[28]); 391 OFFSET(VCPU_FPR29, kvm_vcpu_arch, fpu.fpr[29]); 392 OFFSET(VCPU_FPR30, kvm_vcpu_arch, fpu.fpr[30]); 393 OFFSET(VCPU_FPR31, kvm_vcpu_arch, fpu.fpr[31]); 394 395 OFFSET(VCPU_FCR31, kvm_vcpu_arch, fpu.fcr31); 396 OFFSET(VCPU_MSA_CSR, kvm_vcpu_arch, fpu.msacsr); 397 BLANK(); 398 } 399 #endif 400 401 #ifdef CONFIG_MIPS_CPS 402 void output_cps_defines(void); 403 void output_cps_defines(void) 404 { 405 COMMENT(" MIPS CPS offsets. "); 406 407 OFFSET(COREBOOTCFG_VPEMASK, core_boot_config, vpe_mask); 408 OFFSET(COREBOOTCFG_VPECONFIG, core_boot_config, vpe_config); 409 DEFINE(COREBOOTCFG_SIZE, sizeof(struct core_boot_config)); 410 411 OFFSET(VPEBOOTCFG_PC, vpe_boot_config, pc); 412 OFFSET(VPEBOOTCFG_SP, vpe_boot_config, sp); 413 OFFSET(VPEBOOTCFG_GP, vpe_boot_config, gp); 414 DEFINE(VPEBOOTCFG_SIZE, sizeof(struct vpe_boot_config)); 415 } 416 #endif 417