1 /* 2 * This file is subject to the terms and conditions of the GNU General Public 3 * License. See the file "COPYING" in the main directory of this archive 4 * for more details. 5 * 6 * Copyright (C) 2012 MIPS Technologies, Inc. All rights reserved. 7 * Copyright (C) 2013 Cavium, Inc. 8 * Authors: Sanjay Lal <sanjayl@kymasys.com> 9 */ 10 11 #ifndef __LINUX_KVM_MIPS_H 12 #define __LINUX_KVM_MIPS_H 13 14 #include <linux/types.h> 15 16 /* 17 * KVM MIPS specific structures and definitions. 18 * 19 * Some parts derived from the x86 version of this file. 20 */ 21 22 #define __KVM_HAVE_READONLY_MEM 23 24 /* 25 * for KVM_GET_REGS and KVM_SET_REGS 26 * 27 * If Config[AT] is zero (32-bit CPU), the register contents are 28 * stored in the lower 32-bits of the struct kvm_regs fields and sign 29 * extended to 64-bits. 30 */ 31 struct kvm_regs { 32 /* out (KVM_GET_REGS) / in (KVM_SET_REGS) */ 33 __u64 gpr[32]; 34 __u64 hi; 35 __u64 lo; 36 __u64 pc; 37 }; 38 39 /* 40 * for KVM_GET_FPU and KVM_SET_FPU 41 */ 42 struct kvm_fpu { 43 }; 44 45 46 /* 47 * For MIPS, we use KVM_SET_ONE_REG and KVM_GET_ONE_REG to access various 48 * registers. The id field is broken down as follows: 49 * 50 * bits[63..52] - As per linux/kvm.h 51 * bits[51..32] - Must be zero. 52 * bits[31..16] - Register set. 53 * 54 * Register set = 0: GP registers from kvm_regs (see definitions below). 55 * 56 * Register set = 1: CP0 registers. 57 * bits[15..8] - Must be zero. 58 * bits[7..3] - Register 'rd' index. 59 * bits[2..0] - Register 'sel' index. 60 * 61 * Register set = 2: KVM specific registers (see definitions below). 62 * 63 * Register set = 3: FPU / MSA registers (see definitions below). 64 * 65 * Other sets registers may be added in the future. Each set would 66 * have its own identifier in bits[31..16]. 67 */ 68 69 #define KVM_REG_MIPS_GP (KVM_REG_MIPS | 0x0000000000000000ULL) 70 #define KVM_REG_MIPS_CP0 (KVM_REG_MIPS | 0x0000000000010000ULL) 71 #define KVM_REG_MIPS_KVM (KVM_REG_MIPS | 0x0000000000020000ULL) 72 #define KVM_REG_MIPS_FPU (KVM_REG_MIPS | 0x0000000000030000ULL) 73 74 75 /* 76 * KVM_REG_MIPS_GP - General purpose registers from kvm_regs. 77 */ 78 79 #define KVM_REG_MIPS_R0 (KVM_REG_MIPS_GP | KVM_REG_SIZE_U64 | 0) 80 #define KVM_REG_MIPS_R1 (KVM_REG_MIPS_GP | KVM_REG_SIZE_U64 | 1) 81 #define KVM_REG_MIPS_R2 (KVM_REG_MIPS_GP | KVM_REG_SIZE_U64 | 2) 82 #define KVM_REG_MIPS_R3 (KVM_REG_MIPS_GP | KVM_REG_SIZE_U64 | 3) 83 #define KVM_REG_MIPS_R4 (KVM_REG_MIPS_GP | KVM_REG_SIZE_U64 | 4) 84 #define KVM_REG_MIPS_R5 (KVM_REG_MIPS_GP | KVM_REG_SIZE_U64 | 5) 85 #define KVM_REG_MIPS_R6 (KVM_REG_MIPS_GP | KVM_REG_SIZE_U64 | 6) 86 #define KVM_REG_MIPS_R7 (KVM_REG_MIPS_GP | KVM_REG_SIZE_U64 | 7) 87 #define KVM_REG_MIPS_R8 (KVM_REG_MIPS_GP | KVM_REG_SIZE_U64 | 8) 88 #define KVM_REG_MIPS_R9 (KVM_REG_MIPS_GP | KVM_REG_SIZE_U64 | 9) 89 #define KVM_REG_MIPS_R10 (KVM_REG_MIPS_GP | KVM_REG_SIZE_U64 | 10) 90 #define KVM_REG_MIPS_R11 (KVM_REG_MIPS_GP | KVM_REG_SIZE_U64 | 11) 91 #define KVM_REG_MIPS_R12 (KVM_REG_MIPS_GP | KVM_REG_SIZE_U64 | 12) 92 #define KVM_REG_MIPS_R13 (KVM_REG_MIPS_GP | KVM_REG_SIZE_U64 | 13) 93 #define KVM_REG_MIPS_R14 (KVM_REG_MIPS_GP | KVM_REG_SIZE_U64 | 14) 94 #define KVM_REG_MIPS_R15 (KVM_REG_MIPS_GP | KVM_REG_SIZE_U64 | 15) 95 #define KVM_REG_MIPS_R16 (KVM_REG_MIPS_GP | KVM_REG_SIZE_U64 | 16) 96 #define KVM_REG_MIPS_R17 (KVM_REG_MIPS_GP | KVM_REG_SIZE_U64 | 17) 97 #define KVM_REG_MIPS_R18 (KVM_REG_MIPS_GP | KVM_REG_SIZE_U64 | 18) 98 #define KVM_REG_MIPS_R19 (KVM_REG_MIPS_GP | KVM_REG_SIZE_U64 | 19) 99 #define KVM_REG_MIPS_R20 (KVM_REG_MIPS_GP | KVM_REG_SIZE_U64 | 20) 100 #define KVM_REG_MIPS_R21 (KVM_REG_MIPS_GP | KVM_REG_SIZE_U64 | 21) 101 #define KVM_REG_MIPS_R22 (KVM_REG_MIPS_GP | KVM_REG_SIZE_U64 | 22) 102 #define KVM_REG_MIPS_R23 (KVM_REG_MIPS_GP | KVM_REG_SIZE_U64 | 23) 103 #define KVM_REG_MIPS_R24 (KVM_REG_MIPS_GP | KVM_REG_SIZE_U64 | 24) 104 #define KVM_REG_MIPS_R25 (KVM_REG_MIPS_GP | KVM_REG_SIZE_U64 | 25) 105 #define KVM_REG_MIPS_R26 (KVM_REG_MIPS_GP | KVM_REG_SIZE_U64 | 26) 106 #define KVM_REG_MIPS_R27 (KVM_REG_MIPS_GP | KVM_REG_SIZE_U64 | 27) 107 #define KVM_REG_MIPS_R28 (KVM_REG_MIPS_GP | KVM_REG_SIZE_U64 | 28) 108 #define KVM_REG_MIPS_R29 (KVM_REG_MIPS_GP | KVM_REG_SIZE_U64 | 29) 109 #define KVM_REG_MIPS_R30 (KVM_REG_MIPS_GP | KVM_REG_SIZE_U64 | 30) 110 #define KVM_REG_MIPS_R31 (KVM_REG_MIPS_GP | KVM_REG_SIZE_U64 | 31) 111 112 #define KVM_REG_MIPS_HI (KVM_REG_MIPS_GP | KVM_REG_SIZE_U64 | 32) 113 #define KVM_REG_MIPS_LO (KVM_REG_MIPS_GP | KVM_REG_SIZE_U64 | 33) 114 #define KVM_REG_MIPS_PC (KVM_REG_MIPS_GP | KVM_REG_SIZE_U64 | 34) 115 116 117 /* 118 * KVM_REG_MIPS_KVM - KVM specific control registers. 119 */ 120 121 /* 122 * CP0_Count control 123 * DC: Set 0: Master disable CP0_Count and set COUNT_RESUME to now 124 * Set 1: Master re-enable CP0_Count with unchanged bias, handling timer 125 * interrupts since COUNT_RESUME 126 * This can be used to freeze the timer to get a consistent snapshot of 127 * the CP0_Count and timer interrupt pending state, while also resuming 128 * safely without losing time or guest timer interrupts. 129 * Other: Reserved, do not change. 130 */ 131 #define KVM_REG_MIPS_COUNT_CTL (KVM_REG_MIPS_KVM | KVM_REG_SIZE_U64 | 0) 132 #define KVM_REG_MIPS_COUNT_CTL_DC 0x00000001 133 134 /* 135 * CP0_Count resume monotonic nanoseconds 136 * The monotonic nanosecond time of the last set of COUNT_CTL.DC (master 137 * disable). Any reads and writes of Count related registers while 138 * COUNT_CTL.DC=1 will appear to occur at this time. When COUNT_CTL.DC is 139 * cleared again (master enable) any timer interrupts since this time will be 140 * emulated. 141 * Modifications to times in the future are rejected. 142 */ 143 #define KVM_REG_MIPS_COUNT_RESUME (KVM_REG_MIPS_KVM | KVM_REG_SIZE_U64 | 1) 144 /* 145 * CP0_Count rate in Hz 146 * Specifies the rate of the CP0_Count timer in Hz. Modifications occur without 147 * discontinuities in CP0_Count. 148 */ 149 #define KVM_REG_MIPS_COUNT_HZ (KVM_REG_MIPS_KVM | KVM_REG_SIZE_U64 | 2) 150 151 152 /* 153 * KVM_REG_MIPS_FPU - Floating Point and MIPS SIMD Architecture (MSA) registers. 154 * 155 * bits[15..8] - Register subset (see definitions below). 156 * bits[7..5] - Must be zero. 157 * bits[4..0] - Register number within register subset. 158 */ 159 160 #define KVM_REG_MIPS_FPR (KVM_REG_MIPS_FPU | 0x0000000000000000ULL) 161 #define KVM_REG_MIPS_FCR (KVM_REG_MIPS_FPU | 0x0000000000000100ULL) 162 #define KVM_REG_MIPS_MSACR (KVM_REG_MIPS_FPU | 0x0000000000000200ULL) 163 164 /* 165 * KVM_REG_MIPS_FPR - Floating point / Vector registers. 166 */ 167 #define KVM_REG_MIPS_FPR_32(n) (KVM_REG_MIPS_FPR | KVM_REG_SIZE_U32 | (n)) 168 #define KVM_REG_MIPS_FPR_64(n) (KVM_REG_MIPS_FPR | KVM_REG_SIZE_U64 | (n)) 169 #define KVM_REG_MIPS_VEC_128(n) (KVM_REG_MIPS_FPR | KVM_REG_SIZE_U128 | (n)) 170 171 /* 172 * KVM_REG_MIPS_FCR - Floating point control registers. 173 */ 174 #define KVM_REG_MIPS_FCR_IR (KVM_REG_MIPS_FCR | KVM_REG_SIZE_U32 | 0) 175 #define KVM_REG_MIPS_FCR_CSR (KVM_REG_MIPS_FCR | KVM_REG_SIZE_U32 | 31) 176 177 /* 178 * KVM_REG_MIPS_MSACR - MIPS SIMD Architecture (MSA) control registers. 179 */ 180 #define KVM_REG_MIPS_MSA_IR (KVM_REG_MIPS_MSACR | KVM_REG_SIZE_U32 | 0) 181 #define KVM_REG_MIPS_MSA_CSR (KVM_REG_MIPS_MSACR | KVM_REG_SIZE_U32 | 1) 182 183 184 /* 185 * KVM MIPS specific structures and definitions 186 * 187 */ 188 struct kvm_debug_exit_arch { 189 __u64 epc; 190 }; 191 192 /* for KVM_SET_GUEST_DEBUG */ 193 struct kvm_guest_debug_arch { 194 }; 195 196 /* definition of registers in kvm_run */ 197 struct kvm_sync_regs { 198 }; 199 200 /* dummy definition */ 201 struct kvm_sregs { 202 }; 203 204 struct kvm_mips_interrupt { 205 /* in */ 206 __u32 cpu; 207 __u32 irq; 208 }; 209 210 #endif /* __LINUX_KVM_MIPS_H */ 211