1 /* 2 * include/asm-mips/txx9/tx4927pcic.h 3 * TX4927 PCI controller definitions. 4 * 5 * This file is subject to the terms and conditions of the GNU General Public 6 * License. See the file "COPYING" in the main directory of this archive 7 * for more details. 8 */ 9 #ifndef __ASM_TXX9_TX4927PCIC_H 10 #define __ASM_TXX9_TX4927PCIC_H 11 12 #include <linux/pci.h> 13 #include <linux/irqreturn.h> 14 15 struct tx4927_pcic_reg { 16 u32 pciid; 17 u32 pcistatus; 18 u32 pciccrev; 19 u32 pcicfg1; 20 u32 p2gm0plbase; /* +10 */ 21 u32 p2gm0pubase; 22 u32 p2gm1plbase; 23 u32 p2gm1pubase; 24 u32 p2gm2pbase; /* +20 */ 25 u32 p2giopbase; 26 u32 unused0; 27 u32 pcisid; 28 u32 unused1; /* +30 */ 29 u32 pcicapptr; 30 u32 unused2; 31 u32 pcicfg2; 32 u32 g2ptocnt; /* +40 */ 33 u32 unused3[15]; 34 u32 g2pstatus; /* +80 */ 35 u32 g2pmask; 36 u32 pcisstatus; 37 u32 pcimask; 38 u32 p2gcfg; /* +90 */ 39 u32 p2gstatus; 40 u32 p2gmask; 41 u32 p2gccmd; 42 u32 unused4[24]; /* +a0 */ 43 u32 pbareqport; /* +100 */ 44 u32 pbacfg; 45 u32 pbastatus; 46 u32 pbamask; 47 u32 pbabm; /* +110 */ 48 u32 pbacreq; 49 u32 pbacgnt; 50 u32 pbacstate; 51 u64 g2pmgbase[3]; /* +120 */ 52 u64 g2piogbase; 53 u32 g2pmmask[3]; /* +140 */ 54 u32 g2piomask; 55 u64 g2pmpbase[3]; /* +150 */ 56 u64 g2piopbase; 57 u32 pciccfg; /* +170 */ 58 u32 pcicstatus; 59 u32 pcicmask; 60 u32 unused5; 61 u64 p2gmgbase[3]; /* +180 */ 62 u64 p2giogbase; 63 u32 g2pcfgadrs; /* +1a0 */ 64 u32 g2pcfgdata; 65 u32 unused6[8]; 66 u32 g2pintack; 67 u32 g2pspc; 68 u32 unused7[12]; /* +1d0 */ 69 u64 pdmca; /* +200 */ 70 u64 pdmga; 71 u64 pdmpa; 72 u64 pdmctr; 73 u64 pdmcfg; /* +220 */ 74 u64 pdmsts; 75 }; 76 77 /* bits for PCICMD */ 78 /* see PCI_COMMAND_XXX in linux/pci_regs.h */ 79 80 /* bits for PCISTAT */ 81 /* see PCI_STATUS_XXX in linux/pci_regs.h */ 82 83 /* bits for IOBA/MBA */ 84 /* see PCI_BASE_ADDRESS_XXX in linux/pci_regs.h */ 85 86 /* bits for G2PSTATUS/G2PMASK */ 87 #define TX4927_PCIC_G2PSTATUS_ALL 0x00000003 88 #define TX4927_PCIC_G2PSTATUS_TTOE 0x00000002 89 #define TX4927_PCIC_G2PSTATUS_RTOE 0x00000001 90 91 /* bits for PCIMASK (see also PCI_STATUS_XXX in linux/pci_regs.h */ 92 #define TX4927_PCIC_PCISTATUS_ALL 0x0000f900 93 94 /* bits for PBACFG */ 95 #define TX4927_PCIC_PBACFG_FIXPA 0x00000008 96 #define TX4927_PCIC_PBACFG_RPBA 0x00000004 97 #define TX4927_PCIC_PBACFG_PBAEN 0x00000002 98 #define TX4927_PCIC_PBACFG_BMCEN 0x00000001 99 100 /* bits for PBASTATUS/PBAMASK */ 101 #define TX4927_PCIC_PBASTATUS_ALL 0x00000001 102 #define TX4927_PCIC_PBASTATUS_BM 0x00000001 103 104 /* bits for G2PMnGBASE */ 105 #define TX4927_PCIC_G2PMnGBASE_BSDIS 0x0000002000000000ULL 106 #define TX4927_PCIC_G2PMnGBASE_ECHG 0x0000001000000000ULL 107 108 /* bits for G2PIOGBASE */ 109 #define TX4927_PCIC_G2PIOGBASE_BSDIS 0x0000002000000000ULL 110 #define TX4927_PCIC_G2PIOGBASE_ECHG 0x0000001000000000ULL 111 112 /* bits for PCICSTATUS/PCICMASK */ 113 #define TX4927_PCIC_PCICSTATUS_ALL 0x000007b8 114 #define TX4927_PCIC_PCICSTATUS_PME 0x00000400 115 #define TX4927_PCIC_PCICSTATUS_TLB 0x00000200 116 #define TX4927_PCIC_PCICSTATUS_NIB 0x00000100 117 #define TX4927_PCIC_PCICSTATUS_ZIB 0x00000080 118 #define TX4927_PCIC_PCICSTATUS_PERR 0x00000020 119 #define TX4927_PCIC_PCICSTATUS_SERR 0x00000010 120 #define TX4927_PCIC_PCICSTATUS_GBE 0x00000008 121 #define TX4927_PCIC_PCICSTATUS_IWB 0x00000002 122 #define TX4927_PCIC_PCICSTATUS_E2PDONE 0x00000001 123 124 /* bits for PCICCFG */ 125 #define TX4927_PCIC_PCICCFG_GBWC_MASK 0x0fff0000 126 #define TX4927_PCIC_PCICCFG_HRST 0x00000800 127 #define TX4927_PCIC_PCICCFG_SRST 0x00000400 128 #define TX4927_PCIC_PCICCFG_IRBER 0x00000200 129 #define TX4927_PCIC_PCICCFG_G2PMEN(ch) (0x00000100>>(ch)) 130 #define TX4927_PCIC_PCICCFG_G2PM0EN 0x00000100 131 #define TX4927_PCIC_PCICCFG_G2PM1EN 0x00000080 132 #define TX4927_PCIC_PCICCFG_G2PM2EN 0x00000040 133 #define TX4927_PCIC_PCICCFG_G2PIOEN 0x00000020 134 #define TX4927_PCIC_PCICCFG_TCAR 0x00000010 135 #define TX4927_PCIC_PCICCFG_ICAEN 0x00000008 136 137 /* bits for P2GMnGBASE */ 138 #define TX4927_PCIC_P2GMnGBASE_TMEMEN 0x0000004000000000ULL 139 #define TX4927_PCIC_P2GMnGBASE_TBSDIS 0x0000002000000000ULL 140 #define TX4927_PCIC_P2GMnGBASE_TECHG 0x0000001000000000ULL 141 142 /* bits for P2GIOGBASE */ 143 #define TX4927_PCIC_P2GIOGBASE_TIOEN 0x0000004000000000ULL 144 #define TX4927_PCIC_P2GIOGBASE_TBSDIS 0x0000002000000000ULL 145 #define TX4927_PCIC_P2GIOGBASE_TECHG 0x0000001000000000ULL 146 147 #define TX4927_PCIC_IDSEL_AD_TO_SLOT(ad) ((ad) - 11) 148 #define TX4927_PCIC_MAX_DEVNU TX4927_PCIC_IDSEL_AD_TO_SLOT(32) 149 150 /* bits for PDMCFG */ 151 #define TX4927_PCIC_PDMCFG_RSTFIFO 0x00200000 152 #define TX4927_PCIC_PDMCFG_EXFER 0x00100000 153 #define TX4927_PCIC_PDMCFG_REQDLY_MASK 0x00003800 154 #define TX4927_PCIC_PDMCFG_REQDLY_NONE (0 << 11) 155 #define TX4927_PCIC_PDMCFG_REQDLY_16 (1 << 11) 156 #define TX4927_PCIC_PDMCFG_REQDLY_32 (2 << 11) 157 #define TX4927_PCIC_PDMCFG_REQDLY_64 (3 << 11) 158 #define TX4927_PCIC_PDMCFG_REQDLY_128 (4 << 11) 159 #define TX4927_PCIC_PDMCFG_REQDLY_256 (5 << 11) 160 #define TX4927_PCIC_PDMCFG_REQDLY_512 (6 << 11) 161 #define TX4927_PCIC_PDMCFG_REQDLY_1024 (7 << 11) 162 #define TX4927_PCIC_PDMCFG_ERRIE 0x00000400 163 #define TX4927_PCIC_PDMCFG_NCCMPIE 0x00000200 164 #define TX4927_PCIC_PDMCFG_NTCMPIE 0x00000100 165 #define TX4927_PCIC_PDMCFG_CHNEN 0x00000080 166 #define TX4927_PCIC_PDMCFG_XFRACT 0x00000040 167 #define TX4927_PCIC_PDMCFG_BSWAP 0x00000020 168 #define TX4927_PCIC_PDMCFG_XFRSIZE_MASK 0x0000000c 169 #define TX4927_PCIC_PDMCFG_XFRSIZE_1DW 0x00000000 170 #define TX4927_PCIC_PDMCFG_XFRSIZE_1QW 0x00000004 171 #define TX4927_PCIC_PDMCFG_XFRSIZE_4QW 0x00000008 172 #define TX4927_PCIC_PDMCFG_XFRDIRC 0x00000002 173 #define TX4927_PCIC_PDMCFG_CHRST 0x00000001 174 175 /* bits for PDMSTS */ 176 #define TX4927_PCIC_PDMSTS_REQCNT_MASK 0x3f000000 177 #define TX4927_PCIC_PDMSTS_FIFOCNT_MASK 0x00f00000 178 #define TX4927_PCIC_PDMSTS_FIFOWP_MASK 0x000c0000 179 #define TX4927_PCIC_PDMSTS_FIFORP_MASK 0x00030000 180 #define TX4927_PCIC_PDMSTS_ERRINT 0x00000800 181 #define TX4927_PCIC_PDMSTS_DONEINT 0x00000400 182 #define TX4927_PCIC_PDMSTS_CHNEN 0x00000200 183 #define TX4927_PCIC_PDMSTS_XFRACT 0x00000100 184 #define TX4927_PCIC_PDMSTS_ACCMP 0x00000080 185 #define TX4927_PCIC_PDMSTS_NCCMP 0x00000040 186 #define TX4927_PCIC_PDMSTS_NTCMP 0x00000020 187 #define TX4927_PCIC_PDMSTS_CFGERR 0x00000008 188 #define TX4927_PCIC_PDMSTS_PCIERR 0x00000004 189 #define TX4927_PCIC_PDMSTS_CHNERR 0x00000002 190 #define TX4927_PCIC_PDMSTS_DATAERR 0x00000001 191 #define TX4927_PCIC_PDMSTS_ALL_CMP 0x000000e0 192 #define TX4927_PCIC_PDMSTS_ALL_ERR 0x0000000f 193 194 struct tx4927_pcic_reg __iomem *get_tx4927_pcicptr( 195 struct pci_controller *channel); 196 void tx4927_pcic_setup(struct tx4927_pcic_reg __iomem *pcicptr, 197 struct pci_controller *channel, int extarb); 198 void tx4927_report_pcic_status(void); 199 char *tx4927_pcibios_setup(char *str); 200 void tx4927_dump_pcic_settings(void); 201 irqreturn_t tx4927_pcierr_interrupt(int irq, void *dev_id); 202 203 #endif /* __ASM_TXX9_TX4927PCIC_H */ 204