1 /* 2 * Author: MontaVista Software, Inc. 3 * source@mvista.com 4 * 5 * Copyright 2001-2006 MontaVista Software Inc. 6 * 7 * This program is free software; you can redistribute it and/or modify it 8 * under the terms of the GNU General Public License as published by the 9 * Free Software Foundation; either version 2 of the License, or (at your 10 * option) any later version. 11 * 12 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED 13 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 14 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 15 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 16 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 17 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS 18 * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND 19 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR 20 * TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE 21 * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 22 * 23 * You should have received a copy of the GNU General Public License along 24 * with this program; if not, write to the Free Software Foundation, Inc., 25 * 675 Mass Ave, Cambridge, MA 02139, USA. 26 */ 27 #ifndef __ASM_TXX9_TX4927_H 28 #define __ASM_TXX9_TX4927_H 29 30 #include <linux/types.h> 31 #include <linux/io.h> 32 #include <asm/txx9irq.h> 33 #include <asm/txx9/tx4927pcic.h> 34 35 #ifdef CONFIG_64BIT 36 #define TX4927_REG_BASE 0xffffffffff1f0000UL 37 #else 38 #define TX4927_REG_BASE 0xff1f0000UL 39 #endif 40 #define TX4927_REG_SIZE 0x00010000 41 42 #define TX4927_SDRAMC_REG (TX4927_REG_BASE + 0x8000) 43 #define TX4927_EBUSC_REG (TX4927_REG_BASE + 0x9000) 44 #define TX4927_DMA_REG (TX4927_REG_BASE + 0xb000) 45 #define TX4927_PCIC_REG (TX4927_REG_BASE + 0xd000) 46 #define TX4927_CCFG_REG (TX4927_REG_BASE + 0xe000) 47 #define TX4927_IRC_REG (TX4927_REG_BASE + 0xf600) 48 #define TX4927_NR_TMR 3 49 #define TX4927_TMR_REG(ch) (TX4927_REG_BASE + 0xf000 + (ch) * 0x100) 50 #define TX4927_NR_SIO 2 51 #define TX4927_SIO_REG(ch) (TX4927_REG_BASE + 0xf300 + (ch) * 0x100) 52 #define TX4927_PIO_REG (TX4927_REG_BASE + 0xf500) 53 54 #define TX4927_IR_ECCERR 0 55 #define TX4927_IR_WTOERR 1 56 #define TX4927_NUM_IR_INT 6 57 #define TX4927_IR_INT(n) (2 + (n)) 58 #define TX4927_NUM_IR_SIO 2 59 #define TX4927_IR_SIO(n) (8 + (n)) 60 #define TX4927_NUM_IR_DMA 4 61 #define TX4927_IR_DMA(n) (10 + (n)) 62 #define TX4927_IR_PIO 14 63 #define TX4927_IR_PDMAC 15 64 #define TX4927_IR_PCIC 16 65 #define TX4927_NUM_IR_TMR 3 66 #define TX4927_IR_TMR(n) (17 + (n)) 67 #define TX4927_IR_PCIERR 22 68 #define TX4927_IR_PCIPME 23 69 #define TX4927_IR_ACLC 24 70 #define TX4927_IR_ACLCPME 25 71 #define TX4927_NUM_IR 32 72 73 #define TX4927_IRC_INT 2 /* IP[2] in Status register */ 74 75 #define TX4927_NUM_PIO 16 76 77 struct tx4927_sdramc_reg { 78 u64 cr[4]; 79 u64 unused0[4]; 80 u64 tr; 81 u64 unused1[2]; 82 u64 cmd; 83 }; 84 85 struct tx4927_ebusc_reg { 86 u64 cr[8]; 87 }; 88 89 struct tx4927_ccfg_reg { 90 u64 ccfg; 91 u64 crir; 92 u64 pcfg; 93 u64 toea; 94 u64 clkctr; 95 u64 unused0; 96 u64 garbc; 97 u64 unused1; 98 u64 unused2; 99 u64 ramp; 100 }; 101 102 /* 103 * CCFG 104 */ 105 /* CCFG : Chip Configuration */ 106 #define TX4927_CCFG_WDRST 0x0000020000000000ULL 107 #define TX4927_CCFG_WDREXEN 0x0000010000000000ULL 108 #define TX4927_CCFG_BCFG_MASK 0x000000ff00000000ULL 109 #define TX4927_CCFG_TINTDIS 0x01000000 110 #define TX4927_CCFG_PCI66 0x00800000 111 #define TX4927_CCFG_PCIMODE 0x00400000 112 #define TX4927_CCFG_DIVMODE_MASK 0x000e0000 113 #define TX4927_CCFG_DIVMODE_8 (0x0 << 17) 114 #define TX4927_CCFG_DIVMODE_12 (0x1 << 17) 115 #define TX4927_CCFG_DIVMODE_16 (0x2 << 17) 116 #define TX4927_CCFG_DIVMODE_10 (0x3 << 17) 117 #define TX4927_CCFG_DIVMODE_2 (0x4 << 17) 118 #define TX4927_CCFG_DIVMODE_3 (0x5 << 17) 119 #define TX4927_CCFG_DIVMODE_4 (0x6 << 17) 120 #define TX4927_CCFG_DIVMODE_2_5 (0x7 << 17) 121 #define TX4927_CCFG_BEOW 0x00010000 122 #define TX4927_CCFG_WR 0x00008000 123 #define TX4927_CCFG_TOE 0x00004000 124 #define TX4927_CCFG_PCIARB 0x00002000 125 #define TX4927_CCFG_PCIDIVMODE_MASK 0x00001800 126 #define TX4927_CCFG_PCIDIVMODE_2_5 0x00000000 127 #define TX4927_CCFG_PCIDIVMODE_3 0x00000800 128 #define TX4927_CCFG_PCIDIVMODE_5 0x00001000 129 #define TX4927_CCFG_PCIDIVMODE_6 0x00001800 130 #define TX4927_CCFG_SYSSP_MASK 0x000000c0 131 #define TX4927_CCFG_ENDIAN 0x00000004 132 #define TX4927_CCFG_HALT 0x00000002 133 #define TX4927_CCFG_ACEHOLD 0x00000001 134 #define TX4927_CCFG_W1CBITS (TX4927_CCFG_WDRST | TX4927_CCFG_BEOW) 135 136 /* PCFG : Pin Configuration */ 137 #define TX4927_PCFG_SDCLKDLY_MASK 0x30000000 138 #define TX4927_PCFG_SDCLKDLY(d) ((d)<<28) 139 #define TX4927_PCFG_SYSCLKEN 0x08000000 140 #define TX4927_PCFG_SDCLKEN_ALL 0x07800000 141 #define TX4927_PCFG_SDCLKEN(ch) (0x00800000<<(ch)) 142 #define TX4927_PCFG_PCICLKEN_ALL 0x003f0000 143 #define TX4927_PCFG_PCICLKEN(ch) (0x00010000<<(ch)) 144 #define TX4927_PCFG_SEL2 0x00000200 145 #define TX4927_PCFG_SEL1 0x00000100 146 #define TX4927_PCFG_DMASEL_ALL 0x000000ff 147 #define TX4927_PCFG_DMASEL0_MASK 0x00000003 148 #define TX4927_PCFG_DMASEL1_MASK 0x0000000c 149 #define TX4927_PCFG_DMASEL2_MASK 0x00000030 150 #define TX4927_PCFG_DMASEL3_MASK 0x000000c0 151 #define TX4927_PCFG_DMASEL0_DRQ0 0x00000000 152 #define TX4927_PCFG_DMASEL0_SIO1 0x00000001 153 #define TX4927_PCFG_DMASEL0_ACL0 0x00000002 154 #define TX4927_PCFG_DMASEL0_ACL2 0x00000003 155 #define TX4927_PCFG_DMASEL1_DRQ1 0x00000000 156 #define TX4927_PCFG_DMASEL1_SIO1 0x00000004 157 #define TX4927_PCFG_DMASEL1_ACL1 0x00000008 158 #define TX4927_PCFG_DMASEL1_ACL3 0x0000000c 159 #define TX4927_PCFG_DMASEL2_DRQ2 0x00000000 /* SEL2=0 */ 160 #define TX4927_PCFG_DMASEL2_SIO0 0x00000010 /* SEL2=0 */ 161 #define TX4927_PCFG_DMASEL2_ACL1 0x00000000 /* SEL2=1 */ 162 #define TX4927_PCFG_DMASEL2_ACL2 0x00000020 /* SEL2=1 */ 163 #define TX4927_PCFG_DMASEL2_ACL0 0x00000030 /* SEL2=1 */ 164 #define TX4927_PCFG_DMASEL3_DRQ3 0x00000000 165 #define TX4927_PCFG_DMASEL3_SIO0 0x00000040 166 #define TX4927_PCFG_DMASEL3_ACL3 0x00000080 167 #define TX4927_PCFG_DMASEL3_ACL1 0x000000c0 168 169 /* CLKCTR : Clock Control */ 170 #define TX4927_CLKCTR_ACLCKD 0x02000000 171 #define TX4927_CLKCTR_PIOCKD 0x01000000 172 #define TX4927_CLKCTR_DMACKD 0x00800000 173 #define TX4927_CLKCTR_PCICKD 0x00400000 174 #define TX4927_CLKCTR_TM0CKD 0x00100000 175 #define TX4927_CLKCTR_TM1CKD 0x00080000 176 #define TX4927_CLKCTR_TM2CKD 0x00040000 177 #define TX4927_CLKCTR_SIO0CKD 0x00020000 178 #define TX4927_CLKCTR_SIO1CKD 0x00010000 179 #define TX4927_CLKCTR_ACLRST 0x00000200 180 #define TX4927_CLKCTR_PIORST 0x00000100 181 #define TX4927_CLKCTR_DMARST 0x00000080 182 #define TX4927_CLKCTR_PCIRST 0x00000040 183 #define TX4927_CLKCTR_TM0RST 0x00000010 184 #define TX4927_CLKCTR_TM1RST 0x00000008 185 #define TX4927_CLKCTR_TM2RST 0x00000004 186 #define TX4927_CLKCTR_SIO0RST 0x00000002 187 #define TX4927_CLKCTR_SIO1RST 0x00000001 188 189 #define tx4927_sdramcptr \ 190 ((struct tx4927_sdramc_reg __iomem *)TX4927_SDRAMC_REG) 191 #define tx4927_pcicptr \ 192 ((struct tx4927_pcic_reg __iomem *)TX4927_PCIC_REG) 193 #define tx4927_ccfgptr \ 194 ((struct tx4927_ccfg_reg __iomem *)TX4927_CCFG_REG) 195 #define tx4927_ebuscptr \ 196 ((struct tx4927_ebusc_reg __iomem *)TX4927_EBUSC_REG) 197 #define tx4927_pioptr ((struct txx9_pio_reg __iomem *)TX4927_PIO_REG) 198 199 #define TX4927_REV_PCODE() \ 200 ((__u32)__raw_readq(&tx4927_ccfgptr->crir) >> 16) 201 202 #define TX4927_SDRAMC_CR(ch) __raw_readq(&tx4927_sdramcptr->cr[(ch)]) 203 #define TX4927_SDRAMC_BA(ch) ((TX4927_SDRAMC_CR(ch) >> 49) << 21) 204 #define TX4927_SDRAMC_SIZE(ch) \ 205 ((((TX4927_SDRAMC_CR(ch) >> 33) & 0x7fff) + 1) << 21) 206 207 #define TX4927_EBUSC_CR(ch) __raw_readq(&tx4927_ebuscptr->cr[(ch)]) 208 #define TX4927_EBUSC_BA(ch) ((TX4927_EBUSC_CR(ch) >> 48) << 20) 209 #define TX4927_EBUSC_SIZE(ch) \ 210 (0x00100000 << ((unsigned long)(TX4927_EBUSC_CR(ch) >> 8) & 0xf)) 211 #define TX4927_EBUSC_WIDTH(ch) \ 212 (64 >> ((__u32)(TX4927_EBUSC_CR(ch) >> 20) & 0x3)) 213 214 /* utilities */ 215 static inline void txx9_clear64(__u64 __iomem *adr, __u64 bits) 216 { 217 #ifdef CONFIG_32BIT 218 unsigned long flags; 219 local_irq_save(flags); 220 #endif 221 ____raw_writeq(____raw_readq(adr) & ~bits, adr); 222 #ifdef CONFIG_32BIT 223 local_irq_restore(flags); 224 #endif 225 } 226 static inline void txx9_set64(__u64 __iomem *adr, __u64 bits) 227 { 228 #ifdef CONFIG_32BIT 229 unsigned long flags; 230 local_irq_save(flags); 231 #endif 232 ____raw_writeq(____raw_readq(adr) | bits, adr); 233 #ifdef CONFIG_32BIT 234 local_irq_restore(flags); 235 #endif 236 } 237 238 /* These functions are not interrupt safe. */ 239 static inline void tx4927_ccfg_clear(__u64 bits) 240 { 241 ____raw_writeq(____raw_readq(&tx4927_ccfgptr->ccfg) 242 & ~(TX4927_CCFG_W1CBITS | bits), 243 &tx4927_ccfgptr->ccfg); 244 } 245 static inline void tx4927_ccfg_set(__u64 bits) 246 { 247 ____raw_writeq((____raw_readq(&tx4927_ccfgptr->ccfg) 248 & ~TX4927_CCFG_W1CBITS) | bits, 249 &tx4927_ccfgptr->ccfg); 250 } 251 static inline void tx4927_ccfg_change(__u64 change, __u64 new) 252 { 253 ____raw_writeq((____raw_readq(&tx4927_ccfgptr->ccfg) 254 & ~(TX4927_CCFG_W1CBITS | change)) | 255 new, 256 &tx4927_ccfgptr->ccfg); 257 } 258 259 unsigned int tx4927_get_mem_size(void); 260 void tx4927_wdt_init(void); 261 void tx4927_setup(void); 262 void tx4927_time_init(unsigned int tmrnr); 263 void tx4927_sio_init(unsigned int sclk, unsigned int cts_mask); 264 int tx4927_report_pciclk(void); 265 int tx4927_pciclk66_setup(void); 266 void tx4927_setup_pcierr_irq(void); 267 void tx4927_irq_init(void); 268 void tx4927_mtd_init(int ch); 269 void tx4927_dmac_init(int memcpy_chan); 270 271 #endif /* __ASM_TXX9_TX4927_H */ 272