1 /* 2 * This file is subject to the terms and conditions of the GNU General Public 3 * License. See the file "COPYING" in the main directory of this archive 4 * for more details. 5 * 6 * Derived from IRIX <sys/SN/SN0/addrs.h>, revision 1.126. 7 * 8 * Copyright (C) 1992 - 1997, 1999 Silicon Graphics, Inc. 9 * Copyright (C) 1999 by Ralf Baechle 10 */ 11 #ifndef _ASM_SN_SN0_ADDRS_H 12 #define _ASM_SN_SN0_ADDRS_H 13 14 15 /* 16 * SN0 (on a T5) Address map 17 * 18 * This file contains a set of definitions and macros which are used 19 * to reference into the major address spaces (CAC, HSPEC, IO, MSPEC, 20 * and UNCAC) used by the SN0 architecture. It also contains addresses 21 * for "major" statically locatable PROM/Kernel data structures, such as 22 * the partition table, the configuration data structure, etc. 23 * We make an implicit assumption that the processor using this file 24 * follows the R10K's provisions for specifying uncached attributes; 25 * should this change, the base registers may very well become processor- 26 * dependent. 27 * 28 * For more information on the address spaces, see the "Local Resources" 29 * chapter of the Hub specification. 30 * 31 * NOTE: This header file is included both by C and by assembler source 32 * files. Please bracket any language-dependent definitions 33 * appropriately. 34 */ 35 36 /* 37 * Some of the macros here need to be casted to appropriate types when used 38 * from C. They definitely must not be casted from assembly language so we 39 * use some new ANSI preprocessor stuff to paste these on where needed. 40 */ 41 42 /* 43 * The following couple of definitions will eventually need to be variables, 44 * since the amount of address space assigned to each node depends on 45 * whether the system is running in N-mode (more nodes with less memory) 46 * or M-mode (fewer nodes with more memory). We expect that it will 47 * be a while before we need to make this decision dynamically, though, 48 * so for now we just use defines bracketed by an ifdef. 49 */ 50 51 #ifdef CONFIG_SGI_SN_N_MODE 52 53 #define NODE_SIZE_BITS 31 54 #define BWIN_SIZE_BITS 28 55 56 #define NASID_BITS 9 57 #define NASID_BITMASK (0x1ffLL) 58 #define NASID_SHFT 31 59 #define NASID_META_BITS 5 60 #define NASID_LOCAL_BITS 4 61 62 #define BDDIR_UPPER_MASK (UINT64_CAST 0x7ffff << 10) 63 #define BDECC_UPPER_MASK (UINT64_CAST 0x3ffffff << 3) 64 65 #else /* !defined(CONFIG_SGI_SN_N_MODE), assume that M-mode is desired */ 66 67 #define NODE_SIZE_BITS 32 68 #define BWIN_SIZE_BITS 29 69 70 #define NASID_BITMASK (0xffLL) 71 #define NASID_BITS 8 72 #define NASID_SHFT 32 73 #define NASID_META_BITS 4 74 #define NASID_LOCAL_BITS 4 75 76 #define BDDIR_UPPER_MASK (UINT64_CAST 0xfffff << 10) 77 #define BDECC_UPPER_MASK (UINT64_CAST 0x7ffffff << 3) 78 79 #endif /* !defined(CONFIG_SGI_SN_N_MODE) */ 80 81 #define NODE_ADDRSPACE_SIZE (UINT64_CAST 1 << NODE_SIZE_BITS) 82 83 #define NASID_MASK (UINT64_CAST NASID_BITMASK << NASID_SHFT) 84 #define NASID_GET(_pa) (int) ((UINT64_CAST (_pa) >> \ 85 NASID_SHFT) & NASID_BITMASK) 86 87 #if !defined(__ASSEMBLY__) 88 89 #define NODE_SWIN_BASE(nasid, widget) \ 90 ((widget == 0) ? NODE_BWIN_BASE((nasid), SWIN0_BIGWIN) \ 91 : RAW_NODE_SWIN_BASE(nasid, widget)) 92 #else /* __ASSEMBLY__ */ 93 #define NODE_SWIN_BASE(nasid, widget) \ 94 (NODE_IO_BASE(nasid) + (UINT64_CAST(widget) << SWIN_SIZE_BITS)) 95 #endif /* __ASSEMBLY__ */ 96 97 /* 98 * The following definitions pertain to the IO special address 99 * space. They define the location of the big and little windows 100 * of any given node. 101 */ 102 103 #define BWIN_INDEX_BITS 3 104 #define BWIN_SIZE (UINT64_CAST 1 << BWIN_SIZE_BITS) 105 #define BWIN_SIZEMASK (BWIN_SIZE - 1) 106 #define BWIN_WIDGET_MASK 0x7 107 #define NODE_BWIN_BASE0(nasid) (NODE_IO_BASE(nasid) + BWIN_SIZE) 108 #define NODE_BWIN_BASE(nasid, bigwin) (NODE_BWIN_BASE0(nasid) + \ 109 (UINT64_CAST(bigwin) << BWIN_SIZE_BITS)) 110 111 #define BWIN_WIDGETADDR(addr) ((addr) & BWIN_SIZEMASK) 112 #define BWIN_WINDOWNUM(addr) (((addr) >> BWIN_SIZE_BITS) & BWIN_WIDGET_MASK) 113 /* 114 * Verify if addr belongs to large window address of node with "nasid" 115 * 116 * 117 * NOTE: "addr" is expected to be XKPHYS address, and NOT physical 118 * address 119 * 120 * 121 */ 122 123 #define NODE_BWIN_ADDR(nasid, addr) \ 124 (((addr) >= NODE_BWIN_BASE0(nasid)) && \ 125 ((addr) < (NODE_BWIN_BASE(nasid, HUB_NUM_BIG_WINDOW) + \ 126 BWIN_SIZE))) 127 128 /* 129 * The following define the major position-independent aliases used 130 * in SN0. 131 * CALIAS -- Varies in size, points to the first n bytes of memory 132 * on the reader's node. 133 */ 134 135 #define CALIAS_BASE CAC_BASE 136 137 138 139 #define BRIDGE_REG_PTR(_base, _off) ((volatile bridgereg_t *) \ 140 ((__psunsigned_t)(_base) + (__psunsigned_t)(_off))) 141 142 #define SN0_WIDGET_BASE(_nasid, _wid) (NODE_SWIN_BASE((_nasid), (_wid))) 143 144 /* Turn on sable logging for the processors whose bits are set. */ 145 #define SABLE_LOG_TRIGGER(_map) 146 147 #ifndef __ASSEMBLY__ 148 #define KERN_NMI_ADDR(nasid, slice) \ 149 TO_NODE_UNCAC((nasid), IP27_NMI_KREGS_OFFSET + \ 150 (IP27_NMI_KREGS_CPU_SIZE * (slice))) 151 #endif /* !__ASSEMBLY__ */ 152 153 #ifdef PROM 154 155 #define MISC_PROM_BASE PHYS_TO_K0(0x01300000) 156 #define MISC_PROM_SIZE 0x200000 157 158 #define DIAG_BASE PHYS_TO_K0(0x01500000) 159 #define DIAG_SIZE 0x300000 160 161 #define ROUTE_BASE PHYS_TO_K0(0x01800000) 162 #define ROUTE_SIZE 0x200000 163 164 #define IP27PROM_FLASH_HDR PHYS_TO_K0(0x01300000) 165 #define IP27PROM_FLASH_DATA PHYS_TO_K0(0x01301000) 166 #define IP27PROM_CORP_MAX 32 167 #define IP27PROM_CORP PHYS_TO_K0(0x01800000) 168 #define IP27PROM_CORP_SIZE 0x10000 169 #define IP27PROM_CORP_STK PHYS_TO_K0(0x01810000) 170 #define IP27PROM_CORP_STKSIZE 0x2000 171 #define IP27PROM_DECOMP_BUF PHYS_TO_K0(0x01900000) 172 #define IP27PROM_DECOMP_SIZE 0xfff00 173 174 #define IP27PROM_BASE PHYS_TO_K0(0x01a00000) 175 #define IP27PROM_BASE_MAPPED (UNCAC_BASE | 0x1fc00000) 176 #define IP27PROM_SIZE_MAX 0x100000 177 178 #define IP27PROM_PCFG PHYS_TO_K0(0x01b00000) 179 #define IP27PROM_PCFG_SIZE 0xd0000 180 #define IP27PROM_ERRDMP PHYS_TO_K1(0x01bd0000) 181 #define IP27PROM_ERRDMP_SIZE 0xf000 182 183 #define IP27PROM_INIT_START PHYS_TO_K1(0x01bd0000) 184 #define IP27PROM_CONSOLE PHYS_TO_K1(0x01bdf000) 185 #define IP27PROM_CONSOLE_SIZE 0x200 186 #define IP27PROM_NETUART PHYS_TO_K1(0x01bdf200) 187 #define IP27PROM_NETUART_SIZE 0x100 188 #define IP27PROM_UNUSED1 PHYS_TO_K1(0x01bdf300) 189 #define IP27PROM_UNUSED1_SIZE 0x500 190 #define IP27PROM_ELSC_BASE_A PHYS_TO_K0(0x01bdf800) 191 #define IP27PROM_ELSC_BASE_B PHYS_TO_K0(0x01bdfc00) 192 #define IP27PROM_STACK_A PHYS_TO_K0(0x01be0000) 193 #define IP27PROM_STACK_B PHYS_TO_K0(0x01bf0000) 194 #define IP27PROM_STACK_SHFT 16 195 #define IP27PROM_STACK_SIZE (1 << IP27PROM_STACK_SHFT) 196 #define IP27PROM_INIT_END PHYS_TO_K0(0x01c00000) 197 198 #define SLAVESTACK_BASE PHYS_TO_K0(0x01580000) 199 #define SLAVESTACK_SIZE 0x40000 200 201 #define ENETBUFS_BASE PHYS_TO_K0(0x01f80000) 202 #define ENETBUFS_SIZE 0x20000 203 204 #define IO6PROM_BASE PHYS_TO_K0(0x01c00000) 205 #define IO6PROM_SIZE 0x400000 206 #define IO6PROM_BASE_MAPPED (UNCAC_BASE | 0x11c00000) 207 #define IO6DPROM_BASE PHYS_TO_K0(0x01c00000) 208 #define IO6DPROM_SIZE 0x200000 209 210 #define NODEBUGUNIX_ADDR PHYS_TO_K0(0x00019000) 211 #define DEBUGUNIX_ADDR PHYS_TO_K0(0x00100000) 212 213 #define IP27PROM_INT_LAUNCH 10 /* and 11 */ 214 #define IP27PROM_INT_NETUART 12 /* through 17 */ 215 216 #endif /* PROM */ 217 218 /* 219 * needed by symmon so it needs to be outside #if PROM 220 */ 221 #define IP27PROM_ELSC_SHFT 10 222 #define IP27PROM_ELSC_SIZE (1 << IP27PROM_ELSC_SHFT) 223 224 /* 225 * This address is used by IO6PROM to build MemoryDescriptors of 226 * free memory. This address is important since unix gets loaded 227 * at this address, and this memory has to be FREE if unix is to 228 * be loaded. 229 */ 230 231 #define FREEMEM_BASE PHYS_TO_K0(0x2000000) 232 233 #define IO6PROM_STACK_SHFT 14 /* stack per cpu */ 234 #define IO6PROM_STACK_SIZE (1 << IO6PROM_STACK_SHFT) 235 236 /* 237 * IP27 PROM vectors 238 */ 239 240 #define IP27PROM_ENTRY PHYS_TO_COMPATK1(0x1fc00000) 241 #define IP27PROM_RESTART PHYS_TO_COMPATK1(0x1fc00008) 242 #define IP27PROM_SLAVELOOP PHYS_TO_COMPATK1(0x1fc00010) 243 #define IP27PROM_PODMODE PHYS_TO_COMPATK1(0x1fc00018) 244 #define IP27PROM_IOC3UARTPOD PHYS_TO_COMPATK1(0x1fc00020) 245 #define IP27PROM_FLASHLEDS PHYS_TO_COMPATK1(0x1fc00028) 246 #define IP27PROM_REPOD PHYS_TO_COMPATK1(0x1fc00030) 247 #define IP27PROM_LAUNCHSLAVE PHYS_TO_COMPATK1(0x1fc00038) 248 #define IP27PROM_WAITSLAVE PHYS_TO_COMPATK1(0x1fc00040) 249 #define IP27PROM_POLLSLAVE PHYS_TO_COMPATK1(0x1fc00048) 250 251 #define KL_UART_BASE LOCAL_HUB_ADDR(MD_UREG0_0) /* base of UART regs */ 252 #define KL_UART_CMD LOCAL_HUB_ADDR(MD_UREG0_0) /* UART command reg */ 253 #define KL_UART_DATA LOCAL_HUB_ADDR(MD_UREG0_1) /* UART data reg */ 254 #define KL_I2C_REG MD_UREG0_0 /* I2C reg */ 255 256 #ifndef __ASSEMBLY__ 257 258 /* Address 0x400 to 0x1000 ualias points to cache error eframe + misc 259 * CACHE_ERR_SP_PTR could either contain an address to the stack, or 260 * the stack could start at CACHE_ERR_SP_PTR 261 */ 262 #if defined(HUB_ERR_STS_WAR) 263 #define CACHE_ERR_EFRAME 0x480 264 #else /* HUB_ERR_STS_WAR */ 265 #define CACHE_ERR_EFRAME 0x400 266 #endif /* HUB_ERR_STS_WAR */ 267 268 #define CACHE_ERR_ECCFRAME (CACHE_ERR_EFRAME + EF_SIZE) 269 #define CACHE_ERR_SP_PTR (0x1000 - 32) /* why -32? TBD */ 270 #define CACHE_ERR_IBASE_PTR (0x1000 - 40) 271 #define CACHE_ERR_SP (CACHE_ERR_SP_PTR - 16) 272 #define CACHE_ERR_AREA_SIZE (ARCS_SPB_OFFSET - CACHE_ERR_EFRAME) 273 274 #endif /* !__ASSEMBLY__ */ 275 276 #define _ARCSPROM 277 278 #if defined(HUB_ERR_STS_WAR) 279 280 #define ERR_STS_WAR_REGISTER IIO_IIBUSERR 281 #define ERR_STS_WAR_ADDR LOCAL_HUB_ADDR(IIO_IIBUSERR) 282 #define ERR_STS_WAR_PHYSADDR TO_PHYS((__psunsigned_t)ERR_STS_WAR_ADDR) 283 /* Used to match addr in error reg. */ 284 #define OLD_ERR_STS_WAR_OFFSET ((MD_MEM_BANKS * MD_BANK_SIZE) - 0x100) 285 286 #endif /* HUB_ERR_STS_WAR */ 287 288 #endif /* _ASM_SN_SN0_ADDRS_H */ 289