1 /* ********************************************************************* 2 * SB1250 Board Support Package 3 * 4 * MAC constants and macros File: sb1250_mac.h 5 * 6 * This module contains constants and macros for the SB1250's 7 * ethernet controllers. 8 * 9 * SB1250 specification level: User's manual 1/02/02 10 * 11 ********************************************************************* 12 * 13 * Copyright 2000,2001,2002,2003 14 * Broadcom Corporation. All rights reserved. 15 * 16 * This program is free software; you can redistribute it and/or 17 * modify it under the terms of the GNU General Public License as 18 * published by the Free Software Foundation; either version 2 of 19 * the License, or (at your option) any later version. 20 * 21 * This program is distributed in the hope that it will be useful, 22 * but WITHOUT ANY WARRANTY; without even the implied warranty of 23 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 24 * GNU General Public License for more details. 25 * 26 * You should have received a copy of the GNU General Public License 27 * along with this program; if not, write to the Free Software 28 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 29 * MA 02111-1307 USA 30 ********************************************************************* */ 31 32 33 #ifndef _SB1250_MAC_H 34 #define _SB1250_MAC_H 35 36 #include <asm/sibyte/sb1250_defs.h> 37 38 /* ********************************************************************* 39 * Ethernet MAC Registers 40 ********************************************************************* */ 41 42 /* 43 * MAC Configuration Register (Table 9-13) 44 * Register: MAC_CFG_0 45 * Register: MAC_CFG_1 46 * Register: MAC_CFG_2 47 */ 48 49 50 #define M_MAC_RESERVED0 _SB_MAKEMASK1(0) 51 #define M_MAC_TX_HOLD_SOP_EN _SB_MAKEMASK1(1) 52 #define M_MAC_RETRY_EN _SB_MAKEMASK1(2) 53 #define M_MAC_RET_DRPREQ_EN _SB_MAKEMASK1(3) 54 #define M_MAC_RET_UFL_EN _SB_MAKEMASK1(4) 55 #define M_MAC_BURST_EN _SB_MAKEMASK1(5) 56 57 #define S_MAC_TX_PAUSE _SB_MAKE64(6) 58 #define M_MAC_TX_PAUSE_CNT _SB_MAKEMASK(3, S_MAC_TX_PAUSE) 59 #define V_MAC_TX_PAUSE_CNT(x) _SB_MAKEVALUE(x, S_MAC_TX_PAUSE) 60 61 #define K_MAC_TX_PAUSE_CNT_512 0 62 #define K_MAC_TX_PAUSE_CNT_1K 1 63 #define K_MAC_TX_PAUSE_CNT_2K 2 64 #define K_MAC_TX_PAUSE_CNT_4K 3 65 #define K_MAC_TX_PAUSE_CNT_8K 4 66 #define K_MAC_TX_PAUSE_CNT_16K 5 67 #define K_MAC_TX_PAUSE_CNT_32K 6 68 #define K_MAC_TX_PAUSE_CNT_64K 7 69 70 #define V_MAC_TX_PAUSE_CNT_512 V_MAC_TX_PAUSE_CNT(K_MAC_TX_PAUSE_CNT_512) 71 #define V_MAC_TX_PAUSE_CNT_1K V_MAC_TX_PAUSE_CNT(K_MAC_TX_PAUSE_CNT_1K) 72 #define V_MAC_TX_PAUSE_CNT_2K V_MAC_TX_PAUSE_CNT(K_MAC_TX_PAUSE_CNT_2K) 73 #define V_MAC_TX_PAUSE_CNT_4K V_MAC_TX_PAUSE_CNT(K_MAC_TX_PAUSE_CNT_4K) 74 #define V_MAC_TX_PAUSE_CNT_8K V_MAC_TX_PAUSE_CNT(K_MAC_TX_PAUSE_CNT_8K) 75 #define V_MAC_TX_PAUSE_CNT_16K V_MAC_TX_PAUSE_CNT(K_MAC_TX_PAUSE_CNT_16K) 76 #define V_MAC_TX_PAUSE_CNT_32K V_MAC_TX_PAUSE_CNT(K_MAC_TX_PAUSE_CNT_32K) 77 #define V_MAC_TX_PAUSE_CNT_64K V_MAC_TX_PAUSE_CNT(K_MAC_TX_PAUSE_CNT_64K) 78 79 #define M_MAC_RESERVED1 _SB_MAKEMASK(8, 9) 80 81 #define M_MAC_AP_STAT_EN _SB_MAKEMASK1(17) 82 83 #if SIBYTE_HDR_FEATURE_CHIP(1480) 84 #define M_MAC_TIMESTAMP _SB_MAKEMASK1(18) 85 #endif 86 #define M_MAC_DRP_ERRPKT_EN _SB_MAKEMASK1(19) 87 #define M_MAC_DRP_FCSERRPKT_EN _SB_MAKEMASK1(20) 88 #define M_MAC_DRP_CODEERRPKT_EN _SB_MAKEMASK1(21) 89 #define M_MAC_DRP_DRBLERRPKT_EN _SB_MAKEMASK1(22) 90 #define M_MAC_DRP_RNTPKT_EN _SB_MAKEMASK1(23) 91 #define M_MAC_DRP_OSZPKT_EN _SB_MAKEMASK1(24) 92 #define M_MAC_DRP_LENERRPKT_EN _SB_MAKEMASK1(25) 93 94 #define M_MAC_RESERVED3 _SB_MAKEMASK(6, 26) 95 96 #define M_MAC_BYPASS_SEL _SB_MAKEMASK1(32) 97 #define M_MAC_HDX_EN _SB_MAKEMASK1(33) 98 99 #define S_MAC_SPEED_SEL _SB_MAKE64(34) 100 #define M_MAC_SPEED_SEL _SB_MAKEMASK(2, S_MAC_SPEED_SEL) 101 #define V_MAC_SPEED_SEL(x) _SB_MAKEVALUE(x, S_MAC_SPEED_SEL) 102 #define G_MAC_SPEED_SEL(x) _SB_GETVALUE(x, S_MAC_SPEED_SEL, M_MAC_SPEED_SEL) 103 104 #define K_MAC_SPEED_SEL_10MBPS 0 105 #define K_MAC_SPEED_SEL_100MBPS 1 106 #define K_MAC_SPEED_SEL_1000MBPS 2 107 #define K_MAC_SPEED_SEL_RESERVED 3 108 109 #define V_MAC_SPEED_SEL_10MBPS V_MAC_SPEED_SEL(K_MAC_SPEED_SEL_10MBPS) 110 #define V_MAC_SPEED_SEL_100MBPS V_MAC_SPEED_SEL(K_MAC_SPEED_SEL_100MBPS) 111 #define V_MAC_SPEED_SEL_1000MBPS V_MAC_SPEED_SEL(K_MAC_SPEED_SEL_1000MBPS) 112 #define V_MAC_SPEED_SEL_RESERVED V_MAC_SPEED_SEL(K_MAC_SPEED_SEL_RESERVED) 113 114 #define M_MAC_TX_CLK_EDGE_SEL _SB_MAKEMASK1(36) 115 #define M_MAC_LOOPBACK_SEL _SB_MAKEMASK1(37) 116 #define M_MAC_FAST_SYNC _SB_MAKEMASK1(38) 117 #define M_MAC_SS_EN _SB_MAKEMASK1(39) 118 119 #define S_MAC_BYPASS_CFG _SB_MAKE64(40) 120 #define M_MAC_BYPASS_CFG _SB_MAKEMASK(2, S_MAC_BYPASS_CFG) 121 #define V_MAC_BYPASS_CFG(x) _SB_MAKEVALUE(x, S_MAC_BYPASS_CFG) 122 #define G_MAC_BYPASS_CFG(x) _SB_GETVALUE(x, S_MAC_BYPASS_CFG, M_MAC_BYPASS_CFG) 123 124 #define K_MAC_BYPASS_GMII 0 125 #define K_MAC_BYPASS_ENCODED 1 126 #define K_MAC_BYPASS_SOP 2 127 #define K_MAC_BYPASS_EOP 3 128 129 #define M_MAC_BYPASS_16 _SB_MAKEMASK1(42) 130 #define M_MAC_BYPASS_FCS_CHK _SB_MAKEMASK1(43) 131 132 #if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480) 133 #define M_MAC_RX_CH_SEL_MSB _SB_MAKEMASK1(44) 134 #endif /* 1250 PASS2 || 112x PASS1 || 1480*/ 135 136 #if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480) 137 #define M_MAC_SPLIT_CH_SEL _SB_MAKEMASK1(45) 138 #endif /* 1250 PASS3 || 112x PASS1 || 1480 */ 139 140 #define S_MAC_BYPASS_IFG _SB_MAKE64(46) 141 #define M_MAC_BYPASS_IFG _SB_MAKEMASK(8, S_MAC_BYPASS_IFG) 142 #define V_MAC_BYPASS_IFG(x) _SB_MAKEVALUE(x, S_MAC_BYPASS_IFG) 143 #define G_MAC_BYPASS_IFG(x) _SB_GETVALUE(x, S_MAC_BYPASS_IFG, M_MAC_BYPASS_IFG) 144 145 #define K_MAC_FC_CMD_DISABLED 0 146 #define K_MAC_FC_CMD_ENABLED 1 147 #define K_MAC_FC_CMD_ENAB_FALSECARR 2 148 149 #define V_MAC_FC_CMD_DISABLED V_MAC_FC_CMD(K_MAC_FC_CMD_DISABLED) 150 #define V_MAC_FC_CMD_ENABLED V_MAC_FC_CMD(K_MAC_FC_CMD_ENABLED) 151 #define V_MAC_FC_CMD_ENAB_FALSECARR V_MAC_FC_CMD(K_MAC_FC_CMD_ENAB_FALSECARR) 152 153 #define M_MAC_FC_SEL _SB_MAKEMASK1(54) 154 155 #define S_MAC_FC_CMD _SB_MAKE64(55) 156 #define M_MAC_FC_CMD _SB_MAKEMASK(2, S_MAC_FC_CMD) 157 #define V_MAC_FC_CMD(x) _SB_MAKEVALUE(x, S_MAC_FC_CMD) 158 #define G_MAC_FC_CMD(x) _SB_GETVALUE(x, S_MAC_FC_CMD, M_MAC_FC_CMD) 159 160 #define S_MAC_RX_CH_SEL _SB_MAKE64(57) 161 #define M_MAC_RX_CH_SEL _SB_MAKEMASK(7, S_MAC_RX_CH_SEL) 162 #define V_MAC_RX_CH_SEL(x) _SB_MAKEVALUE(x, S_MAC_RX_CH_SEL) 163 #define G_MAC_RX_CH_SEL(x) _SB_GETVALUE(x, S_MAC_RX_CH_SEL, M_MAC_RX_CH_SEL) 164 165 166 /* 167 * MAC Enable Registers 168 * Register: MAC_ENABLE_0 169 * Register: MAC_ENABLE_1 170 * Register: MAC_ENABLE_2 171 */ 172 173 #define M_MAC_RXDMA_EN0 _SB_MAKEMASK1(0) 174 #define M_MAC_RXDMA_EN1 _SB_MAKEMASK1(1) 175 #define M_MAC_TXDMA_EN0 _SB_MAKEMASK1(4) 176 #define M_MAC_TXDMA_EN1 _SB_MAKEMASK1(5) 177 178 #define M_MAC_PORT_RESET _SB_MAKEMASK1(8) 179 180 #if (SIBYTE_HDR_FEATURE_CHIP(1250) || SIBYTE_HDR_FEATURE_CHIP(112x)) 181 #define M_MAC_RX_ENABLE _SB_MAKEMASK1(10) 182 #define M_MAC_TX_ENABLE _SB_MAKEMASK1(11) 183 #define M_MAC_BYP_RX_ENABLE _SB_MAKEMASK1(12) 184 #define M_MAC_BYP_TX_ENABLE _SB_MAKEMASK1(13) 185 #endif 186 187 /* 188 * MAC reset information register (1280/1255) 189 */ 190 #if SIBYTE_HDR_FEATURE_CHIP(1480) 191 #define M_MAC_RX_CH0_PAUSE_ON _SB_MAKEMASK1(8) 192 #define M_MAC_RX_CH1_PAUSE_ON _SB_MAKEMASK1(16) 193 #define M_MAC_TX_CH0_PAUSE_ON _SB_MAKEMASK1(24) 194 #define M_MAC_TX_CH1_PAUSE_ON _SB_MAKEMASK1(32) 195 #endif 196 197 /* 198 * MAC DMA Control Register 199 * Register: MAC_TXD_CTL_0 200 * Register: MAC_TXD_CTL_1 201 * Register: MAC_TXD_CTL_2 202 */ 203 204 #define S_MAC_TXD_WEIGHT0 _SB_MAKE64(0) 205 #define M_MAC_TXD_WEIGHT0 _SB_MAKEMASK(4, S_MAC_TXD_WEIGHT0) 206 #define V_MAC_TXD_WEIGHT0(x) _SB_MAKEVALUE(x, S_MAC_TXD_WEIGHT0) 207 #define G_MAC_TXD_WEIGHT0(x) _SB_GETVALUE(x, S_MAC_TXD_WEIGHT0, M_MAC_TXD_WEIGHT0) 208 209 #define S_MAC_TXD_WEIGHT1 _SB_MAKE64(4) 210 #define M_MAC_TXD_WEIGHT1 _SB_MAKEMASK(4, S_MAC_TXD_WEIGHT1) 211 #define V_MAC_TXD_WEIGHT1(x) _SB_MAKEVALUE(x, S_MAC_TXD_WEIGHT1) 212 #define G_MAC_TXD_WEIGHT1(x) _SB_GETVALUE(x, S_MAC_TXD_WEIGHT1, M_MAC_TXD_WEIGHT1) 213 214 /* 215 * MAC Fifo Threshold registers (Table 9-14) 216 * Register: MAC_THRSH_CFG_0 217 * Register: MAC_THRSH_CFG_1 218 * Register: MAC_THRSH_CFG_2 219 */ 220 221 #define S_MAC_TX_WR_THRSH _SB_MAKE64(0) 222 #if SIBYTE_HDR_FEATURE_UP_TO(1250, PASS1) 223 /* XXX: Can't enable, as it has the same name as a pass2+ define below. */ 224 /* #define M_MAC_TX_WR_THRSH _SB_MAKEMASK(6, S_MAC_TX_WR_THRSH) */ 225 #endif /* up to 1250 PASS1 */ 226 #if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480) 227 #define M_MAC_TX_WR_THRSH _SB_MAKEMASK(7, S_MAC_TX_WR_THRSH) 228 #endif /* 1250 PASS2 || 112x PASS1 || 1480 */ 229 #define V_MAC_TX_WR_THRSH(x) _SB_MAKEVALUE(x, S_MAC_TX_WR_THRSH) 230 #define G_MAC_TX_WR_THRSH(x) _SB_GETVALUE(x, S_MAC_TX_WR_THRSH, M_MAC_TX_WR_THRSH) 231 232 #define S_MAC_TX_RD_THRSH _SB_MAKE64(8) 233 #if SIBYTE_HDR_FEATURE_UP_TO(1250, PASS1) 234 /* XXX: Can't enable, as it has the same name as a pass2+ define below. */ 235 /* #define M_MAC_TX_RD_THRSH _SB_MAKEMASK(6, S_MAC_TX_RD_THRSH) */ 236 #endif /* up to 1250 PASS1 */ 237 #if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480) 238 #define M_MAC_TX_RD_THRSH _SB_MAKEMASK(7, S_MAC_TX_RD_THRSH) 239 #endif /* 1250 PASS2 || 112x PASS1 || 1480 */ 240 #define V_MAC_TX_RD_THRSH(x) _SB_MAKEVALUE(x, S_MAC_TX_RD_THRSH) 241 #define G_MAC_TX_RD_THRSH(x) _SB_GETVALUE(x, S_MAC_TX_RD_THRSH, M_MAC_TX_RD_THRSH) 242 243 #define S_MAC_TX_RL_THRSH _SB_MAKE64(16) 244 #define M_MAC_TX_RL_THRSH _SB_MAKEMASK(4, S_MAC_TX_RL_THRSH) 245 #define V_MAC_TX_RL_THRSH(x) _SB_MAKEVALUE(x, S_MAC_TX_RL_THRSH) 246 #define G_MAC_TX_RL_THRSH(x) _SB_GETVALUE(x, S_MAC_TX_RL_THRSH, M_MAC_TX_RL_THRSH) 247 248 #define S_MAC_RX_PL_THRSH _SB_MAKE64(24) 249 #define M_MAC_RX_PL_THRSH _SB_MAKEMASK(6, S_MAC_RX_PL_THRSH) 250 #define V_MAC_RX_PL_THRSH(x) _SB_MAKEVALUE(x, S_MAC_RX_PL_THRSH) 251 #define G_MAC_RX_PL_THRSH(x) _SB_GETVALUE(x, S_MAC_RX_PL_THRSH, M_MAC_RX_PL_THRSH) 252 253 #define S_MAC_RX_RD_THRSH _SB_MAKE64(32) 254 #define M_MAC_RX_RD_THRSH _SB_MAKEMASK(6, S_MAC_RX_RD_THRSH) 255 #define V_MAC_RX_RD_THRSH(x) _SB_MAKEVALUE(x, S_MAC_RX_RD_THRSH) 256 #define G_MAC_RX_RD_THRSH(x) _SB_GETVALUE(x, S_MAC_RX_RD_THRSH, M_MAC_RX_RD_THRSH) 257 258 #define S_MAC_RX_RL_THRSH _SB_MAKE64(40) 259 #define M_MAC_RX_RL_THRSH _SB_MAKEMASK(6, S_MAC_RX_RL_THRSH) 260 #define V_MAC_RX_RL_THRSH(x) _SB_MAKEVALUE(x, S_MAC_RX_RL_THRSH) 261 #define G_MAC_RX_RL_THRSH(x) _SB_GETVALUE(x, S_MAC_RX_RL_THRSH, M_MAC_RX_RL_THRSH) 262 263 #if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480) 264 #define S_MAC_ENC_FC_THRSH _SB_MAKE64(56) 265 #define M_MAC_ENC_FC_THRSH _SB_MAKEMASK(6, S_MAC_ENC_FC_THRSH) 266 #define V_MAC_ENC_FC_THRSH(x) _SB_MAKEVALUE(x, S_MAC_ENC_FC_THRSH) 267 #define G_MAC_ENC_FC_THRSH(x) _SB_GETVALUE(x, S_MAC_ENC_FC_THRSH, M_MAC_ENC_FC_THRSH) 268 #endif /* 1250 PASS2 || 112x PASS1 || 1480 */ 269 270 /* 271 * MAC Frame Configuration Registers (Table 9-15) 272 * Register: MAC_FRAME_CFG_0 273 * Register: MAC_FRAME_CFG_1 274 * Register: MAC_FRAME_CFG_2 275 */ 276 277 /* XXXCGD: ??? Unused in pass2? */ 278 #define S_MAC_IFG_RX _SB_MAKE64(0) 279 #define M_MAC_IFG_RX _SB_MAKEMASK(6, S_MAC_IFG_RX) 280 #define V_MAC_IFG_RX(x) _SB_MAKEVALUE(x, S_MAC_IFG_RX) 281 #define G_MAC_IFG_RX(x) _SB_GETVALUE(x, S_MAC_IFG_RX, M_MAC_IFG_RX) 282 283 #if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480) 284 #define S_MAC_PRE_LEN _SB_MAKE64(0) 285 #define M_MAC_PRE_LEN _SB_MAKEMASK(6, S_MAC_PRE_LEN) 286 #define V_MAC_PRE_LEN(x) _SB_MAKEVALUE(x, S_MAC_PRE_LEN) 287 #define G_MAC_PRE_LEN(x) _SB_GETVALUE(x, S_MAC_PRE_LEN, M_MAC_PRE_LEN) 288 #endif /* 1250 PASS3 || 112x PASS1 || 1480 */ 289 290 #define S_MAC_IFG_TX _SB_MAKE64(6) 291 #define M_MAC_IFG_TX _SB_MAKEMASK(6, S_MAC_IFG_TX) 292 #define V_MAC_IFG_TX(x) _SB_MAKEVALUE(x, S_MAC_IFG_TX) 293 #define G_MAC_IFG_TX(x) _SB_GETVALUE(x, S_MAC_IFG_TX, M_MAC_IFG_TX) 294 295 #define S_MAC_IFG_THRSH _SB_MAKE64(12) 296 #define M_MAC_IFG_THRSH _SB_MAKEMASK(6, S_MAC_IFG_THRSH) 297 #define V_MAC_IFG_THRSH(x) _SB_MAKEVALUE(x, S_MAC_IFG_THRSH) 298 #define G_MAC_IFG_THRSH(x) _SB_GETVALUE(x, S_MAC_IFG_THRSH, M_MAC_IFG_THRSH) 299 300 #define S_MAC_BACKOFF_SEL _SB_MAKE64(18) 301 #define M_MAC_BACKOFF_SEL _SB_MAKEMASK(4, S_MAC_BACKOFF_SEL) 302 #define V_MAC_BACKOFF_SEL(x) _SB_MAKEVALUE(x, S_MAC_BACKOFF_SEL) 303 #define G_MAC_BACKOFF_SEL(x) _SB_GETVALUE(x, S_MAC_BACKOFF_SEL, M_MAC_BACKOFF_SEL) 304 305 #define S_MAC_LFSR_SEED _SB_MAKE64(22) 306 #define M_MAC_LFSR_SEED _SB_MAKEMASK(8, S_MAC_LFSR_SEED) 307 #define V_MAC_LFSR_SEED(x) _SB_MAKEVALUE(x, S_MAC_LFSR_SEED) 308 #define G_MAC_LFSR_SEED(x) _SB_GETVALUE(x, S_MAC_LFSR_SEED, M_MAC_LFSR_SEED) 309 310 #define S_MAC_SLOT_SIZE _SB_MAKE64(30) 311 #define M_MAC_SLOT_SIZE _SB_MAKEMASK(10, S_MAC_SLOT_SIZE) 312 #define V_MAC_SLOT_SIZE(x) _SB_MAKEVALUE(x, S_MAC_SLOT_SIZE) 313 #define G_MAC_SLOT_SIZE(x) _SB_GETVALUE(x, S_MAC_SLOT_SIZE, M_MAC_SLOT_SIZE) 314 315 #define S_MAC_MIN_FRAMESZ _SB_MAKE64(40) 316 #define M_MAC_MIN_FRAMESZ _SB_MAKEMASK(8, S_MAC_MIN_FRAMESZ) 317 #define V_MAC_MIN_FRAMESZ(x) _SB_MAKEVALUE(x, S_MAC_MIN_FRAMESZ) 318 #define G_MAC_MIN_FRAMESZ(x) _SB_GETVALUE(x, S_MAC_MIN_FRAMESZ, M_MAC_MIN_FRAMESZ) 319 320 #define S_MAC_MAX_FRAMESZ _SB_MAKE64(48) 321 #define M_MAC_MAX_FRAMESZ _SB_MAKEMASK(16, S_MAC_MAX_FRAMESZ) 322 #define V_MAC_MAX_FRAMESZ(x) _SB_MAKEVALUE(x, S_MAC_MAX_FRAMESZ) 323 #define G_MAC_MAX_FRAMESZ(x) _SB_GETVALUE(x, S_MAC_MAX_FRAMESZ, M_MAC_MAX_FRAMESZ) 324 325 /* 326 * These constants are used to configure the fields within the Frame 327 * Configuration Register. 328 */ 329 330 #define K_MAC_IFG_RX_10 _SB_MAKE64(0) /* See table 176, not used */ 331 #define K_MAC_IFG_RX_100 _SB_MAKE64(0) 332 #define K_MAC_IFG_RX_1000 _SB_MAKE64(0) 333 334 #define K_MAC_IFG_TX_10 _SB_MAKE64(20) 335 #define K_MAC_IFG_TX_100 _SB_MAKE64(20) 336 #define K_MAC_IFG_TX_1000 _SB_MAKE64(8) 337 338 #define K_MAC_IFG_THRSH_10 _SB_MAKE64(4) 339 #define K_MAC_IFG_THRSH_100 _SB_MAKE64(4) 340 #define K_MAC_IFG_THRSH_1000 _SB_MAKE64(0) 341 342 #define K_MAC_SLOT_SIZE_10 _SB_MAKE64(0) 343 #define K_MAC_SLOT_SIZE_100 _SB_MAKE64(0) 344 #define K_MAC_SLOT_SIZE_1000 _SB_MAKE64(0) 345 346 #define V_MAC_IFG_RX_10 V_MAC_IFG_RX(K_MAC_IFG_RX_10) 347 #define V_MAC_IFG_RX_100 V_MAC_IFG_RX(K_MAC_IFG_RX_100) 348 #define V_MAC_IFG_RX_1000 V_MAC_IFG_RX(K_MAC_IFG_RX_1000) 349 350 #define V_MAC_IFG_TX_10 V_MAC_IFG_TX(K_MAC_IFG_TX_10) 351 #define V_MAC_IFG_TX_100 V_MAC_IFG_TX(K_MAC_IFG_TX_100) 352 #define V_MAC_IFG_TX_1000 V_MAC_IFG_TX(K_MAC_IFG_TX_1000) 353 354 #define V_MAC_IFG_THRSH_10 V_MAC_IFG_THRSH(K_MAC_IFG_THRSH_10) 355 #define V_MAC_IFG_THRSH_100 V_MAC_IFG_THRSH(K_MAC_IFG_THRSH_100) 356 #define V_MAC_IFG_THRSH_1000 V_MAC_IFG_THRSH(K_MAC_IFG_THRSH_1000) 357 358 #define V_MAC_SLOT_SIZE_10 V_MAC_SLOT_SIZE(K_MAC_SLOT_SIZE_10) 359 #define V_MAC_SLOT_SIZE_100 V_MAC_SLOT_SIZE(K_MAC_SLOT_SIZE_100) 360 #define V_MAC_SLOT_SIZE_1000 V_MAC_SLOT_SIZE(K_MAC_SLOT_SIZE_1000) 361 362 #define K_MAC_MIN_FRAMESZ_FIFO _SB_MAKE64(9) 363 #define K_MAC_MIN_FRAMESZ_DEFAULT _SB_MAKE64(64) 364 #define K_MAC_MAX_FRAMESZ_DEFAULT _SB_MAKE64(1518) 365 #define K_MAC_MAX_FRAMESZ_JUMBO _SB_MAKE64(9216) 366 367 #define V_MAC_MIN_FRAMESZ_FIFO V_MAC_MIN_FRAMESZ(K_MAC_MIN_FRAMESZ_FIFO) 368 #define V_MAC_MIN_FRAMESZ_DEFAULT V_MAC_MIN_FRAMESZ(K_MAC_MIN_FRAMESZ_DEFAULT) 369 #define V_MAC_MAX_FRAMESZ_DEFAULT V_MAC_MAX_FRAMESZ(K_MAC_MAX_FRAMESZ_DEFAULT) 370 #define V_MAC_MAX_FRAMESZ_JUMBO V_MAC_MAX_FRAMESZ(K_MAC_MAX_FRAMESZ_JUMBO) 371 372 /* 373 * MAC VLAN Tag Registers (Table 9-16) 374 * Register: MAC_VLANTAG_0 375 * Register: MAC_VLANTAG_1 376 * Register: MAC_VLANTAG_2 377 */ 378 379 #define S_MAC_VLAN_TAG _SB_MAKE64(0) 380 #define M_MAC_VLAN_TAG _SB_MAKEMASK(32, S_MAC_VLAN_TAG) 381 #define V_MAC_VLAN_TAG(x) _SB_MAKEVALUE(x, S_MAC_VLAN_TAG) 382 #define G_MAC_VLAN_TAG(x) _SB_GETVALUE(x, S_MAC_VLAN_TAG, M_MAC_VLAN_TAG) 383 384 #if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1) 385 #define S_MAC_TX_PKT_OFFSET _SB_MAKE64(32) 386 #define M_MAC_TX_PKT_OFFSET _SB_MAKEMASK(8, S_MAC_TX_PKT_OFFSET) 387 #define V_MAC_TX_PKT_OFFSET(x) _SB_MAKEVALUE(x, S_MAC_TX_PKT_OFFSET) 388 #define G_MAC_TX_PKT_OFFSET(x) _SB_GETVALUE(x, S_MAC_TX_PKT_OFFSET, M_MAC_TX_PKT_OFFSET) 389 390 #define S_MAC_TX_CRC_OFFSET _SB_MAKE64(40) 391 #define M_MAC_TX_CRC_OFFSET _SB_MAKEMASK(8, S_MAC_TX_CRC_OFFSET) 392 #define V_MAC_TX_CRC_OFFSET(x) _SB_MAKEVALUE(x, S_MAC_TX_CRC_OFFSET) 393 #define G_MAC_TX_CRC_OFFSET(x) _SB_GETVALUE(x, S_MAC_TX_CRC_OFFSET, M_MAC_TX_CRC_OFFSET) 394 395 #define M_MAC_CH_BASE_FC_EN _SB_MAKEMASK1(48) 396 #endif /* 1250 PASS3 || 112x PASS1 */ 397 398 /* 399 * MAC Status Registers (Table 9-17) 400 * Also used for the MAC Interrupt Mask Register (Table 9-18) 401 * Register: MAC_STATUS_0 402 * Register: MAC_STATUS_1 403 * Register: MAC_STATUS_2 404 * Register: MAC_INT_MASK_0 405 * Register: MAC_INT_MASK_1 406 * Register: MAC_INT_MASK_2 407 */ 408 409 /* 410 * Use these constants to shift the appropriate channel 411 * into the CH0 position so the same tests can be used 412 * on each channel. 413 */ 414 415 #define S_MAC_RX_CH0 _SB_MAKE64(0) 416 #define S_MAC_RX_CH1 _SB_MAKE64(8) 417 #define S_MAC_TX_CH0 _SB_MAKE64(16) 418 #define S_MAC_TX_CH1 _SB_MAKE64(24) 419 420 #define S_MAC_TXCHANNELS _SB_MAKE64(16) /* this is 1st TX chan */ 421 #define S_MAC_CHANWIDTH _SB_MAKE64(8) /* bits between channels */ 422 423 /* 424 * These are the same as RX channel 0. The idea here 425 * is that you'll use one of the "S_" things above 426 * and pass just the six bits to a DMA-channel-specific ISR 427 */ 428 #define M_MAC_INT_CHANNEL _SB_MAKEMASK(8, 0) 429 #define M_MAC_INT_EOP_COUNT _SB_MAKEMASK1(0) 430 #define M_MAC_INT_EOP_TIMER _SB_MAKEMASK1(1) 431 #define M_MAC_INT_EOP_SEEN _SB_MAKEMASK1(2) 432 #define M_MAC_INT_HWM _SB_MAKEMASK1(3) 433 #define M_MAC_INT_LWM _SB_MAKEMASK1(4) 434 #define M_MAC_INT_DSCR _SB_MAKEMASK1(5) 435 #define M_MAC_INT_ERR _SB_MAKEMASK1(6) 436 #define M_MAC_INT_DZERO _SB_MAKEMASK1(7) /* only for TX channels */ 437 #define M_MAC_INT_DROP _SB_MAKEMASK1(7) /* only for RX channels */ 438 439 /* 440 * In the following definitions we use ch (0/1) and txrx (TX=1, RX=0, see 441 * also DMA_TX/DMA_RX in sb_regs.h). 442 */ 443 #define S_MAC_STATUS_CH_OFFSET(ch, txrx) _SB_MAKE64(((ch) + 2 * (txrx)) * S_MAC_CHANWIDTH) 444 445 #define M_MAC_STATUS_CHANNEL(ch, txrx) _SB_MAKEVALUE(_SB_MAKEMASK(8, 0), S_MAC_STATUS_CH_OFFSET(ch, txrx)) 446 #define M_MAC_STATUS_EOP_COUNT(ch, txrx) _SB_MAKEVALUE(M_MAC_INT_EOP_COUNT, S_MAC_STATUS_CH_OFFSET(ch, txrx)) 447 #define M_MAC_STATUS_EOP_TIMER(ch, txrx) _SB_MAKEVALUE(M_MAC_INT_EOP_TIMER, S_MAC_STATUS_CH_OFFSET(ch, txrx)) 448 #define M_MAC_STATUS_EOP_SEEN(ch, txrx) _SB_MAKEVALUE(M_MAC_INT_EOP_SEEN, S_MAC_STATUS_CH_OFFSET(ch, txrx)) 449 #define M_MAC_STATUS_HWM(ch, txrx) _SB_MAKEVALUE(M_MAC_INT_HWM, S_MAC_STATUS_CH_OFFSET(ch, txrx)) 450 #define M_MAC_STATUS_LWM(ch, txrx) _SB_MAKEVALUE(M_MAC_INT_LWM, S_MAC_STATUS_CH_OFFSET(ch, txrx)) 451 #define M_MAC_STATUS_DSCR(ch, txrx) _SB_MAKEVALUE(M_MAC_INT_DSCR, S_MAC_STATUS_CH_OFFSET(ch, txrx)) 452 #define M_MAC_STATUS_ERR(ch, txrx) _SB_MAKEVALUE(M_MAC_INT_ERR, S_MAC_STATUS_CH_OFFSET(ch, txrx)) 453 #define M_MAC_STATUS_DZERO(ch, txrx) _SB_MAKEVALUE(M_MAC_INT_DZERO, S_MAC_STATUS_CH_OFFSET(ch, txrx)) 454 #define M_MAC_STATUS_DROP(ch, txrx) _SB_MAKEVALUE(M_MAC_INT_DROP, S_MAC_STATUS_CH_OFFSET(ch, txrx)) 455 #define M_MAC_STATUS_OTHER_ERR _SB_MAKEVALUE(_SB_MAKEMASK(7, 0), 40) 456 457 458 #define M_MAC_RX_UNDRFL _SB_MAKEMASK1(40) 459 #define M_MAC_RX_OVRFL _SB_MAKEMASK1(41) 460 #define M_MAC_TX_UNDRFL _SB_MAKEMASK1(42) 461 #define M_MAC_TX_OVRFL _SB_MAKEMASK1(43) 462 #define M_MAC_LTCOL_ERR _SB_MAKEMASK1(44) 463 #define M_MAC_EXCOL_ERR _SB_MAKEMASK1(45) 464 #define M_MAC_CNTR_OVRFL_ERR _SB_MAKEMASK1(46) 465 #if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480) 466 #define M_MAC_SPLIT_EN _SB_MAKEMASK1(47) /* interrupt mask only */ 467 #endif /* 1250 PASS2 || 112x PASS1 || 1480 */ 468 469 #define S_MAC_COUNTER_ADDR _SB_MAKE64(47) 470 #define M_MAC_COUNTER_ADDR _SB_MAKEMASK(5, S_MAC_COUNTER_ADDR) 471 #define V_MAC_COUNTER_ADDR(x) _SB_MAKEVALUE(x, S_MAC_COUNTER_ADDR) 472 #define G_MAC_COUNTER_ADDR(x) _SB_GETVALUE(x, S_MAC_COUNTER_ADDR, M_MAC_COUNTER_ADDR) 473 474 #if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480) 475 #define M_MAC_TX_PAUSE_ON _SB_MAKEMASK1(52) 476 #endif /* 1250 PASS3 || 112x PASS1 || 1480 */ 477 478 /* 479 * MAC Fifo Pointer Registers (Table 9-19) [Debug register] 480 * Register: MAC_FIFO_PTRS_0 481 * Register: MAC_FIFO_PTRS_1 482 * Register: MAC_FIFO_PTRS_2 483 */ 484 485 #define S_MAC_TX_WRPTR _SB_MAKE64(0) 486 #define M_MAC_TX_WRPTR _SB_MAKEMASK(6, S_MAC_TX_WRPTR) 487 #define V_MAC_TX_WRPTR(x) _SB_MAKEVALUE(x, S_MAC_TX_WRPTR) 488 #define G_MAC_TX_WRPTR(x) _SB_GETVALUE(x, S_MAC_TX_WRPTR, M_MAC_TX_WRPTR) 489 490 #define S_MAC_TX_RDPTR _SB_MAKE64(8) 491 #define M_MAC_TX_RDPTR _SB_MAKEMASK(6, S_MAC_TX_RDPTR) 492 #define V_MAC_TX_RDPTR(x) _SB_MAKEVALUE(x, S_MAC_TX_RDPTR) 493 #define G_MAC_TX_RDPTR(x) _SB_GETVALUE(x, S_MAC_TX_RDPTR, M_MAC_TX_RDPTR) 494 495 #define S_MAC_RX_WRPTR _SB_MAKE64(16) 496 #define M_MAC_RX_WRPTR _SB_MAKEMASK(6, S_MAC_RX_WRPTR) 497 #define V_MAC_RX_WRPTR(x) _SB_MAKEVALUE(x, S_MAC_RX_WRPTR) 498 #define G_MAC_RX_WRPTR(x) _SB_GETVALUE(x, S_MAC_RX_WRPTR, M_MAC_TX_WRPTR) 499 500 #define S_MAC_RX_RDPTR _SB_MAKE64(24) 501 #define M_MAC_RX_RDPTR _SB_MAKEMASK(6, S_MAC_RX_RDPTR) 502 #define V_MAC_RX_RDPTR(x) _SB_MAKEVALUE(x, S_MAC_RX_RDPTR) 503 #define G_MAC_RX_RDPTR(x) _SB_GETVALUE(x, S_MAC_RX_RDPTR, M_MAC_TX_RDPTR) 504 505 /* 506 * MAC Fifo End Of Packet Count Registers (Table 9-20) [Debug register] 507 * Register: MAC_EOPCNT_0 508 * Register: MAC_EOPCNT_1 509 * Register: MAC_EOPCNT_2 510 */ 511 512 #define S_MAC_TX_EOP_COUNTER _SB_MAKE64(0) 513 #define M_MAC_TX_EOP_COUNTER _SB_MAKEMASK(6, S_MAC_TX_EOP_COUNTER) 514 #define V_MAC_TX_EOP_COUNTER(x) _SB_MAKEVALUE(x, S_MAC_TX_EOP_COUNTER) 515 #define G_MAC_TX_EOP_COUNTER(x) _SB_GETVALUE(x, S_MAC_TX_EOP_COUNTER, M_MAC_TX_EOP_COUNTER) 516 517 #define S_MAC_RX_EOP_COUNTER _SB_MAKE64(8) 518 #define M_MAC_RX_EOP_COUNTER _SB_MAKEMASK(6, S_MAC_RX_EOP_COUNTER) 519 #define V_MAC_RX_EOP_COUNTER(x) _SB_MAKEVALUE(x, S_MAC_RX_EOP_COUNTER) 520 #define G_MAC_RX_EOP_COUNTER(x) _SB_GETVALUE(x, S_MAC_RX_EOP_COUNTER, M_MAC_RX_EOP_COUNTER) 521 522 /* 523 * MAC Receive Address Filter Exact Match Registers (Table 9-21) 524 * Registers: MAC_ADDR0_0 through MAC_ADDR7_0 525 * Registers: MAC_ADDR0_1 through MAC_ADDR7_1 526 * Registers: MAC_ADDR0_2 through MAC_ADDR7_2 527 */ 528 529 /* No bitfields */ 530 531 /* 532 * MAC Receive Address Filter Mask Registers 533 * Registers: MAC_ADDRMASK0_0 and MAC_ADDRMASK0_1 534 * Registers: MAC_ADDRMASK1_0 and MAC_ADDRMASK1_1 535 * Registers: MAC_ADDRMASK2_0 and MAC_ADDRMASK2_1 536 */ 537 538 /* No bitfields */ 539 540 /* 541 * MAC Receive Address Filter Hash Match Registers (Table 9-22) 542 * Registers: MAC_HASH0_0 through MAC_HASH7_0 543 * Registers: MAC_HASH0_1 through MAC_HASH7_1 544 * Registers: MAC_HASH0_2 through MAC_HASH7_2 545 */ 546 547 /* No bitfields */ 548 549 /* 550 * MAC Transmit Source Address Registers (Table 9-23) 551 * Register: MAC_ETHERNET_ADDR_0 552 * Register: MAC_ETHERNET_ADDR_1 553 * Register: MAC_ETHERNET_ADDR_2 554 */ 555 556 /* No bitfields */ 557 558 /* 559 * MAC Packet Type Configuration Register 560 * Register: MAC_TYPE_CFG_0 561 * Register: MAC_TYPE_CFG_1 562 * Register: MAC_TYPE_CFG_2 563 */ 564 565 #define S_TYPECFG_TYPESIZE _SB_MAKE64(16) 566 567 #define S_TYPECFG_TYPE0 _SB_MAKE64(0) 568 #define M_TYPECFG_TYPE0 _SB_MAKEMASK(16, S_TYPECFG_TYPE0) 569 #define V_TYPECFG_TYPE0(x) _SB_MAKEVALUE(x, S_TYPECFG_TYPE0) 570 #define G_TYPECFG_TYPE0(x) _SB_GETVALUE(x, S_TYPECFG_TYPE0, M_TYPECFG_TYPE0) 571 572 #define S_TYPECFG_TYPE1 _SB_MAKE64(0) 573 #define M_TYPECFG_TYPE1 _SB_MAKEMASK(16, S_TYPECFG_TYPE1) 574 #define V_TYPECFG_TYPE1(x) _SB_MAKEVALUE(x, S_TYPECFG_TYPE1) 575 #define G_TYPECFG_TYPE1(x) _SB_GETVALUE(x, S_TYPECFG_TYPE1, M_TYPECFG_TYPE1) 576 577 #define S_TYPECFG_TYPE2 _SB_MAKE64(0) 578 #define M_TYPECFG_TYPE2 _SB_MAKEMASK(16, S_TYPECFG_TYPE2) 579 #define V_TYPECFG_TYPE2(x) _SB_MAKEVALUE(x, S_TYPECFG_TYPE2) 580 #define G_TYPECFG_TYPE2(x) _SB_GETVALUE(x, S_TYPECFG_TYPE2, M_TYPECFG_TYPE2) 581 582 #define S_TYPECFG_TYPE3 _SB_MAKE64(0) 583 #define M_TYPECFG_TYPE3 _SB_MAKEMASK(16, S_TYPECFG_TYPE3) 584 #define V_TYPECFG_TYPE3(x) _SB_MAKEVALUE(x, S_TYPECFG_TYPE3) 585 #define G_TYPECFG_TYPE3(x) _SB_GETVALUE(x, S_TYPECFG_TYPE3, M_TYPECFG_TYPE3) 586 587 /* 588 * MAC Receive Address Filter Control Registers (Table 9-24) 589 * Register: MAC_ADFILTER_CFG_0 590 * Register: MAC_ADFILTER_CFG_1 591 * Register: MAC_ADFILTER_CFG_2 592 */ 593 594 #define M_MAC_ALLPKT_EN _SB_MAKEMASK1(0) 595 #define M_MAC_UCAST_EN _SB_MAKEMASK1(1) 596 #define M_MAC_UCAST_INV _SB_MAKEMASK1(2) 597 #define M_MAC_MCAST_EN _SB_MAKEMASK1(3) 598 #define M_MAC_MCAST_INV _SB_MAKEMASK1(4) 599 #define M_MAC_BCAST_EN _SB_MAKEMASK1(5) 600 #define M_MAC_DIRECT_INV _SB_MAKEMASK1(6) 601 #if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480) 602 #define M_MAC_ALLMCAST_EN _SB_MAKEMASK1(7) 603 #endif /* 1250 PASS2 || 112x PASS1 || 1480 */ 604 605 #define S_MAC_IPHDR_OFFSET _SB_MAKE64(8) 606 #define M_MAC_IPHDR_OFFSET _SB_MAKEMASK(8, S_MAC_IPHDR_OFFSET) 607 #define V_MAC_IPHDR_OFFSET(x) _SB_MAKEVALUE(x, S_MAC_IPHDR_OFFSET) 608 #define G_MAC_IPHDR_OFFSET(x) _SB_GETVALUE(x, S_MAC_IPHDR_OFFSET, M_MAC_IPHDR_OFFSET) 609 610 #if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480) 611 #define S_MAC_RX_CRC_OFFSET _SB_MAKE64(16) 612 #define M_MAC_RX_CRC_OFFSET _SB_MAKEMASK(8, S_MAC_RX_CRC_OFFSET) 613 #define V_MAC_RX_CRC_OFFSET(x) _SB_MAKEVALUE(x, S_MAC_RX_CRC_OFFSET) 614 #define G_MAC_RX_CRC_OFFSET(x) _SB_GETVALUE(x, S_MAC_RX_CRC_OFFSET, M_MAC_RX_CRC_OFFSET) 615 616 #define S_MAC_RX_PKT_OFFSET _SB_MAKE64(24) 617 #define M_MAC_RX_PKT_OFFSET _SB_MAKEMASK(8, S_MAC_RX_PKT_OFFSET) 618 #define V_MAC_RX_PKT_OFFSET(x) _SB_MAKEVALUE(x, S_MAC_RX_PKT_OFFSET) 619 #define G_MAC_RX_PKT_OFFSET(x) _SB_GETVALUE(x, S_MAC_RX_PKT_OFFSET, M_MAC_RX_PKT_OFFSET) 620 621 #define M_MAC_FWDPAUSE_EN _SB_MAKEMASK1(32) 622 #define M_MAC_VLAN_DET_EN _SB_MAKEMASK1(33) 623 624 #define S_MAC_RX_CH_MSN_SEL _SB_MAKE64(34) 625 #define M_MAC_RX_CH_MSN_SEL _SB_MAKEMASK(8, S_MAC_RX_CH_MSN_SEL) 626 #define V_MAC_RX_CH_MSN_SEL(x) _SB_MAKEVALUE(x, S_MAC_RX_CH_MSN_SEL) 627 #define G_MAC_RX_CH_MSN_SEL(x) _SB_GETVALUE(x, S_MAC_RX_CH_MSN_SEL, M_MAC_RX_CH_MSN_SEL) 628 #endif /* 1250 PASS3 || 112x PASS1 || 1480 */ 629 630 /* 631 * MAC Receive Channel Select Registers (Table 9-25) 632 */ 633 634 /* no bitfields */ 635 636 /* 637 * MAC MII Management Interface Registers (Table 9-26) 638 * Register: MAC_MDIO_0 639 * Register: MAC_MDIO_1 640 * Register: MAC_MDIO_2 641 */ 642 643 #define S_MAC_MDC 0 644 #define S_MAC_MDIO_DIR 1 645 #define S_MAC_MDIO_OUT 2 646 #define S_MAC_GENC 3 647 #define S_MAC_MDIO_IN 4 648 649 #define M_MAC_MDC _SB_MAKEMASK1(S_MAC_MDC) 650 #define M_MAC_MDIO_DIR _SB_MAKEMASK1(S_MAC_MDIO_DIR) 651 #define M_MAC_MDIO_DIR_INPUT _SB_MAKEMASK1(S_MAC_MDIO_DIR) 652 #define M_MAC_MDIO_OUT _SB_MAKEMASK1(S_MAC_MDIO_OUT) 653 #define M_MAC_GENC _SB_MAKEMASK1(S_MAC_GENC) 654 #define M_MAC_MDIO_IN _SB_MAKEMASK1(S_MAC_MDIO_IN) 655 656 #endif 657