1 /* 2 * This file is subject to the terms and conditions of the GNU General Public 3 * License. See the file "COPYING" in the main directory of this archive 4 * for more details. 5 * 6 * Copyright (C) 1994 - 2002 by Ralf Baechle 7 * Copyright (C) 1999, 2000, 2001 Silicon Graphics, Inc. 8 * Copyright (C) 2002 Maciej W. Rozycki 9 */ 10 #ifndef _ASM_PGTABLE_BITS_H 11 #define _ASM_PGTABLE_BITS_H 12 13 14 /* 15 * Note that we shift the lower 32bits of each EntryLo[01] entry 16 * 6 bits to the left. That way we can convert the PFN into the 17 * physical address by a single 'and' operation and gain 6 additional 18 * bits for storing information which isn't present in a normal 19 * MIPS page table. 20 * 21 * Similar to the Alpha port, we need to keep track of the ref 22 * and mod bits in software. We have a software "yeah you can read 23 * from this page" bit, and a hardware one which actually lets the 24 * process read from the page. On the same token we have a software 25 * writable bit and the real hardware one which actually lets the 26 * process write to the page, this keeps a mod bit via the hardware 27 * dirty bit. 28 * 29 * Certain revisions of the R4000 and R5000 have a bug where if a 30 * certain sequence occurs in the last 3 instructions of an executable 31 * page, and the following page is not mapped, the cpu can do 32 * unpredictable things. The code (when it is written) to deal with 33 * this problem will be in the update_mmu_cache() code for the r4k. 34 */ 35 #if defined(CONFIG_PHYS_ADDR_T_64BIT) && defined(CONFIG_CPU_MIPS32) 36 37 /* 38 * The following bits are implemented by the TLB hardware 39 */ 40 #define _PAGE_GLOBAL_SHIFT 0 41 #define _PAGE_GLOBAL (1 << _PAGE_GLOBAL_SHIFT) 42 #define _PAGE_VALID_SHIFT (_PAGE_GLOBAL_SHIFT + 1) 43 #define _PAGE_VALID (1 << _PAGE_VALID_SHIFT) 44 #define _PAGE_DIRTY_SHIFT (_PAGE_VALID_SHIFT + 1) 45 #define _PAGE_DIRTY (1 << _PAGE_DIRTY_SHIFT) 46 #define _CACHE_SHIFT (_PAGE_DIRTY_SHIFT + 1) 47 #define _CACHE_MASK (7 << _CACHE_SHIFT) 48 49 /* 50 * The following bits are implemented in software 51 */ 52 #define _PAGE_PRESENT_SHIFT (_CACHE_SHIFT + 3) 53 #define _PAGE_PRESENT (1 << _PAGE_PRESENT_SHIFT) 54 #define _PAGE_READ_SHIFT (_PAGE_PRESENT_SHIFT + 1) 55 #define _PAGE_READ (1 << _PAGE_READ_SHIFT) 56 #define _PAGE_WRITE_SHIFT (_PAGE_READ_SHIFT + 1) 57 #define _PAGE_WRITE (1 << _PAGE_WRITE_SHIFT) 58 #define _PAGE_ACCESSED_SHIFT (_PAGE_WRITE_SHIFT + 1) 59 #define _PAGE_ACCESSED (1 << _PAGE_ACCESSED_SHIFT) 60 #define _PAGE_MODIFIED_SHIFT (_PAGE_ACCESSED_SHIFT + 1) 61 #define _PAGE_MODIFIED (1 << _PAGE_MODIFIED_SHIFT) 62 63 #define _PFN_SHIFT (PAGE_SHIFT - 12 + _CACHE_SHIFT + 3) 64 65 #elif defined(CONFIG_CPU_R3000) || defined(CONFIG_CPU_TX39XX) 66 67 /* 68 * The following bits are implemented in software 69 */ 70 #define _PAGE_PRESENT_SHIFT (0) 71 #define _PAGE_PRESENT (1 << _PAGE_PRESENT_SHIFT) 72 #define _PAGE_READ_SHIFT (_PAGE_PRESENT_SHIFT + 1) 73 #define _PAGE_READ (1 << _PAGE_READ_SHIFT) 74 #define _PAGE_WRITE_SHIFT (_PAGE_READ_SHIFT + 1) 75 #define _PAGE_WRITE (1 << _PAGE_WRITE_SHIFT) 76 #define _PAGE_ACCESSED_SHIFT (_PAGE_WRITE_SHIFT + 1) 77 #define _PAGE_ACCESSED (1 << _PAGE_ACCESSED_SHIFT) 78 #define _PAGE_MODIFIED_SHIFT (_PAGE_ACCESSED_SHIFT + 1) 79 #define _PAGE_MODIFIED (1 << _PAGE_MODIFIED_SHIFT) 80 81 /* 82 * The following bits are implemented by the TLB hardware 83 */ 84 #define _PAGE_GLOBAL_SHIFT (_PAGE_MODIFIED_SHIFT + 4) 85 #define _PAGE_GLOBAL (1 << _PAGE_GLOBAL_SHIFT) 86 #define _PAGE_VALID_SHIFT (_PAGE_GLOBAL_SHIFT + 1) 87 #define _PAGE_VALID (1 << _PAGE_VALID_SHIFT) 88 #define _PAGE_DIRTY_SHIFT (_PAGE_VALID_SHIFT + 1) 89 #define _PAGE_DIRTY (1 << _PAGE_DIRTY_SHIFT) 90 #define _CACHE_UNCACHED_SHIFT (_PAGE_DIRTY_SHIFT + 1) 91 #define _CACHE_UNCACHED (1 << _CACHE_UNCACHED_SHIFT) 92 #define _CACHE_MASK _CACHE_UNCACHED 93 94 #define _PFN_SHIFT PAGE_SHIFT 95 96 #else 97 /* 98 * When using the RI/XI bit support, we have 13 bits of flags below 99 * the physical address. The RI/XI bits are placed such that a SRL 5 100 * can strip off the software bits, then a ROTR 2 can move the RI/XI 101 * into bits [63:62]. This also limits physical address to 56 bits, 102 * which is more than we need right now. 103 */ 104 105 /* 106 * The following bits are implemented in software 107 */ 108 #define _PAGE_PRESENT_SHIFT 0 109 #define _PAGE_PRESENT (1 << _PAGE_PRESENT_SHIFT) 110 #define _PAGE_READ_SHIFT (cpu_has_rixi ? _PAGE_PRESENT_SHIFT : _PAGE_PRESENT_SHIFT + 1) 111 #define _PAGE_READ ({BUG_ON(cpu_has_rixi); 1 << _PAGE_READ_SHIFT; }) 112 #define _PAGE_WRITE_SHIFT (_PAGE_READ_SHIFT + 1) 113 #define _PAGE_WRITE (1 << _PAGE_WRITE_SHIFT) 114 #define _PAGE_ACCESSED_SHIFT (_PAGE_WRITE_SHIFT + 1) 115 #define _PAGE_ACCESSED (1 << _PAGE_ACCESSED_SHIFT) 116 #define _PAGE_MODIFIED_SHIFT (_PAGE_ACCESSED_SHIFT + 1) 117 #define _PAGE_MODIFIED (1 << _PAGE_MODIFIED_SHIFT) 118 119 #ifdef CONFIG_MIPS_HUGE_TLB_SUPPORT 120 /* huge tlb page */ 121 #define _PAGE_HUGE_SHIFT (_PAGE_MODIFIED_SHIFT + 1) 122 #define _PAGE_HUGE (1 << _PAGE_HUGE_SHIFT) 123 #define _PAGE_SPLITTING_SHIFT (_PAGE_HUGE_SHIFT + 1) 124 #define _PAGE_SPLITTING (1 << _PAGE_SPLITTING_SHIFT) 125 #else 126 #define _PAGE_HUGE_SHIFT (_PAGE_MODIFIED_SHIFT) 127 #define _PAGE_HUGE ({BUG(); 1; }) /* Dummy value */ 128 #define _PAGE_SPLITTING_SHIFT (_PAGE_HUGE_SHIFT) 129 #define _PAGE_SPLITTING ({BUG(); 1; }) /* Dummy value */ 130 #endif 131 132 /* Page cannot be executed */ 133 #define _PAGE_NO_EXEC_SHIFT (cpu_has_rixi ? _PAGE_SPLITTING_SHIFT + 1 : _PAGE_SPLITTING_SHIFT) 134 #define _PAGE_NO_EXEC ({BUG_ON(!cpu_has_rixi); 1 << _PAGE_NO_EXEC_SHIFT; }) 135 136 /* Page cannot be read */ 137 #define _PAGE_NO_READ_SHIFT (cpu_has_rixi ? _PAGE_NO_EXEC_SHIFT + 1 : _PAGE_NO_EXEC_SHIFT) 138 #define _PAGE_NO_READ ({BUG_ON(!cpu_has_rixi); 1 << _PAGE_NO_READ_SHIFT; }) 139 140 #define _PAGE_GLOBAL_SHIFT (_PAGE_NO_READ_SHIFT + 1) 141 #define _PAGE_GLOBAL (1 << _PAGE_GLOBAL_SHIFT) 142 #define _PAGE_VALID_SHIFT (_PAGE_GLOBAL_SHIFT + 1) 143 #define _PAGE_VALID (1 << _PAGE_VALID_SHIFT) 144 #define _PAGE_DIRTY_SHIFT (_PAGE_VALID_SHIFT + 1) 145 #define _PAGE_DIRTY (1 << _PAGE_DIRTY_SHIFT) 146 #define _CACHE_SHIFT (_PAGE_DIRTY_SHIFT + 1) 147 #define _CACHE_MASK (7 << _CACHE_SHIFT) 148 149 #define _PFN_SHIFT (PAGE_SHIFT - 12 + _CACHE_SHIFT + 3) 150 151 #endif /* defined(CONFIG_PHYS_ADDR_T_64BIT && defined(CONFIG_CPU_MIPS32) */ 152 153 #define _PAGE_SILENT_READ _PAGE_VALID 154 #define _PAGE_SILENT_WRITE _PAGE_DIRTY 155 156 #define _PFN_MASK (~((1 << (_PFN_SHIFT)) - 1)) 157 158 #ifndef _PAGE_NO_READ 159 #define _PAGE_NO_READ ({BUG(); 0; }) 160 #define _PAGE_NO_READ_SHIFT ({BUG(); 0; }) 161 #endif 162 #ifndef _PAGE_NO_EXEC 163 #define _PAGE_NO_EXEC ({BUG(); 0; }) 164 #endif 165 166 167 #ifndef __ASSEMBLY__ 168 /* 169 * pte_to_entrylo converts a page table entry (PTE) into a Mips 170 * entrylo0/1 value. 171 */ 172 static inline uint64_t pte_to_entrylo(unsigned long pte_val) 173 { 174 if (cpu_has_rixi) { 175 int sa; 176 #ifdef CONFIG_32BIT 177 sa = 31 - _PAGE_NO_READ_SHIFT; 178 #else 179 sa = 63 - _PAGE_NO_READ_SHIFT; 180 #endif 181 /* 182 * C has no way to express that this is a DSRL 183 * _PAGE_NO_EXEC_SHIFT followed by a ROTR 2. Luckily 184 * in the fast path this is done in assembly 185 */ 186 return (pte_val >> _PAGE_GLOBAL_SHIFT) | 187 ((pte_val & (_PAGE_NO_EXEC | _PAGE_NO_READ)) << sa); 188 } 189 190 return pte_val >> _PAGE_GLOBAL_SHIFT; 191 } 192 #endif 193 194 /* 195 * Cache attributes 196 */ 197 #if defined(CONFIG_CPU_R3000) || defined(CONFIG_CPU_TX39XX) 198 199 #define _CACHE_CACHABLE_NONCOHERENT 0 200 #define _CACHE_UNCACHED_ACCELERATED _CACHE_UNCACHED 201 202 #elif defined(CONFIG_CPU_SB1) 203 204 /* No penalty for being coherent on the SB1, so just 205 use it for "noncoherent" spaces, too. Shouldn't hurt. */ 206 207 #define _CACHE_CACHABLE_NONCOHERENT (5<<_CACHE_SHIFT) 208 209 #elif defined(CONFIG_CPU_LOONGSON3) 210 211 /* Using COHERENT flag for NONCOHERENT doesn't hurt. */ 212 213 #define _CACHE_CACHABLE_NONCOHERENT (3<<_CACHE_SHIFT) /* LOONGSON */ 214 #define _CACHE_CACHABLE_COHERENT (3<<_CACHE_SHIFT) /* LOONGSON-3 */ 215 216 #elif defined(CONFIG_MACH_JZ4740) 217 218 /* Ingenic uses the WA bit to achieve write-combine memory writes */ 219 #define _CACHE_UNCACHED_ACCELERATED (1<<_CACHE_SHIFT) 220 221 #endif 222 223 #ifndef _CACHE_CACHABLE_NO_WA 224 #define _CACHE_CACHABLE_NO_WA (0<<_CACHE_SHIFT) 225 #endif 226 #ifndef _CACHE_CACHABLE_WA 227 #define _CACHE_CACHABLE_WA (1<<_CACHE_SHIFT) 228 #endif 229 #ifndef _CACHE_UNCACHED 230 #define _CACHE_UNCACHED (2<<_CACHE_SHIFT) 231 #endif 232 #ifndef _CACHE_CACHABLE_NONCOHERENT 233 #define _CACHE_CACHABLE_NONCOHERENT (3<<_CACHE_SHIFT) 234 #endif 235 #ifndef _CACHE_CACHABLE_CE 236 #define _CACHE_CACHABLE_CE (4<<_CACHE_SHIFT) 237 #endif 238 #ifndef _CACHE_CACHABLE_COW 239 #define _CACHE_CACHABLE_COW (5<<_CACHE_SHIFT) 240 #endif 241 #ifndef _CACHE_CACHABLE_CUW 242 #define _CACHE_CACHABLE_CUW (6<<_CACHE_SHIFT) 243 #endif 244 #ifndef _CACHE_UNCACHED_ACCELERATED 245 #define _CACHE_UNCACHED_ACCELERATED (7<<_CACHE_SHIFT) 246 #endif 247 248 #define __READABLE (_PAGE_SILENT_READ | _PAGE_ACCESSED | (cpu_has_rixi ? 0 : _PAGE_READ)) 249 #define __WRITEABLE (_PAGE_SILENT_WRITE | _PAGE_WRITE | _PAGE_MODIFIED) 250 251 #define _PAGE_CHG_MASK (_PAGE_ACCESSED | _PAGE_MODIFIED | \ 252 _PFN_MASK | _CACHE_MASK) 253 254 #endif /* _ASM_PGTABLE_BITS_H */ 255