1 /* 2 * This file is subject to the terms and conditions of the GNU General Public 3 * License. See the file "COPYING" in the main directory of this archive 4 * for more details. 5 * 6 * Copyright (C) 1994 - 2002 by Ralf Baechle 7 * Copyright (C) 1999, 2000, 2001 Silicon Graphics, Inc. 8 * Copyright (C) 2002 Maciej W. Rozycki 9 */ 10 #ifndef _ASM_PGTABLE_BITS_H 11 #define _ASM_PGTABLE_BITS_H 12 13 14 /* 15 * Note that we shift the lower 32bits of each EntryLo[01] entry 16 * 6 bits to the left. That way we can convert the PFN into the 17 * physical address by a single 'and' operation and gain 6 additional 18 * bits for storing information which isn't present in a normal 19 * MIPS page table. 20 * 21 * Similar to the Alpha port, we need to keep track of the ref 22 * and mod bits in software. We have a software "yeah you can read 23 * from this page" bit, and a hardware one which actually lets the 24 * process read from the page. On the same token we have a software 25 * writable bit and the real hardware one which actually lets the 26 * process write to the page, this keeps a mod bit via the hardware 27 * dirty bit. 28 * 29 * Certain revisions of the R4000 and R5000 have a bug where if a 30 * certain sequence occurs in the last 3 instructions of an executable 31 * page, and the following page is not mapped, the cpu can do 32 * unpredictable things. The code (when it is written) to deal with 33 * this problem will be in the update_mmu_cache() code for the r4k. 34 */ 35 #if defined(CONFIG_PHYS_ADDR_T_64BIT) && defined(CONFIG_CPU_MIPS32) 36 37 /* 38 * The following bits are directly used by the TLB hardware 39 */ 40 #define _PAGE_GLOBAL_SHIFT 0 41 #define _PAGE_GLOBAL (1 << _PAGE_GLOBAL_SHIFT) 42 #define _PAGE_VALID_SHIFT (_PAGE_GLOBAL_SHIFT + 1) 43 #define _PAGE_VALID (1 << _PAGE_VALID_SHIFT) 44 #define _PAGE_DIRTY_SHIFT (_PAGE_VALID_SHIFT + 1) 45 #define _PAGE_DIRTY (1 << _PAGE_DIRTY_SHIFT) 46 #define _CACHE_SHIFT (_PAGE_DIRTY_SHIFT + 1) 47 #define _CACHE_MASK (7 << _CACHE_SHIFT) 48 49 /* 50 * The following bits are implemented in software 51 */ 52 #define _PAGE_PRESENT_SHIFT (_CACHE_SHIFT + 3) 53 #define _PAGE_PRESENT (1 << _PAGE_PRESENT_SHIFT) 54 #define _PAGE_READ_SHIFT (_PAGE_PRESENT_SHIFT + 1) 55 #define _PAGE_READ (1 << _PAGE_READ_SHIFT) 56 #define _PAGE_WRITE_SHIFT (_PAGE_READ_SHIFT + 1) 57 #define _PAGE_WRITE (1 << _PAGE_WRITE_SHIFT) 58 #define _PAGE_ACCESSED_SHIFT (_PAGE_WRITE_SHIFT + 1) 59 #define _PAGE_ACCESSED (1 << _PAGE_ACCESSED_SHIFT) 60 #define _PAGE_MODIFIED_SHIFT (_PAGE_ACCESSED_SHIFT + 1) 61 #define _PAGE_MODIFIED (1 << _PAGE_MODIFIED_SHIFT) 62 63 #define _PAGE_SILENT_READ _PAGE_VALID 64 #define _PAGE_SILENT_WRITE _PAGE_DIRTY 65 66 #define _PFN_SHIFT (PAGE_SHIFT - 12 + _CACHE_SHIFT + 3) 67 68 #elif defined(CONFIG_CPU_R3000) || defined(CONFIG_CPU_TX39XX) 69 70 /* 71 * The following are implemented by software 72 */ 73 #define _PAGE_PRESENT_SHIFT 0 74 #define _PAGE_PRESENT (1 << _PAGE_PRESENT_SHIFT) 75 #define _PAGE_READ_SHIFT 1 76 #define _PAGE_READ (1 << _PAGE_READ_SHIFT) 77 #define _PAGE_WRITE_SHIFT 2 78 #define _PAGE_WRITE (1 << _PAGE_WRITE_SHIFT) 79 #define _PAGE_ACCESSED_SHIFT 3 80 #define _PAGE_ACCESSED (1 << _PAGE_ACCESSED_SHIFT) 81 #define _PAGE_MODIFIED_SHIFT 4 82 #define _PAGE_MODIFIED (1 << _PAGE_MODIFIED_SHIFT) 83 84 /* 85 * And these are the hardware TLB bits 86 */ 87 #define _PAGE_GLOBAL_SHIFT 8 88 #define _PAGE_GLOBAL (1 << _PAGE_GLOBAL_SHIFT) 89 #define _PAGE_VALID_SHIFT 9 90 #define _PAGE_VALID (1 << _PAGE_VALID_SHIFT) 91 #define _PAGE_SILENT_READ (1 << _PAGE_VALID_SHIFT) /* synonym */ 92 #define _PAGE_DIRTY_SHIFT 10 93 #define _PAGE_DIRTY (1 << _PAGE_DIRTY_SHIFT) 94 #define _PAGE_SILENT_WRITE (1 << _PAGE_DIRTY_SHIFT) 95 #define _CACHE_UNCACHED_SHIFT 11 96 #define _CACHE_UNCACHED (1 << _CACHE_UNCACHED_SHIFT) 97 #define _CACHE_MASK (1 << _CACHE_UNCACHED_SHIFT) 98 99 #else /* 'Normal' r4K case */ 100 /* 101 * When using the RI/XI bit support, we have 13 bits of flags below 102 * the physical address. The RI/XI bits are placed such that a SRL 5 103 * can strip off the software bits, then a ROTR 2 can move the RI/XI 104 * into bits [63:62]. This also limits physical address to 56 bits, 105 * which is more than we need right now. 106 */ 107 108 /* 109 * The following bits are implemented in software 110 * 111 * _PAGE_READ / _PAGE_READ_SHIFT should be unused if cpu_has_rixi. 112 */ 113 #define _PAGE_PRESENT_SHIFT (0) 114 #define _PAGE_PRESENT (1 << _PAGE_PRESENT_SHIFT) 115 #define _PAGE_READ_SHIFT (cpu_has_rixi ? _PAGE_PRESENT_SHIFT : _PAGE_PRESENT_SHIFT + 1) 116 #define _PAGE_READ ({BUG_ON(cpu_has_rixi); 1 << _PAGE_READ_SHIFT; }) 117 #define _PAGE_WRITE_SHIFT (_PAGE_READ_SHIFT + 1) 118 #define _PAGE_WRITE (1 << _PAGE_WRITE_SHIFT) 119 #define _PAGE_ACCESSED_SHIFT (_PAGE_WRITE_SHIFT + 1) 120 #define _PAGE_ACCESSED (1 << _PAGE_ACCESSED_SHIFT) 121 #define _PAGE_MODIFIED_SHIFT (_PAGE_ACCESSED_SHIFT + 1) 122 #define _PAGE_MODIFIED (1 << _PAGE_MODIFIED_SHIFT) 123 124 #ifdef CONFIG_MIPS_HUGE_TLB_SUPPORT 125 /* huge tlb page */ 126 #define _PAGE_HUGE_SHIFT (_PAGE_MODIFIED_SHIFT + 1) 127 #define _PAGE_HUGE (1 << _PAGE_HUGE_SHIFT) 128 #else 129 #define _PAGE_HUGE_SHIFT (_PAGE_MODIFIED_SHIFT) 130 #define _PAGE_HUGE ({BUG(); 1; }) /* Dummy value */ 131 #endif 132 133 #ifdef CONFIG_MIPS_HUGE_TLB_SUPPORT 134 /* huge tlb page */ 135 #define _PAGE_SPLITTING_SHIFT (_PAGE_HUGE_SHIFT + 1) 136 #define _PAGE_SPLITTING (1 << _PAGE_SPLITTING_SHIFT) 137 #else 138 #define _PAGE_SPLITTING_SHIFT (_PAGE_HUGE_SHIFT) 139 #define _PAGE_SPLITTING ({BUG(); 1; }) /* Dummy value */ 140 #endif 141 142 /* Page cannot be executed */ 143 #define _PAGE_NO_EXEC_SHIFT (cpu_has_rixi ? _PAGE_SPLITTING_SHIFT + 1 : _PAGE_SPLITTING_SHIFT) 144 #define _PAGE_NO_EXEC ({BUG_ON(!cpu_has_rixi); 1 << _PAGE_NO_EXEC_SHIFT; }) 145 146 /* Page cannot be read */ 147 #define _PAGE_NO_READ_SHIFT (cpu_has_rixi ? _PAGE_NO_EXEC_SHIFT + 1 : _PAGE_NO_EXEC_SHIFT) 148 #define _PAGE_NO_READ ({BUG_ON(!cpu_has_rixi); 1 << _PAGE_NO_READ_SHIFT; }) 149 150 #define _PAGE_GLOBAL_SHIFT (_PAGE_NO_READ_SHIFT + 1) 151 #define _PAGE_GLOBAL (1 << _PAGE_GLOBAL_SHIFT) 152 153 #define _PAGE_VALID_SHIFT (_PAGE_GLOBAL_SHIFT + 1) 154 #define _PAGE_VALID (1 << _PAGE_VALID_SHIFT) 155 /* synonym */ 156 #define _PAGE_SILENT_READ (_PAGE_VALID) 157 158 /* The MIPS dirty bit */ 159 #define _PAGE_DIRTY_SHIFT (_PAGE_VALID_SHIFT + 1) 160 #define _PAGE_DIRTY (1 << _PAGE_DIRTY_SHIFT) 161 #define _PAGE_SILENT_WRITE (_PAGE_DIRTY) 162 163 #define _CACHE_SHIFT (_PAGE_DIRTY_SHIFT + 1) 164 #define _CACHE_MASK (7 << _CACHE_SHIFT) 165 166 #define _PFN_SHIFT (PAGE_SHIFT - 12 + _CACHE_SHIFT + 3) 167 168 #endif /* defined(CONFIG_PHYS_ADDR_T_64BIT && defined(CONFIG_CPU_MIPS32) */ 169 170 #ifndef _PFN_SHIFT 171 #define _PFN_SHIFT PAGE_SHIFT 172 #endif 173 #define _PFN_MASK (~((1 << (_PFN_SHIFT)) - 1)) 174 175 #ifndef _PAGE_NO_READ 176 #define _PAGE_NO_READ ({BUG(); 0; }) 177 #define _PAGE_NO_READ_SHIFT ({BUG(); 0; }) 178 #endif 179 #ifndef _PAGE_NO_EXEC 180 #define _PAGE_NO_EXEC ({BUG(); 0; }) 181 #endif 182 #ifndef _PAGE_GLOBAL_SHIFT 183 #define _PAGE_GLOBAL_SHIFT ilog2(_PAGE_GLOBAL) 184 #endif 185 186 187 #ifndef __ASSEMBLY__ 188 /* 189 * pte_to_entrylo converts a page table entry (PTE) into a Mips 190 * entrylo0/1 value. 191 */ 192 static inline uint64_t pte_to_entrylo(unsigned long pte_val) 193 { 194 if (cpu_has_rixi) { 195 int sa; 196 #ifdef CONFIG_32BIT 197 sa = 31 - _PAGE_NO_READ_SHIFT; 198 #else 199 sa = 63 - _PAGE_NO_READ_SHIFT; 200 #endif 201 /* 202 * C has no way to express that this is a DSRL 203 * _PAGE_NO_EXEC_SHIFT followed by a ROTR 2. Luckily 204 * in the fast path this is done in assembly 205 */ 206 return (pte_val >> _PAGE_GLOBAL_SHIFT) | 207 ((pte_val & (_PAGE_NO_EXEC | _PAGE_NO_READ)) << sa); 208 } 209 210 return pte_val >> _PAGE_GLOBAL_SHIFT; 211 } 212 #endif 213 214 /* 215 * Cache attributes 216 */ 217 #if defined(CONFIG_CPU_R3000) || defined(CONFIG_CPU_TX39XX) 218 219 #define _CACHE_CACHABLE_NONCOHERENT 0 220 #define _CACHE_UNCACHED_ACCELERATED _CACHE_UNCACHED 221 222 #elif defined(CONFIG_CPU_SB1) 223 224 /* No penalty for being coherent on the SB1, so just 225 use it for "noncoherent" spaces, too. Shouldn't hurt. */ 226 227 #define _CACHE_CACHABLE_NONCOHERENT (5<<_CACHE_SHIFT) 228 229 #elif defined(CONFIG_CPU_LOONGSON3) 230 231 /* Using COHERENT flag for NONCOHERENT doesn't hurt. */ 232 233 #define _CACHE_CACHABLE_NONCOHERENT (3<<_CACHE_SHIFT) /* LOONGSON */ 234 #define _CACHE_CACHABLE_COHERENT (3<<_CACHE_SHIFT) /* LOONGSON-3 */ 235 236 #elif defined(CONFIG_MACH_JZ4740) 237 238 /* Ingenic uses the WA bit to achieve write-combine memory writes */ 239 #define _CACHE_UNCACHED_ACCELERATED (1<<_CACHE_SHIFT) 240 241 #endif 242 243 #ifndef _CACHE_CACHABLE_NO_WA 244 #define _CACHE_CACHABLE_NO_WA (0<<_CACHE_SHIFT) 245 #endif 246 #ifndef _CACHE_CACHABLE_WA 247 #define _CACHE_CACHABLE_WA (1<<_CACHE_SHIFT) 248 #endif 249 #ifndef _CACHE_UNCACHED 250 #define _CACHE_UNCACHED (2<<_CACHE_SHIFT) 251 #endif 252 #ifndef _CACHE_CACHABLE_NONCOHERENT 253 #define _CACHE_CACHABLE_NONCOHERENT (3<<_CACHE_SHIFT) 254 #endif 255 #ifndef _CACHE_CACHABLE_CE 256 #define _CACHE_CACHABLE_CE (4<<_CACHE_SHIFT) 257 #endif 258 #ifndef _CACHE_CACHABLE_COW 259 #define _CACHE_CACHABLE_COW (5<<_CACHE_SHIFT) 260 #endif 261 #ifndef _CACHE_CACHABLE_CUW 262 #define _CACHE_CACHABLE_CUW (6<<_CACHE_SHIFT) 263 #endif 264 #ifndef _CACHE_UNCACHED_ACCELERATED 265 #define _CACHE_UNCACHED_ACCELERATED (7<<_CACHE_SHIFT) 266 #endif 267 268 #define __READABLE (_PAGE_SILENT_READ | _PAGE_ACCESSED | (cpu_has_rixi ? 0 : _PAGE_READ)) 269 #define __WRITEABLE (_PAGE_WRITE | _PAGE_SILENT_WRITE | _PAGE_MODIFIED) 270 271 #define _PAGE_CHG_MASK (_PFN_MASK | _PAGE_ACCESSED | _PAGE_MODIFIED | _CACHE_MASK) 272 273 #endif /* _ASM_PGTABLE_BITS_H */ 274