1 /* 2 * This file is subject to the terms and conditions of the GNU General Public 3 * License. See the file "COPYING" in the main directory of this archive 4 * for more details. 5 * 6 * Copyright (C) 1994, 95, 96, 97, 98, 99, 2000, 2003 Ralf Baechle 7 * Copyright (C) 1999, 2000, 2001 Silicon Graphics, Inc. 8 */ 9 #ifndef _ASM_PGTABLE_32_H 10 #define _ASM_PGTABLE_32_H 11 12 #include <asm/addrspace.h> 13 #include <asm/page.h> 14 15 #include <linux/linkage.h> 16 #include <asm/cachectl.h> 17 #include <asm/fixmap.h> 18 19 #include <asm-generic/pgtable-nopmd.h> 20 21 #ifdef CONFIG_HIGHMEM 22 #include <asm/highmem.h> 23 #endif 24 25 /* 26 * Regarding 32-bit MIPS huge page support (and the tradeoff it entails): 27 * 28 * We use the same huge page sizes as 64-bit MIPS. Assuming a 4KB page size, 29 * our 2-level table layout would normally have a PGD entry cover a contiguous 30 * 4MB virtual address region (pointing to a 4KB PTE page of 1,024 32-bit pte_t 31 * pointers, each pointing to a 4KB physical page). The problem is that 4MB, 32 * spanning both halves of a TLB EntryLo0,1 pair, requires 2MB hardware page 33 * support, not one of the standard supported sizes (1MB,4MB,16MB,...). 34 * To correct for this, when huge pages are enabled, we halve the number of 35 * pointers a PTE page holds, making its last half go to waste. Correspondingly, 36 * we double the number of PGD pages. Overall, page table memory overhead 37 * increases to match 64-bit MIPS, but PTE lookups remain CPU cache-friendly. 38 * 39 * NOTE: We don't yet support huge pages if extended-addressing is enabled 40 * (i.e. EVA, XPA, 36-bit Alchemy/Netlogic). 41 */ 42 43 extern int temp_tlb_entry; 44 45 /* 46 * - add_temporary_entry() add a temporary TLB entry. We use TLB entries 47 * starting at the top and working down. This is for populating the 48 * TLB before trap_init() puts the TLB miss handler in place. It 49 * should be used only for entries matching the actual page tables, 50 * to prevent inconsistencies. 51 */ 52 extern int add_temporary_entry(unsigned long entrylo0, unsigned long entrylo1, 53 unsigned long entryhi, unsigned long pagemask); 54 55 /* 56 * Basically we have the same two-level (which is the logical three level 57 * Linux page table layout folded) page tables as the i386. Some day 58 * when we have proper page coloring support we can have a 1% quicker 59 * tlb refill handling mechanism, but for now it is a bit slower but 60 * works even with the cache aliasing problem the R4k and above have. 61 */ 62 63 /* PGDIR_SHIFT determines what a third-level page table entry can map */ 64 #if defined(CONFIG_MIPS_HUGE_TLB_SUPPORT) && !defined(CONFIG_PHYS_ADDR_T_64BIT) 65 # define PGDIR_SHIFT (2 * PAGE_SHIFT - PTE_T_LOG2 - 1) 66 #else 67 # define PGDIR_SHIFT (2 * PAGE_SHIFT - PTE_T_LOG2) 68 #endif 69 70 #define PGDIR_SIZE (1UL << PGDIR_SHIFT) 71 #define PGDIR_MASK (~(PGDIR_SIZE-1)) 72 73 /* 74 * Entries per page directory level: we use two-level, so 75 * we don't really have any PUD/PMD directory physically. 76 */ 77 #if defined(CONFIG_MIPS_HUGE_TLB_SUPPORT) && !defined(CONFIG_PHYS_ADDR_T_64BIT) 78 # define __PGD_TABLE_ORDER (32 - 3 * PAGE_SHIFT + PGD_T_LOG2 + PTE_T_LOG2 + 1) 79 #else 80 # define __PGD_TABLE_ORDER (32 - 3 * PAGE_SHIFT + PGD_T_LOG2 + PTE_T_LOG2) 81 #endif 82 83 #define PGD_TABLE_ORDER (__PGD_TABLE_ORDER >= 0 ? __PGD_TABLE_ORDER : 0) 84 #define PUD_TABLE_ORDER aieeee_attempt_to_allocate_pud 85 #define PMD_TABLE_ORDER aieeee_attempt_to_allocate_pmd 86 87 #define PTRS_PER_PGD (USER_PTRS_PER_PGD * 2) 88 #if defined(CONFIG_MIPS_HUGE_TLB_SUPPORT) && !defined(CONFIG_PHYS_ADDR_T_64BIT) 89 # define PTRS_PER_PTE (PAGE_SIZE / sizeof(pte_t) / 2) 90 #else 91 # define PTRS_PER_PTE (PAGE_SIZE / sizeof(pte_t)) 92 #endif 93 94 #define USER_PTRS_PER_PGD (0x80000000UL/PGDIR_SIZE) 95 96 #define VMALLOC_START MAP_BASE 97 98 #define PKMAP_END ((FIXADDR_START) & ~((LAST_PKMAP << PAGE_SHIFT)-1)) 99 #define PKMAP_BASE (PKMAP_END - PAGE_SIZE * LAST_PKMAP) 100 101 #ifdef CONFIG_HIGHMEM 102 # define VMALLOC_END (PKMAP_BASE-2*PAGE_SIZE) 103 #else 104 # define VMALLOC_END (FIXADDR_START-2*PAGE_SIZE) 105 #endif 106 107 extern void load_pgd(unsigned long pg_dir); 108 109 extern pte_t invalid_pte_table[PTRS_PER_PTE]; 110 111 /* 112 * Empty pgd/pmd entries point to the invalid_pte_table. 113 */ 114 static inline int pmd_none(pmd_t pmd) 115 { 116 return pmd_val(pmd) == (unsigned long) invalid_pte_table; 117 } 118 119 static inline int pmd_bad(pmd_t pmd) 120 { 121 #ifdef CONFIG_MIPS_HUGE_TLB_SUPPORT 122 /* pmd_leaf(pmd) but inline */ 123 if (unlikely(pmd_val(pmd) & _PAGE_HUGE)) 124 return 0; 125 #endif 126 127 if (unlikely(pmd_val(pmd) & ~PAGE_MASK)) 128 return 1; 129 130 return 0; 131 } 132 133 static inline int pmd_present(pmd_t pmd) 134 { 135 return pmd_val(pmd) != (unsigned long) invalid_pte_table; 136 } 137 138 static inline void pmd_clear(pmd_t *pmdp) 139 { 140 pmd_val(*pmdp) = ((unsigned long) invalid_pte_table); 141 } 142 143 #if defined(CONFIG_XPA) 144 145 #define MAX_POSSIBLE_PHYSMEM_BITS 40 146 #define pte_pfn(x) (((unsigned long)((x).pte_high >> PFN_PTE_SHIFT)) | (unsigned long)((x).pte_low << _PAGE_PRESENT_SHIFT)) 147 static inline pte_t 148 pfn_pte(unsigned long pfn, pgprot_t prot) 149 { 150 pte_t pte; 151 152 pte.pte_low = (pfn >> _PAGE_PRESENT_SHIFT) | 153 (pgprot_val(prot) & ~_PFNX_MASK); 154 pte.pte_high = (pfn << PFN_PTE_SHIFT) | 155 (pgprot_val(prot) & ~_PFN_MASK); 156 return pte; 157 } 158 159 #elif defined(CONFIG_PHYS_ADDR_T_64BIT) && defined(CONFIG_CPU_MIPS32) 160 161 #define MAX_POSSIBLE_PHYSMEM_BITS 36 162 #define pte_pfn(x) ((unsigned long)((x).pte_high >> 6)) 163 164 static inline pte_t pfn_pte(unsigned long pfn, pgprot_t prot) 165 { 166 pte_t pte; 167 168 pte.pte_high = (pfn << 6) | (pgprot_val(prot) & 0x3f); 169 pte.pte_low = pgprot_val(prot); 170 171 return pte; 172 } 173 174 #else 175 176 #define MAX_POSSIBLE_PHYSMEM_BITS 32 177 #define pte_pfn(x) ((unsigned long)((x).pte >> PFN_PTE_SHIFT)) 178 #define pfn_pte(pfn, prot) __pte(((unsigned long long)(pfn) << PFN_PTE_SHIFT) | pgprot_val(prot)) 179 #define pfn_pmd(pfn, prot) __pmd(((unsigned long long)(pfn) << PFN_PTE_SHIFT) | pgprot_val(prot)) 180 #endif /* defined(CONFIG_PHYS_ADDR_T_64BIT) && defined(CONFIG_CPU_MIPS32) */ 181 182 #define pte_page(x) pfn_to_page(pte_pfn(x)) 183 184 /* 185 * Encode/decode swap entries and swap PTEs. Swap PTEs are all PTEs that 186 * are !pte_none() && !pte_present(). 187 */ 188 #if defined(CONFIG_CPU_R3K_TLB) 189 190 /* 191 * Format of swap PTEs: 192 * 193 * 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 194 * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 195 * <----------- offset ------------> < type -> V G E 0 0 0 0 0 0 P 196 * 197 * E is the exclusive marker that is not stored in swap entries. 198 * _PAGE_PRESENT (P), _PAGE_VALID (V) and_PAGE_GLOBAL (G) have to remain 199 * unused. 200 */ 201 #define __swp_type(x) (((x).val >> 10) & 0x1f) 202 #define __swp_offset(x) ((x).val >> 15) 203 #define __swp_entry(type, offset) ((swp_entry_t) { (((type) & 0x1f) << 10) | ((offset) << 15) }) 204 #define __pte_to_swp_entry(pte) ((swp_entry_t) { pte_val(pte) }) 205 #define __swp_entry_to_pte(x) ((pte_t) { (x).val }) 206 207 /* We borrow bit 7 to store the exclusive marker in swap PTEs. */ 208 #define _PAGE_SWP_EXCLUSIVE (1 << 7) 209 210 #else 211 212 #if defined(CONFIG_XPA) 213 214 /* 215 * Format of swap PTEs: 216 * 217 * 6 6 6 6 5 5 5 5 5 5 5 5 5 5 4 4 4 4 4 4 4 4 4 4 3 3 3 3 3 3 3 3 218 * 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 219 * 0 0 0 0 0 0 E P <------------------ zeroes -------------------> 220 * 221 * 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 222 * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 223 * <----------------- offset ------------------> < type -> V G 0 0 224 * 225 * E is the exclusive marker that is not stored in swap entries. 226 * _PAGE_PRESENT (P), _PAGE_VALID (V) and_PAGE_GLOBAL (G) have to remain 227 * unused. 228 */ 229 #define __swp_type(x) (((x).val >> 4) & 0x1f) 230 #define __swp_offset(x) ((x).val >> 9) 231 #define __swp_entry(type, offset) ((swp_entry_t) { (((type) & 0x1f) << 4) | ((offset) << 9) }) 232 #define __pte_to_swp_entry(pte) ((swp_entry_t) { (pte).pte_high }) 233 #define __swp_entry_to_pte(x) ((pte_t) { 0, (x).val }) 234 235 /* 236 * We borrow bit 57 (bit 25 in the low PTE) to store the exclusive marker in 237 * swap PTEs. 238 */ 239 #define _PAGE_SWP_EXCLUSIVE (1 << 25) 240 241 #elif defined(CONFIG_PHYS_ADDR_T_64BIT) && defined(CONFIG_CPU_MIPS32) 242 243 /* 244 * Format of swap PTEs: 245 * 246 * 6 6 6 6 5 5 5 5 5 5 5 5 5 5 4 4 4 4 4 4 4 4 4 4 3 3 3 3 3 3 3 3 247 * 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 248 * <------------------ zeroes -------------------> E P 0 0 0 0 0 0 249 * 250 * 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 251 * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 252 * <------------------- offset --------------------> < type -> V G 253 * 254 * E is the exclusive marker that is not stored in swap entries. 255 * _PAGE_PRESENT (P), _PAGE_VALID (V) and_PAGE_GLOBAL (G) have to remain 256 * unused. 257 */ 258 #define __swp_type(x) (((x).val >> 2) & 0x1f) 259 #define __swp_offset(x) ((x).val >> 7) 260 #define __swp_entry(type, offset) ((swp_entry_t) { (((type) & 0x1f) << 2) | ((offset) << 7) }) 261 #define __pte_to_swp_entry(pte) ((swp_entry_t) { (pte).pte_high }) 262 #define __swp_entry_to_pte(x) ((pte_t) { 0, (x).val }) 263 264 /* 265 * We borrow bit 39 (bit 7 in the low PTE) to store the exclusive marker in swap 266 * PTEs. 267 */ 268 #define _PAGE_SWP_EXCLUSIVE (1 << 7) 269 270 #else 271 /* 272 * Format of swap PTEs: 273 * 274 * 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 275 * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 276 * <------------- offset --------------> < type -> 0 0 0 0 0 0 E P 277 * 278 * E is the exclusive marker that is not stored in swap entries. 279 * _PAGE_PRESENT (P), _PAGE_VALID (V) and_PAGE_GLOBAL (G) have to remain 280 * unused. The location of V and G varies. 281 */ 282 #define __swp_type(x) (((x).val >> 8) & 0x1f) 283 #define __swp_offset(x) ((x).val >> 13) 284 #define __swp_entry(type, offset) ((swp_entry_t) { ((type) << 8) | ((offset) << 13) }) 285 #define __pte_to_swp_entry(pte) ((swp_entry_t) { pte_val(pte) }) 286 #define __swp_entry_to_pte(x) ((pte_t) { (x).val }) 287 288 /* We borrow bit 1 to store the exclusive marker in swap PTEs. */ 289 #define _PAGE_SWP_EXCLUSIVE (1 << 1) 290 291 #endif /* defined(CONFIG_PHYS_ADDR_T_64BIT) && defined(CONFIG_CPU_MIPS32) */ 292 293 #endif /* defined(CONFIG_CPU_R3K_TLB) */ 294 295 #endif /* _ASM_PGTABLE_32_H */ 296