xref: /linux/arch/mips/include/asm/perf_event.h (revision 14f7001284185bffeb796a181664906f7160f593) 
1*14f70012SDeng-Cheng Zhu /*
2*14f70012SDeng-Cheng Zhu  * linux/arch/mips/include/asm/perf_event.h
3*14f70012SDeng-Cheng Zhu  *
4*14f70012SDeng-Cheng Zhu  * Copyright (C) 2010 MIPS Technologies, Inc.
5*14f70012SDeng-Cheng Zhu  * Author: Deng-Cheng Zhu
6*14f70012SDeng-Cheng Zhu  *
7*14f70012SDeng-Cheng Zhu  * This program is free software; you can redistribute it and/or modify
8*14f70012SDeng-Cheng Zhu  * it under the terms of the GNU General Public License version 2 as
9*14f70012SDeng-Cheng Zhu  * published by the Free Software Foundation.
10*14f70012SDeng-Cheng Zhu  */
11*14f70012SDeng-Cheng Zhu 
12*14f70012SDeng-Cheng Zhu #ifndef __MIPS_PERF_EVENT_H__
13*14f70012SDeng-Cheng Zhu #define __MIPS_PERF_EVENT_H__
14*14f70012SDeng-Cheng Zhu 
15*14f70012SDeng-Cheng Zhu /*
16*14f70012SDeng-Cheng Zhu  * MIPS performance counters do not raise NMI upon overflow, a regular
17*14f70012SDeng-Cheng Zhu  * interrupt will be signaled. Hence we can do the pending perf event
18*14f70012SDeng-Cheng Zhu  * work at the tail of the irq handler.
19*14f70012SDeng-Cheng Zhu  */
20*14f70012SDeng-Cheng Zhu static inline void
21*14f70012SDeng-Cheng Zhu set_perf_event_pending(void)
22*14f70012SDeng-Cheng Zhu {
23*14f70012SDeng-Cheng Zhu }
24*14f70012SDeng-Cheng Zhu 
25*14f70012SDeng-Cheng Zhu #endif /* __MIPS_PERF_EVENT_H__ */
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