1 /***********************license start*************** 2 * Author: Cavium Networks 3 * 4 * Contact: support@caviumnetworks.com 5 * This file is part of the OCTEON SDK 6 * 7 * Copyright (c) 2003-2008 Cavium Networks 8 * 9 * This file is free software; you can redistribute it and/or modify 10 * it under the terms of the GNU General Public License, Version 2, as 11 * published by the Free Software Foundation. 12 * 13 * This file is distributed in the hope that it will be useful, but 14 * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty 15 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or 16 * NONINFRINGEMENT. See the GNU General Public License for more 17 * details. 18 * 19 * You should have received a copy of the GNU General Public License 20 * along with this file; if not, write to the Free Software 21 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA 22 * or visit http://www.gnu.org/licenses/. 23 * 24 * This file may also be available under a different license from Cavium. 25 * Contact Cavium Networks for more information 26 ***********************license end**************************************/ 27 28 /** 29 * 30 * Interface to the hardware Packet Output unit. 31 * 32 * Starting with SDK 1.7.0, the PKO output functions now support 33 * two types of locking. CVMX_PKO_LOCK_ATOMIC_TAG continues to 34 * function similarly to previous SDKs by using POW atomic tags 35 * to preserve ordering and exclusivity. As a new option, you 36 * can now pass CVMX_PKO_LOCK_CMD_QUEUE which uses a ll/sc 37 * memory based locking instead. This locking has the advantage 38 * of not affecting the tag state but doesn't preserve packet 39 * ordering. CVMX_PKO_LOCK_CMD_QUEUE is appropriate in most 40 * generic code while CVMX_PKO_LOCK_CMD_QUEUE should be used 41 * with hand tuned fast path code. 42 * 43 * Some of other SDK differences visible to the command queuing: 44 * - PKO indexes are no longer stored in the FAU. A large 45 * percentage of the FAU register block used to be tied up 46 * maintaining PKO queue pointers. These are now stored in a 47 * global named block. 48 * - The PKO <b>use_locking</b> parameter can now have a global 49 * effect. Since all application use the same named block, 50 * queue locking correctly applies across all operating 51 * systems when using CVMX_PKO_LOCK_CMD_QUEUE. 52 * - PKO 3 word commands are now supported. Use 53 * cvmx_pko_send_packet_finish3(). 54 * 55 */ 56 57 #ifndef __CVMX_PKO_H__ 58 #define __CVMX_PKO_H__ 59 60 #include <asm/octeon/cvmx-fpa.h> 61 #include <asm/octeon/cvmx-pow.h> 62 #include <asm/octeon/cvmx-cmd-queue.h> 63 #include <asm/octeon/cvmx-pko-defs.h> 64 65 /* Adjust the command buffer size by 1 word so that in the case of using only 66 * two word PKO commands no command words stradle buffers. The useful values 67 * for this are 0 and 1. */ 68 #define CVMX_PKO_COMMAND_BUFFER_SIZE_ADJUST (1) 69 70 #define CVMX_PKO_MAX_OUTPUT_QUEUES_STATIC 256 71 #define CVMX_PKO_MAX_OUTPUT_QUEUES ((OCTEON_IS_MODEL(OCTEON_CN31XX) || \ 72 OCTEON_IS_MODEL(OCTEON_CN3010) || OCTEON_IS_MODEL(OCTEON_CN3005) || \ 73 OCTEON_IS_MODEL(OCTEON_CN50XX)) ? 32 : \ 74 (OCTEON_IS_MODEL(OCTEON_CN58XX) || \ 75 OCTEON_IS_MODEL(OCTEON_CN56XX)) ? 256 : 128) 76 #define CVMX_PKO_NUM_OUTPUT_PORTS 40 77 /* use this for queues that are not used */ 78 #define CVMX_PKO_MEM_QUEUE_PTRS_ILLEGAL_PID 63 79 #define CVMX_PKO_QUEUE_STATIC_PRIORITY 9 80 #define CVMX_PKO_ILLEGAL_QUEUE 0xFFFF 81 #define CVMX_PKO_MAX_QUEUE_DEPTH 0 82 83 typedef enum { 84 CVMX_PKO_SUCCESS, 85 CVMX_PKO_INVALID_PORT, 86 CVMX_PKO_INVALID_QUEUE, 87 CVMX_PKO_INVALID_PRIORITY, 88 CVMX_PKO_NO_MEMORY, 89 CVMX_PKO_PORT_ALREADY_SETUP, 90 CVMX_PKO_CMD_QUEUE_INIT_ERROR 91 } cvmx_pko_status_t; 92 93 /** 94 * This enumeration represents the different locking modes supported by PKO. 95 */ 96 typedef enum { 97 /* 98 * PKO doesn't do any locking. It is the responsibility of the 99 * application to make sure that no other core is accessing 100 * the same queue at the same time 101 */ 102 CVMX_PKO_LOCK_NONE = 0, 103 /* 104 * PKO performs an atomic tagswitch to insure exclusive access 105 * to the output queue. This will maintain packet ordering on 106 * output. 107 */ 108 CVMX_PKO_LOCK_ATOMIC_TAG = 1, 109 /* 110 * PKO uses the common command queue locks to insure exclusive 111 * access to the output queue. This is a memory based 112 * ll/sc. This is the most portable locking mechanism. 113 */ 114 CVMX_PKO_LOCK_CMD_QUEUE = 2, 115 } cvmx_pko_lock_t; 116 117 typedef struct { 118 uint32_t packets; 119 uint64_t octets; 120 uint64_t doorbell; 121 } cvmx_pko_port_status_t; 122 123 /** 124 * This structure defines the address to use on a packet enqueue 125 */ 126 typedef union { 127 uint64_t u64; 128 struct { 129 #ifdef __BIG_ENDIAN_BITFIELD 130 /* Must CVMX_IO_SEG */ 131 uint64_t mem_space:2; 132 /* Must be zero */ 133 uint64_t reserved:13; 134 /* Must be one */ 135 uint64_t is_io:1; 136 /* The ID of the device on the non-coherent bus */ 137 uint64_t did:8; 138 /* Must be zero */ 139 uint64_t reserved2:4; 140 /* Must be zero */ 141 uint64_t reserved3:18; 142 /* 143 * The hardware likes to have the output port in 144 * addition to the output queue, 145 */ 146 uint64_t port:6; 147 /* 148 * The output queue to send the packet to (0-127 are 149 * legal) 150 */ 151 uint64_t queue:9; 152 /* Must be zero */ 153 uint64_t reserved4:3; 154 #else 155 uint64_t reserved4:3; 156 uint64_t queue:9; 157 uint64_t port:9; 158 uint64_t reserved3:15; 159 uint64_t reserved2:4; 160 uint64_t did:8; 161 uint64_t is_io:1; 162 uint64_t reserved:13; 163 uint64_t mem_space:2; 164 #endif 165 } s; 166 } cvmx_pko_doorbell_address_t; 167 168 /** 169 * Structure of the first packet output command word. 170 */ 171 union cvmx_pko_command_word0 { 172 uint64_t u64; 173 struct { 174 #ifdef __BIG_ENDIAN_BITFIELD 175 /* 176 * The size of the reg1 operation - could be 8, 16, 177 * 32, or 64 bits. 178 */ 179 uint64_t size1:2; 180 /* 181 * The size of the reg0 operation - could be 8, 16, 182 * 32, or 64 bits. 183 */ 184 uint64_t size0:2; 185 /* 186 * If set, subtract 1, if clear, subtract packet 187 * size. 188 */ 189 uint64_t subone1:1; 190 /* 191 * The register, subtract will be done if reg1 is 192 * non-zero. 193 */ 194 uint64_t reg1:11; 195 /* If set, subtract 1, if clear, subtract packet size */ 196 uint64_t subone0:1; 197 /* The register, subtract will be done if reg0 is non-zero */ 198 uint64_t reg0:11; 199 /* 200 * When set, interpret segment pointer and segment 201 * bytes in little endian order. 202 */ 203 uint64_t le:1; 204 /* 205 * When set, packet data not allocated in L2 cache by 206 * PKO. 207 */ 208 uint64_t n2:1; 209 /* 210 * If set and rsp is set, word3 contains a pointer to 211 * a work queue entry. 212 */ 213 uint64_t wqp:1; 214 /* If set, the hardware will send a response when done */ 215 uint64_t rsp:1; 216 /* 217 * If set, the supplied pkt_ptr is really a pointer to 218 * a list of pkt_ptr's. 219 */ 220 uint64_t gather:1; 221 /* 222 * If ipoffp1 is non zero, (ipoffp1-1) is the number 223 * of bytes to IP header, and the hardware will 224 * calculate and insert the UDP/TCP checksum. 225 */ 226 uint64_t ipoffp1:7; 227 /* 228 * If set, ignore the I bit (force to zero) from all 229 * pointer structures. 230 */ 231 uint64_t ignore_i:1; 232 /* 233 * If clear, the hardware will attempt to free the 234 * buffers containing the packet. 235 */ 236 uint64_t dontfree:1; 237 /* 238 * The total number of segs in the packet, if gather 239 * set, also gather list length. 240 */ 241 uint64_t segs:6; 242 /* Including L2, but no trailing CRC */ 243 uint64_t total_bytes:16; 244 #else 245 uint64_t total_bytes:16; 246 uint64_t segs:6; 247 uint64_t dontfree:1; 248 uint64_t ignore_i:1; 249 uint64_t ipoffp1:7; 250 uint64_t gather:1; 251 uint64_t rsp:1; 252 uint64_t wqp:1; 253 uint64_t n2:1; 254 uint64_t le:1; 255 uint64_t reg0:11; 256 uint64_t subone0:1; 257 uint64_t reg1:11; 258 uint64_t subone1:1; 259 uint64_t size0:2; 260 uint64_t size1:2; 261 #endif 262 } s; 263 }; 264 265 /* CSR typedefs have been moved to cvmx-csr-*.h */ 266 267 /** 268 * Definition of internal state for Packet output processing 269 */ 270 typedef struct { 271 /* ptr to start of buffer, offset kept in FAU reg */ 272 uint64_t *start_ptr; 273 } cvmx_pko_state_elem_t; 274 275 /** 276 * Call before any other calls to initialize the packet 277 * output system. 278 */ 279 extern void cvmx_pko_initialize_global(void); 280 281 /** 282 * Enables the packet output hardware. It must already be 283 * configured. 284 */ 285 extern void cvmx_pko_enable(void); 286 287 /** 288 * Disables the packet output. Does not affect any configuration. 289 */ 290 extern void cvmx_pko_disable(void); 291 292 /** 293 * Shutdown and free resources required by packet output. 294 */ 295 296 extern void cvmx_pko_shutdown(void); 297 298 /** 299 * Configure a output port and the associated queues for use. 300 * 301 * @port: Port to configure. 302 * @base_queue: First queue number to associate with this port. 303 * @num_queues: Number of queues t oassociate with this port 304 * @priority: Array of priority levels for each queue. Values are 305 * allowed to be 1-8. A value of 8 get 8 times the traffic 306 * of a value of 1. There must be num_queues elements in the 307 * array. 308 */ 309 extern cvmx_pko_status_t cvmx_pko_config_port(uint64_t port, 310 uint64_t base_queue, 311 uint64_t num_queues, 312 const uint64_t priority[]); 313 314 /** 315 * Ring the packet output doorbell. This tells the packet 316 * output hardware that "len" command words have been added 317 * to its pending list. This command includes the required 318 * CVMX_SYNCWS before the doorbell ring. 319 * 320 * @port: Port the packet is for 321 * @queue: Queue the packet is for 322 * @len: Length of the command in 64 bit words 323 */ 324 static inline void cvmx_pko_doorbell(uint64_t port, uint64_t queue, 325 uint64_t len) 326 { 327 cvmx_pko_doorbell_address_t ptr; 328 329 ptr.u64 = 0; 330 ptr.s.mem_space = CVMX_IO_SEG; 331 ptr.s.did = CVMX_OCT_DID_PKT_SEND; 332 ptr.s.is_io = 1; 333 ptr.s.port = port; 334 ptr.s.queue = queue; 335 /* 336 * Need to make sure output queue data is in DRAM before 337 * doorbell write. 338 */ 339 CVMX_SYNCWS; 340 cvmx_write_io(ptr.u64, len); 341 } 342 343 /** 344 * Prepare to send a packet. This may initiate a tag switch to 345 * get exclusive access to the output queue structure, and 346 * performs other prep work for the packet send operation. 347 * 348 * cvmx_pko_send_packet_finish() MUST be called after this function is called, 349 * and must be called with the same port/queue/use_locking arguments. 350 * 351 * The use_locking parameter allows the caller to use three 352 * possible locking modes. 353 * - CVMX_PKO_LOCK_NONE 354 * - PKO doesn't do any locking. It is the responsibility 355 * of the application to make sure that no other core 356 * is accessing the same queue at the same time. 357 * - CVMX_PKO_LOCK_ATOMIC_TAG 358 * - PKO performs an atomic tagswitch to insure exclusive 359 * access to the output queue. This will maintain 360 * packet ordering on output. 361 * - CVMX_PKO_LOCK_CMD_QUEUE 362 * - PKO uses the common command queue locks to insure 363 * exclusive access to the output queue. This is a 364 * memory based ll/sc. This is the most portable 365 * locking mechanism. 366 * 367 * NOTE: If atomic locking is used, the POW entry CANNOT be 368 * descheduled, as it does not contain a valid WQE pointer. 369 * 370 * @port: Port to send it on 371 * @queue: Queue to use 372 * @use_locking: CVMX_PKO_LOCK_NONE, CVMX_PKO_LOCK_ATOMIC_TAG, or 373 * CVMX_PKO_LOCK_CMD_QUEUE 374 */ 375 376 static inline void cvmx_pko_send_packet_prepare(uint64_t port, uint64_t queue, 377 cvmx_pko_lock_t use_locking) 378 { 379 if (use_locking == CVMX_PKO_LOCK_ATOMIC_TAG) { 380 /* 381 * Must do a full switch here to handle all cases. We 382 * use a fake WQE pointer, as the POW does not access 383 * this memory. The WQE pointer and group are only 384 * used if this work is descheduled, which is not 385 * supported by the 386 * cvmx_pko_send_packet_prepare/cvmx_pko_send_packet_finish 387 * combination. Note that this is a special case in 388 * which these fake values can be used - this is not a 389 * general technique. 390 */ 391 uint32_t tag = 392 CVMX_TAG_SW_BITS_INTERNAL << CVMX_TAG_SW_SHIFT | 393 CVMX_TAG_SUBGROUP_PKO << CVMX_TAG_SUBGROUP_SHIFT | 394 (CVMX_TAG_SUBGROUP_MASK & queue); 395 cvmx_pow_tag_sw_full((struct cvmx_wqe *) cvmx_phys_to_ptr(0x80), tag, 396 CVMX_POW_TAG_TYPE_ATOMIC, 0); 397 } 398 } 399 400 /** 401 * Complete packet output. cvmx_pko_send_packet_prepare() must be 402 * called exactly once before this, and the same parameters must be 403 * passed to both cvmx_pko_send_packet_prepare() and 404 * cvmx_pko_send_packet_finish(). 405 * 406 * @port: Port to send it on 407 * @queue: Queue to use 408 * @pko_command: 409 * PKO HW command word 410 * @packet: Packet to send 411 * @use_locking: CVMX_PKO_LOCK_NONE, CVMX_PKO_LOCK_ATOMIC_TAG, or 412 * CVMX_PKO_LOCK_CMD_QUEUE 413 * 414 * Returns: CVMX_PKO_SUCCESS on success, or error code on 415 * failure of output 416 */ 417 static inline cvmx_pko_status_t cvmx_pko_send_packet_finish( 418 uint64_t port, 419 uint64_t queue, 420 union cvmx_pko_command_word0 pko_command, 421 union cvmx_buf_ptr packet, 422 cvmx_pko_lock_t use_locking) 423 { 424 cvmx_cmd_queue_result_t result; 425 if (use_locking == CVMX_PKO_LOCK_ATOMIC_TAG) 426 cvmx_pow_tag_sw_wait(); 427 result = cvmx_cmd_queue_write2(CVMX_CMD_QUEUE_PKO(queue), 428 (use_locking == CVMX_PKO_LOCK_CMD_QUEUE), 429 pko_command.u64, packet.u64); 430 if (likely(result == CVMX_CMD_QUEUE_SUCCESS)) { 431 cvmx_pko_doorbell(port, queue, 2); 432 return CVMX_PKO_SUCCESS; 433 } else if ((result == CVMX_CMD_QUEUE_NO_MEMORY) 434 || (result == CVMX_CMD_QUEUE_FULL)) { 435 return CVMX_PKO_NO_MEMORY; 436 } else { 437 return CVMX_PKO_INVALID_QUEUE; 438 } 439 } 440 441 /** 442 * Complete packet output. cvmx_pko_send_packet_prepare() must be 443 * called exactly once before this, and the same parameters must be 444 * passed to both cvmx_pko_send_packet_prepare() and 445 * cvmx_pko_send_packet_finish(). 446 * 447 * @port: Port to send it on 448 * @queue: Queue to use 449 * @pko_command: 450 * PKO HW command word 451 * @packet: Packet to send 452 * @addr: Plysical address of a work queue entry or physical address 453 * to zero on complete. 454 * @use_locking: CVMX_PKO_LOCK_NONE, CVMX_PKO_LOCK_ATOMIC_TAG, or 455 * CVMX_PKO_LOCK_CMD_QUEUE 456 * 457 * Returns: CVMX_PKO_SUCCESS on success, or error code on 458 * failure of output 459 */ 460 static inline cvmx_pko_status_t cvmx_pko_send_packet_finish3( 461 uint64_t port, 462 uint64_t queue, 463 union cvmx_pko_command_word0 pko_command, 464 union cvmx_buf_ptr packet, 465 uint64_t addr, 466 cvmx_pko_lock_t use_locking) 467 { 468 cvmx_cmd_queue_result_t result; 469 if (use_locking == CVMX_PKO_LOCK_ATOMIC_TAG) 470 cvmx_pow_tag_sw_wait(); 471 result = cvmx_cmd_queue_write3(CVMX_CMD_QUEUE_PKO(queue), 472 (use_locking == CVMX_PKO_LOCK_CMD_QUEUE), 473 pko_command.u64, packet.u64, addr); 474 if (likely(result == CVMX_CMD_QUEUE_SUCCESS)) { 475 cvmx_pko_doorbell(port, queue, 3); 476 return CVMX_PKO_SUCCESS; 477 } else if ((result == CVMX_CMD_QUEUE_NO_MEMORY) 478 || (result == CVMX_CMD_QUEUE_FULL)) { 479 return CVMX_PKO_NO_MEMORY; 480 } else { 481 return CVMX_PKO_INVALID_QUEUE; 482 } 483 } 484 485 /** 486 * Return the pko output queue associated with a port and a specific core. 487 * In normal mode (PKO lockless operation is disabled), the value returned 488 * is the base queue. 489 * 490 * @port: Port number 491 * @core: Core to get queue for 492 * 493 * Returns Core-specific output queue 494 */ 495 static inline int cvmx_pko_get_base_queue_per_core(int port, int core) 496 { 497 #ifndef CVMX_HELPER_PKO_MAX_PORTS_INTERFACE0 498 #define CVMX_HELPER_PKO_MAX_PORTS_INTERFACE0 16 499 #endif 500 #ifndef CVMX_HELPER_PKO_MAX_PORTS_INTERFACE1 501 #define CVMX_HELPER_PKO_MAX_PORTS_INTERFACE1 16 502 #endif 503 504 if (port < CVMX_PKO_MAX_PORTS_INTERFACE0) 505 return port * CVMX_PKO_QUEUES_PER_PORT_INTERFACE0 + core; 506 else if (port >= 16 && port < 16 + CVMX_PKO_MAX_PORTS_INTERFACE1) 507 return CVMX_PKO_MAX_PORTS_INTERFACE0 * 508 CVMX_PKO_QUEUES_PER_PORT_INTERFACE0 + (port - 509 16) * 510 CVMX_PKO_QUEUES_PER_PORT_INTERFACE1 + core; 511 else if ((port >= 32) && (port < 36)) 512 return CVMX_PKO_MAX_PORTS_INTERFACE0 * 513 CVMX_PKO_QUEUES_PER_PORT_INTERFACE0 + 514 CVMX_PKO_MAX_PORTS_INTERFACE1 * 515 CVMX_PKO_QUEUES_PER_PORT_INTERFACE1 + (port - 516 32) * 517 CVMX_PKO_QUEUES_PER_PORT_PCI; 518 else if ((port >= 36) && (port < 40)) 519 return CVMX_PKO_MAX_PORTS_INTERFACE0 * 520 CVMX_PKO_QUEUES_PER_PORT_INTERFACE0 + 521 CVMX_PKO_MAX_PORTS_INTERFACE1 * 522 CVMX_PKO_QUEUES_PER_PORT_INTERFACE1 + 523 4 * CVMX_PKO_QUEUES_PER_PORT_PCI + (port - 524 36) * 525 CVMX_PKO_QUEUES_PER_PORT_LOOP; 526 else 527 /* Given the limit on the number of ports we can map to 528 * CVMX_MAX_OUTPUT_QUEUES_STATIC queues (currently 256, 529 * divided among all cores), the remaining unmapped ports 530 * are assigned an illegal queue number */ 531 return CVMX_PKO_ILLEGAL_QUEUE; 532 } 533 534 /** 535 * For a given port number, return the base pko output queue 536 * for the port. 537 * 538 * @port: Port number 539 * Returns Base output queue 540 */ 541 static inline int cvmx_pko_get_base_queue(int port) 542 { 543 if (OCTEON_IS_MODEL(OCTEON_CN68XX)) 544 return port; 545 546 return cvmx_pko_get_base_queue_per_core(port, 0); 547 } 548 549 /** 550 * For a given port number, return the number of pko output queues. 551 * 552 * @port: Port number 553 * Returns Number of output queues 554 */ 555 static inline int cvmx_pko_get_num_queues(int port) 556 { 557 if (port < 16) 558 return CVMX_PKO_QUEUES_PER_PORT_INTERFACE0; 559 else if (port < 32) 560 return CVMX_PKO_QUEUES_PER_PORT_INTERFACE1; 561 else if (port < 36) 562 return CVMX_PKO_QUEUES_PER_PORT_PCI; 563 else if (port < 40) 564 return CVMX_PKO_QUEUES_PER_PORT_LOOP; 565 else 566 return 0; 567 } 568 569 /** 570 * Get the status counters for a port. 571 * 572 * @port_num: Port number to get statistics for. 573 * @clear: Set to 1 to clear the counters after they are read 574 * @status: Where to put the results. 575 */ 576 static inline void cvmx_pko_get_port_status(uint64_t port_num, uint64_t clear, 577 cvmx_pko_port_status_t *status) 578 { 579 union cvmx_pko_reg_read_idx pko_reg_read_idx; 580 union cvmx_pko_mem_count0 pko_mem_count0; 581 union cvmx_pko_mem_count1 pko_mem_count1; 582 583 pko_reg_read_idx.u64 = 0; 584 pko_reg_read_idx.s.index = port_num; 585 cvmx_write_csr(CVMX_PKO_REG_READ_IDX, pko_reg_read_idx.u64); 586 587 pko_mem_count0.u64 = cvmx_read_csr(CVMX_PKO_MEM_COUNT0); 588 status->packets = pko_mem_count0.s.count; 589 if (clear) { 590 pko_mem_count0.s.count = port_num; 591 cvmx_write_csr(CVMX_PKO_MEM_COUNT0, pko_mem_count0.u64); 592 } 593 594 pko_mem_count1.u64 = cvmx_read_csr(CVMX_PKO_MEM_COUNT1); 595 status->octets = pko_mem_count1.s.count; 596 if (clear) { 597 pko_mem_count1.s.count = port_num; 598 cvmx_write_csr(CVMX_PKO_MEM_COUNT1, pko_mem_count1.u64); 599 } 600 601 if (OCTEON_IS_MODEL(OCTEON_CN3XXX)) { 602 union cvmx_pko_mem_debug9 debug9; 603 pko_reg_read_idx.s.index = cvmx_pko_get_base_queue(port_num); 604 cvmx_write_csr(CVMX_PKO_REG_READ_IDX, pko_reg_read_idx.u64); 605 debug9.u64 = cvmx_read_csr(CVMX_PKO_MEM_DEBUG9); 606 status->doorbell = debug9.cn38xx.doorbell; 607 } else { 608 union cvmx_pko_mem_debug8 debug8; 609 pko_reg_read_idx.s.index = cvmx_pko_get_base_queue(port_num); 610 cvmx_write_csr(CVMX_PKO_REG_READ_IDX, pko_reg_read_idx.u64); 611 debug8.u64 = cvmx_read_csr(CVMX_PKO_MEM_DEBUG8); 612 status->doorbell = debug8.cn50xx.doorbell; 613 } 614 } 615 616 /** 617 * Rate limit a PKO port to a max packets/sec. This function is only 618 * supported on CN57XX, CN56XX, CN55XX, and CN54XX. 619 * 620 * @port: Port to rate limit 621 * @packets_s: Maximum packet/sec 622 * @burst: Maximum number of packets to burst in a row before rate 623 * limiting cuts in. 624 * 625 * Returns Zero on success, negative on failure 626 */ 627 extern int cvmx_pko_rate_limit_packets(int port, int packets_s, int burst); 628 629 /** 630 * Rate limit a PKO port to a max bits/sec. This function is only 631 * supported on CN57XX, CN56XX, CN55XX, and CN54XX. 632 * 633 * @port: Port to rate limit 634 * @bits_s: PKO rate limit in bits/sec 635 * @burst: Maximum number of bits to burst before rate 636 * limiting cuts in. 637 * 638 * Returns Zero on success, negative on failure 639 */ 640 extern int cvmx_pko_rate_limit_bits(int port, uint64_t bits_s, int burst); 641 642 #endif /* __CVMX_PKO_H__ */ 643