1 /***********************license start*************** 2 * Author: Cavium Networks 3 * 4 * Contact: support@caviumnetworks.com 5 * This file is part of the OCTEON SDK 6 * 7 * Copyright (c) 2003-2012 Cavium Networks 8 * 9 * This file is free software; you can redistribute it and/or modify 10 * it under the terms of the GNU General Public License, Version 2, as 11 * published by the Free Software Foundation. 12 * 13 * This file is distributed in the hope that it will be useful, but 14 * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty 15 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or 16 * NONINFRINGEMENT. See the GNU General Public License for more 17 * details. 18 * 19 * You should have received a copy of the GNU General Public License 20 * along with this file; if not, write to the Free Software 21 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA 22 * or visit http://www.gnu.org/licenses/. 23 * 24 * This file may also be available under a different license from Cavium. 25 * Contact Cavium Networks for more information 26 ***********************license end**************************************/ 27 28 #ifndef __CVMX_NPI_DEFS_H__ 29 #define __CVMX_NPI_DEFS_H__ 30 31 #define CVMX_NPI_BASE_ADDR_INPUT0 CVMX_NPI_BASE_ADDR_INPUTX(0) 32 #define CVMX_NPI_BASE_ADDR_INPUT1 CVMX_NPI_BASE_ADDR_INPUTX(1) 33 #define CVMX_NPI_BASE_ADDR_INPUT2 CVMX_NPI_BASE_ADDR_INPUTX(2) 34 #define CVMX_NPI_BASE_ADDR_INPUT3 CVMX_NPI_BASE_ADDR_INPUTX(3) 35 #define CVMX_NPI_BASE_ADDR_INPUTX(offset) (CVMX_ADD_IO_SEG(0x00011F0000000070ull) + ((offset) & 3) * 16) 36 #define CVMX_NPI_BASE_ADDR_OUTPUT0 CVMX_NPI_BASE_ADDR_OUTPUTX(0) 37 #define CVMX_NPI_BASE_ADDR_OUTPUT1 CVMX_NPI_BASE_ADDR_OUTPUTX(1) 38 #define CVMX_NPI_BASE_ADDR_OUTPUT2 CVMX_NPI_BASE_ADDR_OUTPUTX(2) 39 #define CVMX_NPI_BASE_ADDR_OUTPUT3 CVMX_NPI_BASE_ADDR_OUTPUTX(3) 40 #define CVMX_NPI_BASE_ADDR_OUTPUTX(offset) (CVMX_ADD_IO_SEG(0x00011F00000000B8ull) + ((offset) & 3) * 8) 41 #define CVMX_NPI_BIST_STATUS (CVMX_ADD_IO_SEG(0x00011F00000003F8ull)) 42 #define CVMX_NPI_BUFF_SIZE_OUTPUT0 CVMX_NPI_BUFF_SIZE_OUTPUTX(0) 43 #define CVMX_NPI_BUFF_SIZE_OUTPUT1 CVMX_NPI_BUFF_SIZE_OUTPUTX(1) 44 #define CVMX_NPI_BUFF_SIZE_OUTPUT2 CVMX_NPI_BUFF_SIZE_OUTPUTX(2) 45 #define CVMX_NPI_BUFF_SIZE_OUTPUT3 CVMX_NPI_BUFF_SIZE_OUTPUTX(3) 46 #define CVMX_NPI_BUFF_SIZE_OUTPUTX(offset) (CVMX_ADD_IO_SEG(0x00011F00000000E0ull) + ((offset) & 3) * 8) 47 #define CVMX_NPI_COMP_CTL (CVMX_ADD_IO_SEG(0x00011F0000000218ull)) 48 #define CVMX_NPI_CTL_STATUS (CVMX_ADD_IO_SEG(0x00011F0000000010ull)) 49 #define CVMX_NPI_DBG_SELECT (CVMX_ADD_IO_SEG(0x00011F0000000008ull)) 50 #define CVMX_NPI_DMA_CONTROL (CVMX_ADD_IO_SEG(0x00011F0000000128ull)) 51 #define CVMX_NPI_DMA_HIGHP_COUNTS (CVMX_ADD_IO_SEG(0x00011F0000000148ull)) 52 #define CVMX_NPI_DMA_HIGHP_NADDR (CVMX_ADD_IO_SEG(0x00011F0000000158ull)) 53 #define CVMX_NPI_DMA_LOWP_COUNTS (CVMX_ADD_IO_SEG(0x00011F0000000140ull)) 54 #define CVMX_NPI_DMA_LOWP_NADDR (CVMX_ADD_IO_SEG(0x00011F0000000150ull)) 55 #define CVMX_NPI_HIGHP_DBELL (CVMX_ADD_IO_SEG(0x00011F0000000120ull)) 56 #define CVMX_NPI_HIGHP_IBUFF_SADDR (CVMX_ADD_IO_SEG(0x00011F0000000110ull)) 57 #define CVMX_NPI_INPUT_CONTROL (CVMX_ADD_IO_SEG(0x00011F0000000138ull)) 58 #define CVMX_NPI_INT_ENB (CVMX_ADD_IO_SEG(0x00011F0000000020ull)) 59 #define CVMX_NPI_INT_SUM (CVMX_ADD_IO_SEG(0x00011F0000000018ull)) 60 #define CVMX_NPI_LOWP_DBELL (CVMX_ADD_IO_SEG(0x00011F0000000118ull)) 61 #define CVMX_NPI_LOWP_IBUFF_SADDR (CVMX_ADD_IO_SEG(0x00011F0000000108ull)) 62 #define CVMX_NPI_MEM_ACCESS_SUBID3 CVMX_NPI_MEM_ACCESS_SUBIDX(3) 63 #define CVMX_NPI_MEM_ACCESS_SUBID4 CVMX_NPI_MEM_ACCESS_SUBIDX(4) 64 #define CVMX_NPI_MEM_ACCESS_SUBID5 CVMX_NPI_MEM_ACCESS_SUBIDX(5) 65 #define CVMX_NPI_MEM_ACCESS_SUBID6 CVMX_NPI_MEM_ACCESS_SUBIDX(6) 66 #define CVMX_NPI_MEM_ACCESS_SUBIDX(offset) (CVMX_ADD_IO_SEG(0x00011F0000000028ull) + ((offset) & 7) * 8 - 8*3) 67 #define CVMX_NPI_MSI_RCV (0x0000000000000190ull) 68 #define CVMX_NPI_NPI_MSI_RCV (CVMX_ADD_IO_SEG(0x00011F0000001190ull)) 69 #define CVMX_NPI_NUM_DESC_OUTPUT0 CVMX_NPI_NUM_DESC_OUTPUTX(0) 70 #define CVMX_NPI_NUM_DESC_OUTPUT1 CVMX_NPI_NUM_DESC_OUTPUTX(1) 71 #define CVMX_NPI_NUM_DESC_OUTPUT2 CVMX_NPI_NUM_DESC_OUTPUTX(2) 72 #define CVMX_NPI_NUM_DESC_OUTPUT3 CVMX_NPI_NUM_DESC_OUTPUTX(3) 73 #define CVMX_NPI_NUM_DESC_OUTPUTX(offset) (CVMX_ADD_IO_SEG(0x00011F0000000050ull) + ((offset) & 3) * 8) 74 #define CVMX_NPI_OUTPUT_CONTROL (CVMX_ADD_IO_SEG(0x00011F0000000100ull)) 75 #define CVMX_NPI_P0_DBPAIR_ADDR CVMX_NPI_PX_DBPAIR_ADDR(0) 76 #define CVMX_NPI_P0_INSTR_ADDR CVMX_NPI_PX_INSTR_ADDR(0) 77 #define CVMX_NPI_P0_INSTR_CNTS CVMX_NPI_PX_INSTR_CNTS(0) 78 #define CVMX_NPI_P0_PAIR_CNTS CVMX_NPI_PX_PAIR_CNTS(0) 79 #define CVMX_NPI_P1_DBPAIR_ADDR CVMX_NPI_PX_DBPAIR_ADDR(1) 80 #define CVMX_NPI_P1_INSTR_ADDR CVMX_NPI_PX_INSTR_ADDR(1) 81 #define CVMX_NPI_P1_INSTR_CNTS CVMX_NPI_PX_INSTR_CNTS(1) 82 #define CVMX_NPI_P1_PAIR_CNTS CVMX_NPI_PX_PAIR_CNTS(1) 83 #define CVMX_NPI_P2_DBPAIR_ADDR CVMX_NPI_PX_DBPAIR_ADDR(2) 84 #define CVMX_NPI_P2_INSTR_ADDR CVMX_NPI_PX_INSTR_ADDR(2) 85 #define CVMX_NPI_P2_INSTR_CNTS CVMX_NPI_PX_INSTR_CNTS(2) 86 #define CVMX_NPI_P2_PAIR_CNTS CVMX_NPI_PX_PAIR_CNTS(2) 87 #define CVMX_NPI_P3_DBPAIR_ADDR CVMX_NPI_PX_DBPAIR_ADDR(3) 88 #define CVMX_NPI_P3_INSTR_ADDR CVMX_NPI_PX_INSTR_ADDR(3) 89 #define CVMX_NPI_P3_INSTR_CNTS CVMX_NPI_PX_INSTR_CNTS(3) 90 #define CVMX_NPI_P3_PAIR_CNTS CVMX_NPI_PX_PAIR_CNTS(3) 91 #define CVMX_NPI_PCI_BAR1_INDEXX(offset) (CVMX_ADD_IO_SEG(0x00011F0000001100ull) + ((offset) & 31) * 4) 92 #define CVMX_NPI_PCI_BIST_REG (CVMX_ADD_IO_SEG(0x00011F00000011C0ull)) 93 #define CVMX_NPI_PCI_BURST_SIZE (CVMX_ADD_IO_SEG(0x00011F00000000D8ull)) 94 #define CVMX_NPI_PCI_CFG00 (CVMX_ADD_IO_SEG(0x00011F0000001800ull)) 95 #define CVMX_NPI_PCI_CFG01 (CVMX_ADD_IO_SEG(0x00011F0000001804ull)) 96 #define CVMX_NPI_PCI_CFG02 (CVMX_ADD_IO_SEG(0x00011F0000001808ull)) 97 #define CVMX_NPI_PCI_CFG03 (CVMX_ADD_IO_SEG(0x00011F000000180Cull)) 98 #define CVMX_NPI_PCI_CFG04 (CVMX_ADD_IO_SEG(0x00011F0000001810ull)) 99 #define CVMX_NPI_PCI_CFG05 (CVMX_ADD_IO_SEG(0x00011F0000001814ull)) 100 #define CVMX_NPI_PCI_CFG06 (CVMX_ADD_IO_SEG(0x00011F0000001818ull)) 101 #define CVMX_NPI_PCI_CFG07 (CVMX_ADD_IO_SEG(0x00011F000000181Cull)) 102 #define CVMX_NPI_PCI_CFG08 (CVMX_ADD_IO_SEG(0x00011F0000001820ull)) 103 #define CVMX_NPI_PCI_CFG09 (CVMX_ADD_IO_SEG(0x00011F0000001824ull)) 104 #define CVMX_NPI_PCI_CFG10 (CVMX_ADD_IO_SEG(0x00011F0000001828ull)) 105 #define CVMX_NPI_PCI_CFG11 (CVMX_ADD_IO_SEG(0x00011F000000182Cull)) 106 #define CVMX_NPI_PCI_CFG12 (CVMX_ADD_IO_SEG(0x00011F0000001830ull)) 107 #define CVMX_NPI_PCI_CFG13 (CVMX_ADD_IO_SEG(0x00011F0000001834ull)) 108 #define CVMX_NPI_PCI_CFG15 (CVMX_ADD_IO_SEG(0x00011F000000183Cull)) 109 #define CVMX_NPI_PCI_CFG16 (CVMX_ADD_IO_SEG(0x00011F0000001840ull)) 110 #define CVMX_NPI_PCI_CFG17 (CVMX_ADD_IO_SEG(0x00011F0000001844ull)) 111 #define CVMX_NPI_PCI_CFG18 (CVMX_ADD_IO_SEG(0x00011F0000001848ull)) 112 #define CVMX_NPI_PCI_CFG19 (CVMX_ADD_IO_SEG(0x00011F000000184Cull)) 113 #define CVMX_NPI_PCI_CFG20 (CVMX_ADD_IO_SEG(0x00011F0000001850ull)) 114 #define CVMX_NPI_PCI_CFG21 (CVMX_ADD_IO_SEG(0x00011F0000001854ull)) 115 #define CVMX_NPI_PCI_CFG22 (CVMX_ADD_IO_SEG(0x00011F0000001858ull)) 116 #define CVMX_NPI_PCI_CFG56 (CVMX_ADD_IO_SEG(0x00011F00000018E0ull)) 117 #define CVMX_NPI_PCI_CFG57 (CVMX_ADD_IO_SEG(0x00011F00000018E4ull)) 118 #define CVMX_NPI_PCI_CFG58 (CVMX_ADD_IO_SEG(0x00011F00000018E8ull)) 119 #define CVMX_NPI_PCI_CFG59 (CVMX_ADD_IO_SEG(0x00011F00000018ECull)) 120 #define CVMX_NPI_PCI_CFG60 (CVMX_ADD_IO_SEG(0x00011F00000018F0ull)) 121 #define CVMX_NPI_PCI_CFG61 (CVMX_ADD_IO_SEG(0x00011F00000018F4ull)) 122 #define CVMX_NPI_PCI_CFG62 (CVMX_ADD_IO_SEG(0x00011F00000018F8ull)) 123 #define CVMX_NPI_PCI_CFG63 (CVMX_ADD_IO_SEG(0x00011F00000018FCull)) 124 #define CVMX_NPI_PCI_CNT_REG (CVMX_ADD_IO_SEG(0x00011F00000011B8ull)) 125 #define CVMX_NPI_PCI_CTL_STATUS_2 (CVMX_ADD_IO_SEG(0x00011F000000118Cull)) 126 #define CVMX_NPI_PCI_INT_ARB_CFG (CVMX_ADD_IO_SEG(0x00011F0000000130ull)) 127 #define CVMX_NPI_PCI_INT_ENB2 (CVMX_ADD_IO_SEG(0x00011F00000011A0ull)) 128 #define CVMX_NPI_PCI_INT_SUM2 (CVMX_ADD_IO_SEG(0x00011F0000001198ull)) 129 #define CVMX_NPI_PCI_READ_CMD (CVMX_ADD_IO_SEG(0x00011F0000000048ull)) 130 #define CVMX_NPI_PCI_READ_CMD_6 (CVMX_ADD_IO_SEG(0x00011F0000001180ull)) 131 #define CVMX_NPI_PCI_READ_CMD_C (CVMX_ADD_IO_SEG(0x00011F0000001184ull)) 132 #define CVMX_NPI_PCI_READ_CMD_E (CVMX_ADD_IO_SEG(0x00011F0000001188ull)) 133 #define CVMX_NPI_PCI_SCM_REG (CVMX_ADD_IO_SEG(0x00011F00000011A8ull)) 134 #define CVMX_NPI_PCI_TSR_REG (CVMX_ADD_IO_SEG(0x00011F00000011B0ull)) 135 #define CVMX_NPI_PORT32_INSTR_HDR (CVMX_ADD_IO_SEG(0x00011F00000001F8ull)) 136 #define CVMX_NPI_PORT33_INSTR_HDR (CVMX_ADD_IO_SEG(0x00011F0000000200ull)) 137 #define CVMX_NPI_PORT34_INSTR_HDR (CVMX_ADD_IO_SEG(0x00011F0000000208ull)) 138 #define CVMX_NPI_PORT35_INSTR_HDR (CVMX_ADD_IO_SEG(0x00011F0000000210ull)) 139 #define CVMX_NPI_PORT_BP_CONTROL (CVMX_ADD_IO_SEG(0x00011F00000001F0ull)) 140 #define CVMX_NPI_PX_DBPAIR_ADDR(offset) (CVMX_ADD_IO_SEG(0x00011F0000000180ull) + ((offset) & 3) * 8) 141 #define CVMX_NPI_PX_INSTR_ADDR(offset) (CVMX_ADD_IO_SEG(0x00011F00000001C0ull) + ((offset) & 3) * 8) 142 #define CVMX_NPI_PX_INSTR_CNTS(offset) (CVMX_ADD_IO_SEG(0x00011F00000001A0ull) + ((offset) & 3) * 8) 143 #define CVMX_NPI_PX_PAIR_CNTS(offset) (CVMX_ADD_IO_SEG(0x00011F0000000160ull) + ((offset) & 3) * 8) 144 #define CVMX_NPI_RSL_INT_BLOCKS (CVMX_ADD_IO_SEG(0x00011F0000000000ull)) 145 #define CVMX_NPI_SIZE_INPUT0 CVMX_NPI_SIZE_INPUTX(0) 146 #define CVMX_NPI_SIZE_INPUT1 CVMX_NPI_SIZE_INPUTX(1) 147 #define CVMX_NPI_SIZE_INPUT2 CVMX_NPI_SIZE_INPUTX(2) 148 #define CVMX_NPI_SIZE_INPUT3 CVMX_NPI_SIZE_INPUTX(3) 149 #define CVMX_NPI_SIZE_INPUTX(offset) (CVMX_ADD_IO_SEG(0x00011F0000000078ull) + ((offset) & 3) * 16) 150 #define CVMX_NPI_WIN_READ_TO (CVMX_ADD_IO_SEG(0x00011F00000001E0ull)) 151 152 union cvmx_npi_base_addr_inputx { 153 uint64_t u64; 154 struct cvmx_npi_base_addr_inputx_s { 155 #ifdef __BIG_ENDIAN_BITFIELD 156 uint64_t baddr:61; 157 uint64_t reserved_0_2:3; 158 #else 159 uint64_t reserved_0_2:3; 160 uint64_t baddr:61; 161 #endif 162 } s; 163 }; 164 165 union cvmx_npi_base_addr_outputx { 166 uint64_t u64; 167 struct cvmx_npi_base_addr_outputx_s { 168 #ifdef __BIG_ENDIAN_BITFIELD 169 uint64_t baddr:61; 170 uint64_t reserved_0_2:3; 171 #else 172 uint64_t reserved_0_2:3; 173 uint64_t baddr:61; 174 #endif 175 } s; 176 }; 177 178 union cvmx_npi_bist_status { 179 uint64_t u64; 180 struct cvmx_npi_bist_status_s { 181 #ifdef __BIG_ENDIAN_BITFIELD 182 uint64_t reserved_20_63:44; 183 uint64_t csr_bs:1; 184 uint64_t dif_bs:1; 185 uint64_t rdp_bs:1; 186 uint64_t pcnc_bs:1; 187 uint64_t pcn_bs:1; 188 uint64_t rdn_bs:1; 189 uint64_t pcac_bs:1; 190 uint64_t pcad_bs:1; 191 uint64_t rdnl_bs:1; 192 uint64_t pgf_bs:1; 193 uint64_t pig_bs:1; 194 uint64_t pof0_bs:1; 195 uint64_t pof1_bs:1; 196 uint64_t pof2_bs:1; 197 uint64_t pof3_bs:1; 198 uint64_t pos_bs:1; 199 uint64_t nus_bs:1; 200 uint64_t dob_bs:1; 201 uint64_t pdf_bs:1; 202 uint64_t dpi_bs:1; 203 #else 204 uint64_t dpi_bs:1; 205 uint64_t pdf_bs:1; 206 uint64_t dob_bs:1; 207 uint64_t nus_bs:1; 208 uint64_t pos_bs:1; 209 uint64_t pof3_bs:1; 210 uint64_t pof2_bs:1; 211 uint64_t pof1_bs:1; 212 uint64_t pof0_bs:1; 213 uint64_t pig_bs:1; 214 uint64_t pgf_bs:1; 215 uint64_t rdnl_bs:1; 216 uint64_t pcad_bs:1; 217 uint64_t pcac_bs:1; 218 uint64_t rdn_bs:1; 219 uint64_t pcn_bs:1; 220 uint64_t pcnc_bs:1; 221 uint64_t rdp_bs:1; 222 uint64_t dif_bs:1; 223 uint64_t csr_bs:1; 224 uint64_t reserved_20_63:44; 225 #endif 226 } s; 227 struct cvmx_npi_bist_status_cn30xx { 228 #ifdef __BIG_ENDIAN_BITFIELD 229 uint64_t reserved_20_63:44; 230 uint64_t csr_bs:1; 231 uint64_t dif_bs:1; 232 uint64_t rdp_bs:1; 233 uint64_t pcnc_bs:1; 234 uint64_t pcn_bs:1; 235 uint64_t rdn_bs:1; 236 uint64_t pcac_bs:1; 237 uint64_t pcad_bs:1; 238 uint64_t rdnl_bs:1; 239 uint64_t pgf_bs:1; 240 uint64_t pig_bs:1; 241 uint64_t pof0_bs:1; 242 uint64_t reserved_5_7:3; 243 uint64_t pos_bs:1; 244 uint64_t nus_bs:1; 245 uint64_t dob_bs:1; 246 uint64_t pdf_bs:1; 247 uint64_t dpi_bs:1; 248 #else 249 uint64_t dpi_bs:1; 250 uint64_t pdf_bs:1; 251 uint64_t dob_bs:1; 252 uint64_t nus_bs:1; 253 uint64_t pos_bs:1; 254 uint64_t reserved_5_7:3; 255 uint64_t pof0_bs:1; 256 uint64_t pig_bs:1; 257 uint64_t pgf_bs:1; 258 uint64_t rdnl_bs:1; 259 uint64_t pcad_bs:1; 260 uint64_t pcac_bs:1; 261 uint64_t rdn_bs:1; 262 uint64_t pcn_bs:1; 263 uint64_t pcnc_bs:1; 264 uint64_t rdp_bs:1; 265 uint64_t dif_bs:1; 266 uint64_t csr_bs:1; 267 uint64_t reserved_20_63:44; 268 #endif 269 } cn30xx; 270 struct cvmx_npi_bist_status_cn50xx { 271 #ifdef __BIG_ENDIAN_BITFIELD 272 uint64_t reserved_20_63:44; 273 uint64_t csr_bs:1; 274 uint64_t dif_bs:1; 275 uint64_t rdp_bs:1; 276 uint64_t pcnc_bs:1; 277 uint64_t pcn_bs:1; 278 uint64_t rdn_bs:1; 279 uint64_t pcac_bs:1; 280 uint64_t pcad_bs:1; 281 uint64_t rdnl_bs:1; 282 uint64_t pgf_bs:1; 283 uint64_t pig_bs:1; 284 uint64_t pof0_bs:1; 285 uint64_t pof1_bs:1; 286 uint64_t reserved_5_6:2; 287 uint64_t pos_bs:1; 288 uint64_t nus_bs:1; 289 uint64_t dob_bs:1; 290 uint64_t pdf_bs:1; 291 uint64_t dpi_bs:1; 292 #else 293 uint64_t dpi_bs:1; 294 uint64_t pdf_bs:1; 295 uint64_t dob_bs:1; 296 uint64_t nus_bs:1; 297 uint64_t pos_bs:1; 298 uint64_t reserved_5_6:2; 299 uint64_t pof1_bs:1; 300 uint64_t pof0_bs:1; 301 uint64_t pig_bs:1; 302 uint64_t pgf_bs:1; 303 uint64_t rdnl_bs:1; 304 uint64_t pcad_bs:1; 305 uint64_t pcac_bs:1; 306 uint64_t rdn_bs:1; 307 uint64_t pcn_bs:1; 308 uint64_t pcnc_bs:1; 309 uint64_t rdp_bs:1; 310 uint64_t dif_bs:1; 311 uint64_t csr_bs:1; 312 uint64_t reserved_20_63:44; 313 #endif 314 } cn50xx; 315 }; 316 317 union cvmx_npi_buff_size_outputx { 318 uint64_t u64; 319 struct cvmx_npi_buff_size_outputx_s { 320 #ifdef __BIG_ENDIAN_BITFIELD 321 uint64_t reserved_23_63:41; 322 uint64_t isize:7; 323 uint64_t bsize:16; 324 #else 325 uint64_t bsize:16; 326 uint64_t isize:7; 327 uint64_t reserved_23_63:41; 328 #endif 329 } s; 330 }; 331 332 union cvmx_npi_comp_ctl { 333 uint64_t u64; 334 struct cvmx_npi_comp_ctl_s { 335 #ifdef __BIG_ENDIAN_BITFIELD 336 uint64_t reserved_10_63:54; 337 uint64_t pctl:5; 338 uint64_t nctl:5; 339 #else 340 uint64_t nctl:5; 341 uint64_t pctl:5; 342 uint64_t reserved_10_63:54; 343 #endif 344 } s; 345 }; 346 347 union cvmx_npi_ctl_status { 348 uint64_t u64; 349 struct cvmx_npi_ctl_status_s { 350 #ifdef __BIG_ENDIAN_BITFIELD 351 uint64_t reserved_63_63:1; 352 uint64_t chip_rev:8; 353 uint64_t dis_pniw:1; 354 uint64_t out3_enb:1; 355 uint64_t out2_enb:1; 356 uint64_t out1_enb:1; 357 uint64_t out0_enb:1; 358 uint64_t ins3_enb:1; 359 uint64_t ins2_enb:1; 360 uint64_t ins1_enb:1; 361 uint64_t ins0_enb:1; 362 uint64_t ins3_64b:1; 363 uint64_t ins2_64b:1; 364 uint64_t ins1_64b:1; 365 uint64_t ins0_64b:1; 366 uint64_t pci_wdis:1; 367 uint64_t wait_com:1; 368 uint64_t reserved_37_39:3; 369 uint64_t max_word:5; 370 uint64_t reserved_10_31:22; 371 uint64_t timer:10; 372 #else 373 uint64_t timer:10; 374 uint64_t reserved_10_31:22; 375 uint64_t max_word:5; 376 uint64_t reserved_37_39:3; 377 uint64_t wait_com:1; 378 uint64_t pci_wdis:1; 379 uint64_t ins0_64b:1; 380 uint64_t ins1_64b:1; 381 uint64_t ins2_64b:1; 382 uint64_t ins3_64b:1; 383 uint64_t ins0_enb:1; 384 uint64_t ins1_enb:1; 385 uint64_t ins2_enb:1; 386 uint64_t ins3_enb:1; 387 uint64_t out0_enb:1; 388 uint64_t out1_enb:1; 389 uint64_t out2_enb:1; 390 uint64_t out3_enb:1; 391 uint64_t dis_pniw:1; 392 uint64_t chip_rev:8; 393 uint64_t reserved_63_63:1; 394 #endif 395 } s; 396 struct cvmx_npi_ctl_status_cn30xx { 397 #ifdef __BIG_ENDIAN_BITFIELD 398 uint64_t reserved_63_63:1; 399 uint64_t chip_rev:8; 400 uint64_t dis_pniw:1; 401 uint64_t reserved_51_53:3; 402 uint64_t out0_enb:1; 403 uint64_t reserved_47_49:3; 404 uint64_t ins0_enb:1; 405 uint64_t reserved_43_45:3; 406 uint64_t ins0_64b:1; 407 uint64_t pci_wdis:1; 408 uint64_t wait_com:1; 409 uint64_t reserved_37_39:3; 410 uint64_t max_word:5; 411 uint64_t reserved_10_31:22; 412 uint64_t timer:10; 413 #else 414 uint64_t timer:10; 415 uint64_t reserved_10_31:22; 416 uint64_t max_word:5; 417 uint64_t reserved_37_39:3; 418 uint64_t wait_com:1; 419 uint64_t pci_wdis:1; 420 uint64_t ins0_64b:1; 421 uint64_t reserved_43_45:3; 422 uint64_t ins0_enb:1; 423 uint64_t reserved_47_49:3; 424 uint64_t out0_enb:1; 425 uint64_t reserved_51_53:3; 426 uint64_t dis_pniw:1; 427 uint64_t chip_rev:8; 428 uint64_t reserved_63_63:1; 429 #endif 430 } cn30xx; 431 struct cvmx_npi_ctl_status_cn31xx { 432 #ifdef __BIG_ENDIAN_BITFIELD 433 uint64_t reserved_63_63:1; 434 uint64_t chip_rev:8; 435 uint64_t dis_pniw:1; 436 uint64_t reserved_52_53:2; 437 uint64_t out1_enb:1; 438 uint64_t out0_enb:1; 439 uint64_t reserved_48_49:2; 440 uint64_t ins1_enb:1; 441 uint64_t ins0_enb:1; 442 uint64_t reserved_44_45:2; 443 uint64_t ins1_64b:1; 444 uint64_t ins0_64b:1; 445 uint64_t pci_wdis:1; 446 uint64_t wait_com:1; 447 uint64_t reserved_37_39:3; 448 uint64_t max_word:5; 449 uint64_t reserved_10_31:22; 450 uint64_t timer:10; 451 #else 452 uint64_t timer:10; 453 uint64_t reserved_10_31:22; 454 uint64_t max_word:5; 455 uint64_t reserved_37_39:3; 456 uint64_t wait_com:1; 457 uint64_t pci_wdis:1; 458 uint64_t ins0_64b:1; 459 uint64_t ins1_64b:1; 460 uint64_t reserved_44_45:2; 461 uint64_t ins0_enb:1; 462 uint64_t ins1_enb:1; 463 uint64_t reserved_48_49:2; 464 uint64_t out0_enb:1; 465 uint64_t out1_enb:1; 466 uint64_t reserved_52_53:2; 467 uint64_t dis_pniw:1; 468 uint64_t chip_rev:8; 469 uint64_t reserved_63_63:1; 470 #endif 471 } cn31xx; 472 }; 473 474 union cvmx_npi_dbg_select { 475 uint64_t u64; 476 struct cvmx_npi_dbg_select_s { 477 #ifdef __BIG_ENDIAN_BITFIELD 478 uint64_t reserved_16_63:48; 479 uint64_t dbg_sel:16; 480 #else 481 uint64_t dbg_sel:16; 482 uint64_t reserved_16_63:48; 483 #endif 484 } s; 485 }; 486 487 union cvmx_npi_dma_control { 488 uint64_t u64; 489 struct cvmx_npi_dma_control_s { 490 #ifdef __BIG_ENDIAN_BITFIELD 491 uint64_t reserved_36_63:28; 492 uint64_t b0_lend:1; 493 uint64_t dwb_denb:1; 494 uint64_t dwb_ichk:9; 495 uint64_t fpa_que:3; 496 uint64_t o_add1:1; 497 uint64_t o_ro:1; 498 uint64_t o_ns:1; 499 uint64_t o_es:2; 500 uint64_t o_mode:1; 501 uint64_t hp_enb:1; 502 uint64_t lp_enb:1; 503 uint64_t csize:14; 504 #else 505 uint64_t csize:14; 506 uint64_t lp_enb:1; 507 uint64_t hp_enb:1; 508 uint64_t o_mode:1; 509 uint64_t o_es:2; 510 uint64_t o_ns:1; 511 uint64_t o_ro:1; 512 uint64_t o_add1:1; 513 uint64_t fpa_que:3; 514 uint64_t dwb_ichk:9; 515 uint64_t dwb_denb:1; 516 uint64_t b0_lend:1; 517 uint64_t reserved_36_63:28; 518 #endif 519 } s; 520 }; 521 522 union cvmx_npi_dma_highp_counts { 523 uint64_t u64; 524 struct cvmx_npi_dma_highp_counts_s { 525 #ifdef __BIG_ENDIAN_BITFIELD 526 uint64_t reserved_39_63:25; 527 uint64_t fcnt:7; 528 uint64_t dbell:32; 529 #else 530 uint64_t dbell:32; 531 uint64_t fcnt:7; 532 uint64_t reserved_39_63:25; 533 #endif 534 } s; 535 }; 536 537 union cvmx_npi_dma_highp_naddr { 538 uint64_t u64; 539 struct cvmx_npi_dma_highp_naddr_s { 540 #ifdef __BIG_ENDIAN_BITFIELD 541 uint64_t reserved_40_63:24; 542 uint64_t state:4; 543 uint64_t addr:36; 544 #else 545 uint64_t addr:36; 546 uint64_t state:4; 547 uint64_t reserved_40_63:24; 548 #endif 549 } s; 550 }; 551 552 union cvmx_npi_dma_lowp_counts { 553 uint64_t u64; 554 struct cvmx_npi_dma_lowp_counts_s { 555 #ifdef __BIG_ENDIAN_BITFIELD 556 uint64_t reserved_39_63:25; 557 uint64_t fcnt:7; 558 uint64_t dbell:32; 559 #else 560 uint64_t dbell:32; 561 uint64_t fcnt:7; 562 uint64_t reserved_39_63:25; 563 #endif 564 } s; 565 }; 566 567 union cvmx_npi_dma_lowp_naddr { 568 uint64_t u64; 569 struct cvmx_npi_dma_lowp_naddr_s { 570 #ifdef __BIG_ENDIAN_BITFIELD 571 uint64_t reserved_40_63:24; 572 uint64_t state:4; 573 uint64_t addr:36; 574 #else 575 uint64_t addr:36; 576 uint64_t state:4; 577 uint64_t reserved_40_63:24; 578 #endif 579 } s; 580 }; 581 582 union cvmx_npi_highp_dbell { 583 uint64_t u64; 584 struct cvmx_npi_highp_dbell_s { 585 #ifdef __BIG_ENDIAN_BITFIELD 586 uint64_t reserved_16_63:48; 587 uint64_t dbell:16; 588 #else 589 uint64_t dbell:16; 590 uint64_t reserved_16_63:48; 591 #endif 592 } s; 593 }; 594 595 union cvmx_npi_highp_ibuff_saddr { 596 uint64_t u64; 597 struct cvmx_npi_highp_ibuff_saddr_s { 598 #ifdef __BIG_ENDIAN_BITFIELD 599 uint64_t reserved_36_63:28; 600 uint64_t saddr:36; 601 #else 602 uint64_t saddr:36; 603 uint64_t reserved_36_63:28; 604 #endif 605 } s; 606 }; 607 608 union cvmx_npi_input_control { 609 uint64_t u64; 610 struct cvmx_npi_input_control_s { 611 #ifdef __BIG_ENDIAN_BITFIELD 612 uint64_t reserved_23_63:41; 613 uint64_t pkt_rr:1; 614 uint64_t pbp_dhi:13; 615 uint64_t d_nsr:1; 616 uint64_t d_esr:2; 617 uint64_t d_ror:1; 618 uint64_t use_csr:1; 619 uint64_t nsr:1; 620 uint64_t esr:2; 621 uint64_t ror:1; 622 #else 623 uint64_t ror:1; 624 uint64_t esr:2; 625 uint64_t nsr:1; 626 uint64_t use_csr:1; 627 uint64_t d_ror:1; 628 uint64_t d_esr:2; 629 uint64_t d_nsr:1; 630 uint64_t pbp_dhi:13; 631 uint64_t pkt_rr:1; 632 uint64_t reserved_23_63:41; 633 #endif 634 } s; 635 struct cvmx_npi_input_control_cn30xx { 636 #ifdef __BIG_ENDIAN_BITFIELD 637 uint64_t reserved_22_63:42; 638 uint64_t pbp_dhi:13; 639 uint64_t d_nsr:1; 640 uint64_t d_esr:2; 641 uint64_t d_ror:1; 642 uint64_t use_csr:1; 643 uint64_t nsr:1; 644 uint64_t esr:2; 645 uint64_t ror:1; 646 #else 647 uint64_t ror:1; 648 uint64_t esr:2; 649 uint64_t nsr:1; 650 uint64_t use_csr:1; 651 uint64_t d_ror:1; 652 uint64_t d_esr:2; 653 uint64_t d_nsr:1; 654 uint64_t pbp_dhi:13; 655 uint64_t reserved_22_63:42; 656 #endif 657 } cn30xx; 658 }; 659 660 union cvmx_npi_int_enb { 661 uint64_t u64; 662 struct cvmx_npi_int_enb_s { 663 #ifdef __BIG_ENDIAN_BITFIELD 664 uint64_t reserved_62_63:2; 665 uint64_t q1_a_f:1; 666 uint64_t q1_s_e:1; 667 uint64_t pdf_p_f:1; 668 uint64_t pdf_p_e:1; 669 uint64_t pcf_p_f:1; 670 uint64_t pcf_p_e:1; 671 uint64_t rdx_s_e:1; 672 uint64_t rwx_s_e:1; 673 uint64_t pnc_a_f:1; 674 uint64_t pnc_s_e:1; 675 uint64_t com_a_f:1; 676 uint64_t com_s_e:1; 677 uint64_t q3_a_f:1; 678 uint64_t q3_s_e:1; 679 uint64_t q2_a_f:1; 680 uint64_t q2_s_e:1; 681 uint64_t pcr_a_f:1; 682 uint64_t pcr_s_e:1; 683 uint64_t fcr_a_f:1; 684 uint64_t fcr_s_e:1; 685 uint64_t iobdma:1; 686 uint64_t p_dperr:1; 687 uint64_t win_rto:1; 688 uint64_t i3_pperr:1; 689 uint64_t i2_pperr:1; 690 uint64_t i1_pperr:1; 691 uint64_t i0_pperr:1; 692 uint64_t p3_ptout:1; 693 uint64_t p2_ptout:1; 694 uint64_t p1_ptout:1; 695 uint64_t p0_ptout:1; 696 uint64_t p3_pperr:1; 697 uint64_t p2_pperr:1; 698 uint64_t p1_pperr:1; 699 uint64_t p0_pperr:1; 700 uint64_t g3_rtout:1; 701 uint64_t g2_rtout:1; 702 uint64_t g1_rtout:1; 703 uint64_t g0_rtout:1; 704 uint64_t p3_perr:1; 705 uint64_t p2_perr:1; 706 uint64_t p1_perr:1; 707 uint64_t p0_perr:1; 708 uint64_t p3_rtout:1; 709 uint64_t p2_rtout:1; 710 uint64_t p1_rtout:1; 711 uint64_t p0_rtout:1; 712 uint64_t i3_overf:1; 713 uint64_t i2_overf:1; 714 uint64_t i1_overf:1; 715 uint64_t i0_overf:1; 716 uint64_t i3_rtout:1; 717 uint64_t i2_rtout:1; 718 uint64_t i1_rtout:1; 719 uint64_t i0_rtout:1; 720 uint64_t po3_2sml:1; 721 uint64_t po2_2sml:1; 722 uint64_t po1_2sml:1; 723 uint64_t po0_2sml:1; 724 uint64_t pci_rsl:1; 725 uint64_t rml_wto:1; 726 uint64_t rml_rto:1; 727 #else 728 uint64_t rml_rto:1; 729 uint64_t rml_wto:1; 730 uint64_t pci_rsl:1; 731 uint64_t po0_2sml:1; 732 uint64_t po1_2sml:1; 733 uint64_t po2_2sml:1; 734 uint64_t po3_2sml:1; 735 uint64_t i0_rtout:1; 736 uint64_t i1_rtout:1; 737 uint64_t i2_rtout:1; 738 uint64_t i3_rtout:1; 739 uint64_t i0_overf:1; 740 uint64_t i1_overf:1; 741 uint64_t i2_overf:1; 742 uint64_t i3_overf:1; 743 uint64_t p0_rtout:1; 744 uint64_t p1_rtout:1; 745 uint64_t p2_rtout:1; 746 uint64_t p3_rtout:1; 747 uint64_t p0_perr:1; 748 uint64_t p1_perr:1; 749 uint64_t p2_perr:1; 750 uint64_t p3_perr:1; 751 uint64_t g0_rtout:1; 752 uint64_t g1_rtout:1; 753 uint64_t g2_rtout:1; 754 uint64_t g3_rtout:1; 755 uint64_t p0_pperr:1; 756 uint64_t p1_pperr:1; 757 uint64_t p2_pperr:1; 758 uint64_t p3_pperr:1; 759 uint64_t p0_ptout:1; 760 uint64_t p1_ptout:1; 761 uint64_t p2_ptout:1; 762 uint64_t p3_ptout:1; 763 uint64_t i0_pperr:1; 764 uint64_t i1_pperr:1; 765 uint64_t i2_pperr:1; 766 uint64_t i3_pperr:1; 767 uint64_t win_rto:1; 768 uint64_t p_dperr:1; 769 uint64_t iobdma:1; 770 uint64_t fcr_s_e:1; 771 uint64_t fcr_a_f:1; 772 uint64_t pcr_s_e:1; 773 uint64_t pcr_a_f:1; 774 uint64_t q2_s_e:1; 775 uint64_t q2_a_f:1; 776 uint64_t q3_s_e:1; 777 uint64_t q3_a_f:1; 778 uint64_t com_s_e:1; 779 uint64_t com_a_f:1; 780 uint64_t pnc_s_e:1; 781 uint64_t pnc_a_f:1; 782 uint64_t rwx_s_e:1; 783 uint64_t rdx_s_e:1; 784 uint64_t pcf_p_e:1; 785 uint64_t pcf_p_f:1; 786 uint64_t pdf_p_e:1; 787 uint64_t pdf_p_f:1; 788 uint64_t q1_s_e:1; 789 uint64_t q1_a_f:1; 790 uint64_t reserved_62_63:2; 791 #endif 792 } s; 793 struct cvmx_npi_int_enb_cn30xx { 794 #ifdef __BIG_ENDIAN_BITFIELD 795 uint64_t reserved_62_63:2; 796 uint64_t q1_a_f:1; 797 uint64_t q1_s_e:1; 798 uint64_t pdf_p_f:1; 799 uint64_t pdf_p_e:1; 800 uint64_t pcf_p_f:1; 801 uint64_t pcf_p_e:1; 802 uint64_t rdx_s_e:1; 803 uint64_t rwx_s_e:1; 804 uint64_t pnc_a_f:1; 805 uint64_t pnc_s_e:1; 806 uint64_t com_a_f:1; 807 uint64_t com_s_e:1; 808 uint64_t q3_a_f:1; 809 uint64_t q3_s_e:1; 810 uint64_t q2_a_f:1; 811 uint64_t q2_s_e:1; 812 uint64_t pcr_a_f:1; 813 uint64_t pcr_s_e:1; 814 uint64_t fcr_a_f:1; 815 uint64_t fcr_s_e:1; 816 uint64_t iobdma:1; 817 uint64_t p_dperr:1; 818 uint64_t win_rto:1; 819 uint64_t reserved_36_38:3; 820 uint64_t i0_pperr:1; 821 uint64_t reserved_32_34:3; 822 uint64_t p0_ptout:1; 823 uint64_t reserved_28_30:3; 824 uint64_t p0_pperr:1; 825 uint64_t reserved_24_26:3; 826 uint64_t g0_rtout:1; 827 uint64_t reserved_20_22:3; 828 uint64_t p0_perr:1; 829 uint64_t reserved_16_18:3; 830 uint64_t p0_rtout:1; 831 uint64_t reserved_12_14:3; 832 uint64_t i0_overf:1; 833 uint64_t reserved_8_10:3; 834 uint64_t i0_rtout:1; 835 uint64_t reserved_4_6:3; 836 uint64_t po0_2sml:1; 837 uint64_t pci_rsl:1; 838 uint64_t rml_wto:1; 839 uint64_t rml_rto:1; 840 #else 841 uint64_t rml_rto:1; 842 uint64_t rml_wto:1; 843 uint64_t pci_rsl:1; 844 uint64_t po0_2sml:1; 845 uint64_t reserved_4_6:3; 846 uint64_t i0_rtout:1; 847 uint64_t reserved_8_10:3; 848 uint64_t i0_overf:1; 849 uint64_t reserved_12_14:3; 850 uint64_t p0_rtout:1; 851 uint64_t reserved_16_18:3; 852 uint64_t p0_perr:1; 853 uint64_t reserved_20_22:3; 854 uint64_t g0_rtout:1; 855 uint64_t reserved_24_26:3; 856 uint64_t p0_pperr:1; 857 uint64_t reserved_28_30:3; 858 uint64_t p0_ptout:1; 859 uint64_t reserved_32_34:3; 860 uint64_t i0_pperr:1; 861 uint64_t reserved_36_38:3; 862 uint64_t win_rto:1; 863 uint64_t p_dperr:1; 864 uint64_t iobdma:1; 865 uint64_t fcr_s_e:1; 866 uint64_t fcr_a_f:1; 867 uint64_t pcr_s_e:1; 868 uint64_t pcr_a_f:1; 869 uint64_t q2_s_e:1; 870 uint64_t q2_a_f:1; 871 uint64_t q3_s_e:1; 872 uint64_t q3_a_f:1; 873 uint64_t com_s_e:1; 874 uint64_t com_a_f:1; 875 uint64_t pnc_s_e:1; 876 uint64_t pnc_a_f:1; 877 uint64_t rwx_s_e:1; 878 uint64_t rdx_s_e:1; 879 uint64_t pcf_p_e:1; 880 uint64_t pcf_p_f:1; 881 uint64_t pdf_p_e:1; 882 uint64_t pdf_p_f:1; 883 uint64_t q1_s_e:1; 884 uint64_t q1_a_f:1; 885 uint64_t reserved_62_63:2; 886 #endif 887 } cn30xx; 888 struct cvmx_npi_int_enb_cn31xx { 889 #ifdef __BIG_ENDIAN_BITFIELD 890 uint64_t reserved_62_63:2; 891 uint64_t q1_a_f:1; 892 uint64_t q1_s_e:1; 893 uint64_t pdf_p_f:1; 894 uint64_t pdf_p_e:1; 895 uint64_t pcf_p_f:1; 896 uint64_t pcf_p_e:1; 897 uint64_t rdx_s_e:1; 898 uint64_t rwx_s_e:1; 899 uint64_t pnc_a_f:1; 900 uint64_t pnc_s_e:1; 901 uint64_t com_a_f:1; 902 uint64_t com_s_e:1; 903 uint64_t q3_a_f:1; 904 uint64_t q3_s_e:1; 905 uint64_t q2_a_f:1; 906 uint64_t q2_s_e:1; 907 uint64_t pcr_a_f:1; 908 uint64_t pcr_s_e:1; 909 uint64_t fcr_a_f:1; 910 uint64_t fcr_s_e:1; 911 uint64_t iobdma:1; 912 uint64_t p_dperr:1; 913 uint64_t win_rto:1; 914 uint64_t reserved_37_38:2; 915 uint64_t i1_pperr:1; 916 uint64_t i0_pperr:1; 917 uint64_t reserved_33_34:2; 918 uint64_t p1_ptout:1; 919 uint64_t p0_ptout:1; 920 uint64_t reserved_29_30:2; 921 uint64_t p1_pperr:1; 922 uint64_t p0_pperr:1; 923 uint64_t reserved_25_26:2; 924 uint64_t g1_rtout:1; 925 uint64_t g0_rtout:1; 926 uint64_t reserved_21_22:2; 927 uint64_t p1_perr:1; 928 uint64_t p0_perr:1; 929 uint64_t reserved_17_18:2; 930 uint64_t p1_rtout:1; 931 uint64_t p0_rtout:1; 932 uint64_t reserved_13_14:2; 933 uint64_t i1_overf:1; 934 uint64_t i0_overf:1; 935 uint64_t reserved_9_10:2; 936 uint64_t i1_rtout:1; 937 uint64_t i0_rtout:1; 938 uint64_t reserved_5_6:2; 939 uint64_t po1_2sml:1; 940 uint64_t po0_2sml:1; 941 uint64_t pci_rsl:1; 942 uint64_t rml_wto:1; 943 uint64_t rml_rto:1; 944 #else 945 uint64_t rml_rto:1; 946 uint64_t rml_wto:1; 947 uint64_t pci_rsl:1; 948 uint64_t po0_2sml:1; 949 uint64_t po1_2sml:1; 950 uint64_t reserved_5_6:2; 951 uint64_t i0_rtout:1; 952 uint64_t i1_rtout:1; 953 uint64_t reserved_9_10:2; 954 uint64_t i0_overf:1; 955 uint64_t i1_overf:1; 956 uint64_t reserved_13_14:2; 957 uint64_t p0_rtout:1; 958 uint64_t p1_rtout:1; 959 uint64_t reserved_17_18:2; 960 uint64_t p0_perr:1; 961 uint64_t p1_perr:1; 962 uint64_t reserved_21_22:2; 963 uint64_t g0_rtout:1; 964 uint64_t g1_rtout:1; 965 uint64_t reserved_25_26:2; 966 uint64_t p0_pperr:1; 967 uint64_t p1_pperr:1; 968 uint64_t reserved_29_30:2; 969 uint64_t p0_ptout:1; 970 uint64_t p1_ptout:1; 971 uint64_t reserved_33_34:2; 972 uint64_t i0_pperr:1; 973 uint64_t i1_pperr:1; 974 uint64_t reserved_37_38:2; 975 uint64_t win_rto:1; 976 uint64_t p_dperr:1; 977 uint64_t iobdma:1; 978 uint64_t fcr_s_e:1; 979 uint64_t fcr_a_f:1; 980 uint64_t pcr_s_e:1; 981 uint64_t pcr_a_f:1; 982 uint64_t q2_s_e:1; 983 uint64_t q2_a_f:1; 984 uint64_t q3_s_e:1; 985 uint64_t q3_a_f:1; 986 uint64_t com_s_e:1; 987 uint64_t com_a_f:1; 988 uint64_t pnc_s_e:1; 989 uint64_t pnc_a_f:1; 990 uint64_t rwx_s_e:1; 991 uint64_t rdx_s_e:1; 992 uint64_t pcf_p_e:1; 993 uint64_t pcf_p_f:1; 994 uint64_t pdf_p_e:1; 995 uint64_t pdf_p_f:1; 996 uint64_t q1_s_e:1; 997 uint64_t q1_a_f:1; 998 uint64_t reserved_62_63:2; 999 #endif 1000 } cn31xx; 1001 struct cvmx_npi_int_enb_cn38xxp2 { 1002 #ifdef __BIG_ENDIAN_BITFIELD 1003 uint64_t reserved_42_63:22; 1004 uint64_t iobdma:1; 1005 uint64_t p_dperr:1; 1006 uint64_t win_rto:1; 1007 uint64_t i3_pperr:1; 1008 uint64_t i2_pperr:1; 1009 uint64_t i1_pperr:1; 1010 uint64_t i0_pperr:1; 1011 uint64_t p3_ptout:1; 1012 uint64_t p2_ptout:1; 1013 uint64_t p1_ptout:1; 1014 uint64_t p0_ptout:1; 1015 uint64_t p3_pperr:1; 1016 uint64_t p2_pperr:1; 1017 uint64_t p1_pperr:1; 1018 uint64_t p0_pperr:1; 1019 uint64_t g3_rtout:1; 1020 uint64_t g2_rtout:1; 1021 uint64_t g1_rtout:1; 1022 uint64_t g0_rtout:1; 1023 uint64_t p3_perr:1; 1024 uint64_t p2_perr:1; 1025 uint64_t p1_perr:1; 1026 uint64_t p0_perr:1; 1027 uint64_t p3_rtout:1; 1028 uint64_t p2_rtout:1; 1029 uint64_t p1_rtout:1; 1030 uint64_t p0_rtout:1; 1031 uint64_t i3_overf:1; 1032 uint64_t i2_overf:1; 1033 uint64_t i1_overf:1; 1034 uint64_t i0_overf:1; 1035 uint64_t i3_rtout:1; 1036 uint64_t i2_rtout:1; 1037 uint64_t i1_rtout:1; 1038 uint64_t i0_rtout:1; 1039 uint64_t po3_2sml:1; 1040 uint64_t po2_2sml:1; 1041 uint64_t po1_2sml:1; 1042 uint64_t po0_2sml:1; 1043 uint64_t pci_rsl:1; 1044 uint64_t rml_wto:1; 1045 uint64_t rml_rto:1; 1046 #else 1047 uint64_t rml_rto:1; 1048 uint64_t rml_wto:1; 1049 uint64_t pci_rsl:1; 1050 uint64_t po0_2sml:1; 1051 uint64_t po1_2sml:1; 1052 uint64_t po2_2sml:1; 1053 uint64_t po3_2sml:1; 1054 uint64_t i0_rtout:1; 1055 uint64_t i1_rtout:1; 1056 uint64_t i2_rtout:1; 1057 uint64_t i3_rtout:1; 1058 uint64_t i0_overf:1; 1059 uint64_t i1_overf:1; 1060 uint64_t i2_overf:1; 1061 uint64_t i3_overf:1; 1062 uint64_t p0_rtout:1; 1063 uint64_t p1_rtout:1; 1064 uint64_t p2_rtout:1; 1065 uint64_t p3_rtout:1; 1066 uint64_t p0_perr:1; 1067 uint64_t p1_perr:1; 1068 uint64_t p2_perr:1; 1069 uint64_t p3_perr:1; 1070 uint64_t g0_rtout:1; 1071 uint64_t g1_rtout:1; 1072 uint64_t g2_rtout:1; 1073 uint64_t g3_rtout:1; 1074 uint64_t p0_pperr:1; 1075 uint64_t p1_pperr:1; 1076 uint64_t p2_pperr:1; 1077 uint64_t p3_pperr:1; 1078 uint64_t p0_ptout:1; 1079 uint64_t p1_ptout:1; 1080 uint64_t p2_ptout:1; 1081 uint64_t p3_ptout:1; 1082 uint64_t i0_pperr:1; 1083 uint64_t i1_pperr:1; 1084 uint64_t i2_pperr:1; 1085 uint64_t i3_pperr:1; 1086 uint64_t win_rto:1; 1087 uint64_t p_dperr:1; 1088 uint64_t iobdma:1; 1089 uint64_t reserved_42_63:22; 1090 #endif 1091 } cn38xxp2; 1092 }; 1093 1094 union cvmx_npi_int_sum { 1095 uint64_t u64; 1096 struct cvmx_npi_int_sum_s { 1097 #ifdef __BIG_ENDIAN_BITFIELD 1098 uint64_t reserved_62_63:2; 1099 uint64_t q1_a_f:1; 1100 uint64_t q1_s_e:1; 1101 uint64_t pdf_p_f:1; 1102 uint64_t pdf_p_e:1; 1103 uint64_t pcf_p_f:1; 1104 uint64_t pcf_p_e:1; 1105 uint64_t rdx_s_e:1; 1106 uint64_t rwx_s_e:1; 1107 uint64_t pnc_a_f:1; 1108 uint64_t pnc_s_e:1; 1109 uint64_t com_a_f:1; 1110 uint64_t com_s_e:1; 1111 uint64_t q3_a_f:1; 1112 uint64_t q3_s_e:1; 1113 uint64_t q2_a_f:1; 1114 uint64_t q2_s_e:1; 1115 uint64_t pcr_a_f:1; 1116 uint64_t pcr_s_e:1; 1117 uint64_t fcr_a_f:1; 1118 uint64_t fcr_s_e:1; 1119 uint64_t iobdma:1; 1120 uint64_t p_dperr:1; 1121 uint64_t win_rto:1; 1122 uint64_t i3_pperr:1; 1123 uint64_t i2_pperr:1; 1124 uint64_t i1_pperr:1; 1125 uint64_t i0_pperr:1; 1126 uint64_t p3_ptout:1; 1127 uint64_t p2_ptout:1; 1128 uint64_t p1_ptout:1; 1129 uint64_t p0_ptout:1; 1130 uint64_t p3_pperr:1; 1131 uint64_t p2_pperr:1; 1132 uint64_t p1_pperr:1; 1133 uint64_t p0_pperr:1; 1134 uint64_t g3_rtout:1; 1135 uint64_t g2_rtout:1; 1136 uint64_t g1_rtout:1; 1137 uint64_t g0_rtout:1; 1138 uint64_t p3_perr:1; 1139 uint64_t p2_perr:1; 1140 uint64_t p1_perr:1; 1141 uint64_t p0_perr:1; 1142 uint64_t p3_rtout:1; 1143 uint64_t p2_rtout:1; 1144 uint64_t p1_rtout:1; 1145 uint64_t p0_rtout:1; 1146 uint64_t i3_overf:1; 1147 uint64_t i2_overf:1; 1148 uint64_t i1_overf:1; 1149 uint64_t i0_overf:1; 1150 uint64_t i3_rtout:1; 1151 uint64_t i2_rtout:1; 1152 uint64_t i1_rtout:1; 1153 uint64_t i0_rtout:1; 1154 uint64_t po3_2sml:1; 1155 uint64_t po2_2sml:1; 1156 uint64_t po1_2sml:1; 1157 uint64_t po0_2sml:1; 1158 uint64_t pci_rsl:1; 1159 uint64_t rml_wto:1; 1160 uint64_t rml_rto:1; 1161 #else 1162 uint64_t rml_rto:1; 1163 uint64_t rml_wto:1; 1164 uint64_t pci_rsl:1; 1165 uint64_t po0_2sml:1; 1166 uint64_t po1_2sml:1; 1167 uint64_t po2_2sml:1; 1168 uint64_t po3_2sml:1; 1169 uint64_t i0_rtout:1; 1170 uint64_t i1_rtout:1; 1171 uint64_t i2_rtout:1; 1172 uint64_t i3_rtout:1; 1173 uint64_t i0_overf:1; 1174 uint64_t i1_overf:1; 1175 uint64_t i2_overf:1; 1176 uint64_t i3_overf:1; 1177 uint64_t p0_rtout:1; 1178 uint64_t p1_rtout:1; 1179 uint64_t p2_rtout:1; 1180 uint64_t p3_rtout:1; 1181 uint64_t p0_perr:1; 1182 uint64_t p1_perr:1; 1183 uint64_t p2_perr:1; 1184 uint64_t p3_perr:1; 1185 uint64_t g0_rtout:1; 1186 uint64_t g1_rtout:1; 1187 uint64_t g2_rtout:1; 1188 uint64_t g3_rtout:1; 1189 uint64_t p0_pperr:1; 1190 uint64_t p1_pperr:1; 1191 uint64_t p2_pperr:1; 1192 uint64_t p3_pperr:1; 1193 uint64_t p0_ptout:1; 1194 uint64_t p1_ptout:1; 1195 uint64_t p2_ptout:1; 1196 uint64_t p3_ptout:1; 1197 uint64_t i0_pperr:1; 1198 uint64_t i1_pperr:1; 1199 uint64_t i2_pperr:1; 1200 uint64_t i3_pperr:1; 1201 uint64_t win_rto:1; 1202 uint64_t p_dperr:1; 1203 uint64_t iobdma:1; 1204 uint64_t fcr_s_e:1; 1205 uint64_t fcr_a_f:1; 1206 uint64_t pcr_s_e:1; 1207 uint64_t pcr_a_f:1; 1208 uint64_t q2_s_e:1; 1209 uint64_t q2_a_f:1; 1210 uint64_t q3_s_e:1; 1211 uint64_t q3_a_f:1; 1212 uint64_t com_s_e:1; 1213 uint64_t com_a_f:1; 1214 uint64_t pnc_s_e:1; 1215 uint64_t pnc_a_f:1; 1216 uint64_t rwx_s_e:1; 1217 uint64_t rdx_s_e:1; 1218 uint64_t pcf_p_e:1; 1219 uint64_t pcf_p_f:1; 1220 uint64_t pdf_p_e:1; 1221 uint64_t pdf_p_f:1; 1222 uint64_t q1_s_e:1; 1223 uint64_t q1_a_f:1; 1224 uint64_t reserved_62_63:2; 1225 #endif 1226 } s; 1227 struct cvmx_npi_int_sum_cn30xx { 1228 #ifdef __BIG_ENDIAN_BITFIELD 1229 uint64_t reserved_62_63:2; 1230 uint64_t q1_a_f:1; 1231 uint64_t q1_s_e:1; 1232 uint64_t pdf_p_f:1; 1233 uint64_t pdf_p_e:1; 1234 uint64_t pcf_p_f:1; 1235 uint64_t pcf_p_e:1; 1236 uint64_t rdx_s_e:1; 1237 uint64_t rwx_s_e:1; 1238 uint64_t pnc_a_f:1; 1239 uint64_t pnc_s_e:1; 1240 uint64_t com_a_f:1; 1241 uint64_t com_s_e:1; 1242 uint64_t q3_a_f:1; 1243 uint64_t q3_s_e:1; 1244 uint64_t q2_a_f:1; 1245 uint64_t q2_s_e:1; 1246 uint64_t pcr_a_f:1; 1247 uint64_t pcr_s_e:1; 1248 uint64_t fcr_a_f:1; 1249 uint64_t fcr_s_e:1; 1250 uint64_t iobdma:1; 1251 uint64_t p_dperr:1; 1252 uint64_t win_rto:1; 1253 uint64_t reserved_36_38:3; 1254 uint64_t i0_pperr:1; 1255 uint64_t reserved_32_34:3; 1256 uint64_t p0_ptout:1; 1257 uint64_t reserved_28_30:3; 1258 uint64_t p0_pperr:1; 1259 uint64_t reserved_24_26:3; 1260 uint64_t g0_rtout:1; 1261 uint64_t reserved_20_22:3; 1262 uint64_t p0_perr:1; 1263 uint64_t reserved_16_18:3; 1264 uint64_t p0_rtout:1; 1265 uint64_t reserved_12_14:3; 1266 uint64_t i0_overf:1; 1267 uint64_t reserved_8_10:3; 1268 uint64_t i0_rtout:1; 1269 uint64_t reserved_4_6:3; 1270 uint64_t po0_2sml:1; 1271 uint64_t pci_rsl:1; 1272 uint64_t rml_wto:1; 1273 uint64_t rml_rto:1; 1274 #else 1275 uint64_t rml_rto:1; 1276 uint64_t rml_wto:1; 1277 uint64_t pci_rsl:1; 1278 uint64_t po0_2sml:1; 1279 uint64_t reserved_4_6:3; 1280 uint64_t i0_rtout:1; 1281 uint64_t reserved_8_10:3; 1282 uint64_t i0_overf:1; 1283 uint64_t reserved_12_14:3; 1284 uint64_t p0_rtout:1; 1285 uint64_t reserved_16_18:3; 1286 uint64_t p0_perr:1; 1287 uint64_t reserved_20_22:3; 1288 uint64_t g0_rtout:1; 1289 uint64_t reserved_24_26:3; 1290 uint64_t p0_pperr:1; 1291 uint64_t reserved_28_30:3; 1292 uint64_t p0_ptout:1; 1293 uint64_t reserved_32_34:3; 1294 uint64_t i0_pperr:1; 1295 uint64_t reserved_36_38:3; 1296 uint64_t win_rto:1; 1297 uint64_t p_dperr:1; 1298 uint64_t iobdma:1; 1299 uint64_t fcr_s_e:1; 1300 uint64_t fcr_a_f:1; 1301 uint64_t pcr_s_e:1; 1302 uint64_t pcr_a_f:1; 1303 uint64_t q2_s_e:1; 1304 uint64_t q2_a_f:1; 1305 uint64_t q3_s_e:1; 1306 uint64_t q3_a_f:1; 1307 uint64_t com_s_e:1; 1308 uint64_t com_a_f:1; 1309 uint64_t pnc_s_e:1; 1310 uint64_t pnc_a_f:1; 1311 uint64_t rwx_s_e:1; 1312 uint64_t rdx_s_e:1; 1313 uint64_t pcf_p_e:1; 1314 uint64_t pcf_p_f:1; 1315 uint64_t pdf_p_e:1; 1316 uint64_t pdf_p_f:1; 1317 uint64_t q1_s_e:1; 1318 uint64_t q1_a_f:1; 1319 uint64_t reserved_62_63:2; 1320 #endif 1321 } cn30xx; 1322 struct cvmx_npi_int_sum_cn31xx { 1323 #ifdef __BIG_ENDIAN_BITFIELD 1324 uint64_t reserved_62_63:2; 1325 uint64_t q1_a_f:1; 1326 uint64_t q1_s_e:1; 1327 uint64_t pdf_p_f:1; 1328 uint64_t pdf_p_e:1; 1329 uint64_t pcf_p_f:1; 1330 uint64_t pcf_p_e:1; 1331 uint64_t rdx_s_e:1; 1332 uint64_t rwx_s_e:1; 1333 uint64_t pnc_a_f:1; 1334 uint64_t pnc_s_e:1; 1335 uint64_t com_a_f:1; 1336 uint64_t com_s_e:1; 1337 uint64_t q3_a_f:1; 1338 uint64_t q3_s_e:1; 1339 uint64_t q2_a_f:1; 1340 uint64_t q2_s_e:1; 1341 uint64_t pcr_a_f:1; 1342 uint64_t pcr_s_e:1; 1343 uint64_t fcr_a_f:1; 1344 uint64_t fcr_s_e:1; 1345 uint64_t iobdma:1; 1346 uint64_t p_dperr:1; 1347 uint64_t win_rto:1; 1348 uint64_t reserved_37_38:2; 1349 uint64_t i1_pperr:1; 1350 uint64_t i0_pperr:1; 1351 uint64_t reserved_33_34:2; 1352 uint64_t p1_ptout:1; 1353 uint64_t p0_ptout:1; 1354 uint64_t reserved_29_30:2; 1355 uint64_t p1_pperr:1; 1356 uint64_t p0_pperr:1; 1357 uint64_t reserved_25_26:2; 1358 uint64_t g1_rtout:1; 1359 uint64_t g0_rtout:1; 1360 uint64_t reserved_21_22:2; 1361 uint64_t p1_perr:1; 1362 uint64_t p0_perr:1; 1363 uint64_t reserved_17_18:2; 1364 uint64_t p1_rtout:1; 1365 uint64_t p0_rtout:1; 1366 uint64_t reserved_13_14:2; 1367 uint64_t i1_overf:1; 1368 uint64_t i0_overf:1; 1369 uint64_t reserved_9_10:2; 1370 uint64_t i1_rtout:1; 1371 uint64_t i0_rtout:1; 1372 uint64_t reserved_5_6:2; 1373 uint64_t po1_2sml:1; 1374 uint64_t po0_2sml:1; 1375 uint64_t pci_rsl:1; 1376 uint64_t rml_wto:1; 1377 uint64_t rml_rto:1; 1378 #else 1379 uint64_t rml_rto:1; 1380 uint64_t rml_wto:1; 1381 uint64_t pci_rsl:1; 1382 uint64_t po0_2sml:1; 1383 uint64_t po1_2sml:1; 1384 uint64_t reserved_5_6:2; 1385 uint64_t i0_rtout:1; 1386 uint64_t i1_rtout:1; 1387 uint64_t reserved_9_10:2; 1388 uint64_t i0_overf:1; 1389 uint64_t i1_overf:1; 1390 uint64_t reserved_13_14:2; 1391 uint64_t p0_rtout:1; 1392 uint64_t p1_rtout:1; 1393 uint64_t reserved_17_18:2; 1394 uint64_t p0_perr:1; 1395 uint64_t p1_perr:1; 1396 uint64_t reserved_21_22:2; 1397 uint64_t g0_rtout:1; 1398 uint64_t g1_rtout:1; 1399 uint64_t reserved_25_26:2; 1400 uint64_t p0_pperr:1; 1401 uint64_t p1_pperr:1; 1402 uint64_t reserved_29_30:2; 1403 uint64_t p0_ptout:1; 1404 uint64_t p1_ptout:1; 1405 uint64_t reserved_33_34:2; 1406 uint64_t i0_pperr:1; 1407 uint64_t i1_pperr:1; 1408 uint64_t reserved_37_38:2; 1409 uint64_t win_rto:1; 1410 uint64_t p_dperr:1; 1411 uint64_t iobdma:1; 1412 uint64_t fcr_s_e:1; 1413 uint64_t fcr_a_f:1; 1414 uint64_t pcr_s_e:1; 1415 uint64_t pcr_a_f:1; 1416 uint64_t q2_s_e:1; 1417 uint64_t q2_a_f:1; 1418 uint64_t q3_s_e:1; 1419 uint64_t q3_a_f:1; 1420 uint64_t com_s_e:1; 1421 uint64_t com_a_f:1; 1422 uint64_t pnc_s_e:1; 1423 uint64_t pnc_a_f:1; 1424 uint64_t rwx_s_e:1; 1425 uint64_t rdx_s_e:1; 1426 uint64_t pcf_p_e:1; 1427 uint64_t pcf_p_f:1; 1428 uint64_t pdf_p_e:1; 1429 uint64_t pdf_p_f:1; 1430 uint64_t q1_s_e:1; 1431 uint64_t q1_a_f:1; 1432 uint64_t reserved_62_63:2; 1433 #endif 1434 } cn31xx; 1435 struct cvmx_npi_int_sum_cn38xxp2 { 1436 #ifdef __BIG_ENDIAN_BITFIELD 1437 uint64_t reserved_42_63:22; 1438 uint64_t iobdma:1; 1439 uint64_t p_dperr:1; 1440 uint64_t win_rto:1; 1441 uint64_t i3_pperr:1; 1442 uint64_t i2_pperr:1; 1443 uint64_t i1_pperr:1; 1444 uint64_t i0_pperr:1; 1445 uint64_t p3_ptout:1; 1446 uint64_t p2_ptout:1; 1447 uint64_t p1_ptout:1; 1448 uint64_t p0_ptout:1; 1449 uint64_t p3_pperr:1; 1450 uint64_t p2_pperr:1; 1451 uint64_t p1_pperr:1; 1452 uint64_t p0_pperr:1; 1453 uint64_t g3_rtout:1; 1454 uint64_t g2_rtout:1; 1455 uint64_t g1_rtout:1; 1456 uint64_t g0_rtout:1; 1457 uint64_t p3_perr:1; 1458 uint64_t p2_perr:1; 1459 uint64_t p1_perr:1; 1460 uint64_t p0_perr:1; 1461 uint64_t p3_rtout:1; 1462 uint64_t p2_rtout:1; 1463 uint64_t p1_rtout:1; 1464 uint64_t p0_rtout:1; 1465 uint64_t i3_overf:1; 1466 uint64_t i2_overf:1; 1467 uint64_t i1_overf:1; 1468 uint64_t i0_overf:1; 1469 uint64_t i3_rtout:1; 1470 uint64_t i2_rtout:1; 1471 uint64_t i1_rtout:1; 1472 uint64_t i0_rtout:1; 1473 uint64_t po3_2sml:1; 1474 uint64_t po2_2sml:1; 1475 uint64_t po1_2sml:1; 1476 uint64_t po0_2sml:1; 1477 uint64_t pci_rsl:1; 1478 uint64_t rml_wto:1; 1479 uint64_t rml_rto:1; 1480 #else 1481 uint64_t rml_rto:1; 1482 uint64_t rml_wto:1; 1483 uint64_t pci_rsl:1; 1484 uint64_t po0_2sml:1; 1485 uint64_t po1_2sml:1; 1486 uint64_t po2_2sml:1; 1487 uint64_t po3_2sml:1; 1488 uint64_t i0_rtout:1; 1489 uint64_t i1_rtout:1; 1490 uint64_t i2_rtout:1; 1491 uint64_t i3_rtout:1; 1492 uint64_t i0_overf:1; 1493 uint64_t i1_overf:1; 1494 uint64_t i2_overf:1; 1495 uint64_t i3_overf:1; 1496 uint64_t p0_rtout:1; 1497 uint64_t p1_rtout:1; 1498 uint64_t p2_rtout:1; 1499 uint64_t p3_rtout:1; 1500 uint64_t p0_perr:1; 1501 uint64_t p1_perr:1; 1502 uint64_t p2_perr:1; 1503 uint64_t p3_perr:1; 1504 uint64_t g0_rtout:1; 1505 uint64_t g1_rtout:1; 1506 uint64_t g2_rtout:1; 1507 uint64_t g3_rtout:1; 1508 uint64_t p0_pperr:1; 1509 uint64_t p1_pperr:1; 1510 uint64_t p2_pperr:1; 1511 uint64_t p3_pperr:1; 1512 uint64_t p0_ptout:1; 1513 uint64_t p1_ptout:1; 1514 uint64_t p2_ptout:1; 1515 uint64_t p3_ptout:1; 1516 uint64_t i0_pperr:1; 1517 uint64_t i1_pperr:1; 1518 uint64_t i2_pperr:1; 1519 uint64_t i3_pperr:1; 1520 uint64_t win_rto:1; 1521 uint64_t p_dperr:1; 1522 uint64_t iobdma:1; 1523 uint64_t reserved_42_63:22; 1524 #endif 1525 } cn38xxp2; 1526 }; 1527 1528 union cvmx_npi_lowp_dbell { 1529 uint64_t u64; 1530 struct cvmx_npi_lowp_dbell_s { 1531 #ifdef __BIG_ENDIAN_BITFIELD 1532 uint64_t reserved_16_63:48; 1533 uint64_t dbell:16; 1534 #else 1535 uint64_t dbell:16; 1536 uint64_t reserved_16_63:48; 1537 #endif 1538 } s; 1539 }; 1540 1541 union cvmx_npi_lowp_ibuff_saddr { 1542 uint64_t u64; 1543 struct cvmx_npi_lowp_ibuff_saddr_s { 1544 #ifdef __BIG_ENDIAN_BITFIELD 1545 uint64_t reserved_36_63:28; 1546 uint64_t saddr:36; 1547 #else 1548 uint64_t saddr:36; 1549 uint64_t reserved_36_63:28; 1550 #endif 1551 } s; 1552 }; 1553 1554 union cvmx_npi_mem_access_subidx { 1555 uint64_t u64; 1556 struct cvmx_npi_mem_access_subidx_s { 1557 #ifdef __BIG_ENDIAN_BITFIELD 1558 uint64_t reserved_38_63:26; 1559 uint64_t shortl:1; 1560 uint64_t nmerge:1; 1561 uint64_t esr:2; 1562 uint64_t esw:2; 1563 uint64_t nsr:1; 1564 uint64_t nsw:1; 1565 uint64_t ror:1; 1566 uint64_t row:1; 1567 uint64_t ba:28; 1568 #else 1569 uint64_t ba:28; 1570 uint64_t row:1; 1571 uint64_t ror:1; 1572 uint64_t nsw:1; 1573 uint64_t nsr:1; 1574 uint64_t esw:2; 1575 uint64_t esr:2; 1576 uint64_t nmerge:1; 1577 uint64_t shortl:1; 1578 uint64_t reserved_38_63:26; 1579 #endif 1580 } s; 1581 struct cvmx_npi_mem_access_subidx_cn31xx { 1582 #ifdef __BIG_ENDIAN_BITFIELD 1583 uint64_t reserved_36_63:28; 1584 uint64_t esr:2; 1585 uint64_t esw:2; 1586 uint64_t nsr:1; 1587 uint64_t nsw:1; 1588 uint64_t ror:1; 1589 uint64_t row:1; 1590 uint64_t ba:28; 1591 #else 1592 uint64_t ba:28; 1593 uint64_t row:1; 1594 uint64_t ror:1; 1595 uint64_t nsw:1; 1596 uint64_t nsr:1; 1597 uint64_t esw:2; 1598 uint64_t esr:2; 1599 uint64_t reserved_36_63:28; 1600 #endif 1601 } cn31xx; 1602 }; 1603 1604 union cvmx_npi_msi_rcv { 1605 uint64_t u64; 1606 struct cvmx_npi_msi_rcv_s { 1607 #ifdef __BIG_ENDIAN_BITFIELD 1608 uint64_t int_vec:64; 1609 #else 1610 uint64_t int_vec:64; 1611 #endif 1612 } s; 1613 }; 1614 1615 union cvmx_npi_num_desc_outputx { 1616 uint64_t u64; 1617 struct cvmx_npi_num_desc_outputx_s { 1618 #ifdef __BIG_ENDIAN_BITFIELD 1619 uint64_t reserved_32_63:32; 1620 uint64_t size:32; 1621 #else 1622 uint64_t size:32; 1623 uint64_t reserved_32_63:32; 1624 #endif 1625 } s; 1626 }; 1627 1628 union cvmx_npi_output_control { 1629 uint64_t u64; 1630 struct cvmx_npi_output_control_s { 1631 #ifdef __BIG_ENDIAN_BITFIELD 1632 uint64_t reserved_49_63:15; 1633 uint64_t pkt_rr:1; 1634 uint64_t p3_bmode:1; 1635 uint64_t p2_bmode:1; 1636 uint64_t p1_bmode:1; 1637 uint64_t p0_bmode:1; 1638 uint64_t o3_es:2; 1639 uint64_t o3_ns:1; 1640 uint64_t o3_ro:1; 1641 uint64_t o2_es:2; 1642 uint64_t o2_ns:1; 1643 uint64_t o2_ro:1; 1644 uint64_t o1_es:2; 1645 uint64_t o1_ns:1; 1646 uint64_t o1_ro:1; 1647 uint64_t o0_es:2; 1648 uint64_t o0_ns:1; 1649 uint64_t o0_ro:1; 1650 uint64_t o3_csrm:1; 1651 uint64_t o2_csrm:1; 1652 uint64_t o1_csrm:1; 1653 uint64_t o0_csrm:1; 1654 uint64_t reserved_20_23:4; 1655 uint64_t iptr_o3:1; 1656 uint64_t iptr_o2:1; 1657 uint64_t iptr_o1:1; 1658 uint64_t iptr_o0:1; 1659 uint64_t esr_sl3:2; 1660 uint64_t nsr_sl3:1; 1661 uint64_t ror_sl3:1; 1662 uint64_t esr_sl2:2; 1663 uint64_t nsr_sl2:1; 1664 uint64_t ror_sl2:1; 1665 uint64_t esr_sl1:2; 1666 uint64_t nsr_sl1:1; 1667 uint64_t ror_sl1:1; 1668 uint64_t esr_sl0:2; 1669 uint64_t nsr_sl0:1; 1670 uint64_t ror_sl0:1; 1671 #else 1672 uint64_t ror_sl0:1; 1673 uint64_t nsr_sl0:1; 1674 uint64_t esr_sl0:2; 1675 uint64_t ror_sl1:1; 1676 uint64_t nsr_sl1:1; 1677 uint64_t esr_sl1:2; 1678 uint64_t ror_sl2:1; 1679 uint64_t nsr_sl2:1; 1680 uint64_t esr_sl2:2; 1681 uint64_t ror_sl3:1; 1682 uint64_t nsr_sl3:1; 1683 uint64_t esr_sl3:2; 1684 uint64_t iptr_o0:1; 1685 uint64_t iptr_o1:1; 1686 uint64_t iptr_o2:1; 1687 uint64_t iptr_o3:1; 1688 uint64_t reserved_20_23:4; 1689 uint64_t o0_csrm:1; 1690 uint64_t o1_csrm:1; 1691 uint64_t o2_csrm:1; 1692 uint64_t o3_csrm:1; 1693 uint64_t o0_ro:1; 1694 uint64_t o0_ns:1; 1695 uint64_t o0_es:2; 1696 uint64_t o1_ro:1; 1697 uint64_t o1_ns:1; 1698 uint64_t o1_es:2; 1699 uint64_t o2_ro:1; 1700 uint64_t o2_ns:1; 1701 uint64_t o2_es:2; 1702 uint64_t o3_ro:1; 1703 uint64_t o3_ns:1; 1704 uint64_t o3_es:2; 1705 uint64_t p0_bmode:1; 1706 uint64_t p1_bmode:1; 1707 uint64_t p2_bmode:1; 1708 uint64_t p3_bmode:1; 1709 uint64_t pkt_rr:1; 1710 uint64_t reserved_49_63:15; 1711 #endif 1712 } s; 1713 struct cvmx_npi_output_control_cn30xx { 1714 #ifdef __BIG_ENDIAN_BITFIELD 1715 uint64_t reserved_45_63:19; 1716 uint64_t p0_bmode:1; 1717 uint64_t reserved_32_43:12; 1718 uint64_t o0_es:2; 1719 uint64_t o0_ns:1; 1720 uint64_t o0_ro:1; 1721 uint64_t reserved_25_27:3; 1722 uint64_t o0_csrm:1; 1723 uint64_t reserved_17_23:7; 1724 uint64_t iptr_o0:1; 1725 uint64_t reserved_4_15:12; 1726 uint64_t esr_sl0:2; 1727 uint64_t nsr_sl0:1; 1728 uint64_t ror_sl0:1; 1729 #else 1730 uint64_t ror_sl0:1; 1731 uint64_t nsr_sl0:1; 1732 uint64_t esr_sl0:2; 1733 uint64_t reserved_4_15:12; 1734 uint64_t iptr_o0:1; 1735 uint64_t reserved_17_23:7; 1736 uint64_t o0_csrm:1; 1737 uint64_t reserved_25_27:3; 1738 uint64_t o0_ro:1; 1739 uint64_t o0_ns:1; 1740 uint64_t o0_es:2; 1741 uint64_t reserved_32_43:12; 1742 uint64_t p0_bmode:1; 1743 uint64_t reserved_45_63:19; 1744 #endif 1745 } cn30xx; 1746 struct cvmx_npi_output_control_cn31xx { 1747 #ifdef __BIG_ENDIAN_BITFIELD 1748 uint64_t reserved_46_63:18; 1749 uint64_t p1_bmode:1; 1750 uint64_t p0_bmode:1; 1751 uint64_t reserved_36_43:8; 1752 uint64_t o1_es:2; 1753 uint64_t o1_ns:1; 1754 uint64_t o1_ro:1; 1755 uint64_t o0_es:2; 1756 uint64_t o0_ns:1; 1757 uint64_t o0_ro:1; 1758 uint64_t reserved_26_27:2; 1759 uint64_t o1_csrm:1; 1760 uint64_t o0_csrm:1; 1761 uint64_t reserved_18_23:6; 1762 uint64_t iptr_o1:1; 1763 uint64_t iptr_o0:1; 1764 uint64_t reserved_8_15:8; 1765 uint64_t esr_sl1:2; 1766 uint64_t nsr_sl1:1; 1767 uint64_t ror_sl1:1; 1768 uint64_t esr_sl0:2; 1769 uint64_t nsr_sl0:1; 1770 uint64_t ror_sl0:1; 1771 #else 1772 uint64_t ror_sl0:1; 1773 uint64_t nsr_sl0:1; 1774 uint64_t esr_sl0:2; 1775 uint64_t ror_sl1:1; 1776 uint64_t nsr_sl1:1; 1777 uint64_t esr_sl1:2; 1778 uint64_t reserved_8_15:8; 1779 uint64_t iptr_o0:1; 1780 uint64_t iptr_o1:1; 1781 uint64_t reserved_18_23:6; 1782 uint64_t o0_csrm:1; 1783 uint64_t o1_csrm:1; 1784 uint64_t reserved_26_27:2; 1785 uint64_t o0_ro:1; 1786 uint64_t o0_ns:1; 1787 uint64_t o0_es:2; 1788 uint64_t o1_ro:1; 1789 uint64_t o1_ns:1; 1790 uint64_t o1_es:2; 1791 uint64_t reserved_36_43:8; 1792 uint64_t p0_bmode:1; 1793 uint64_t p1_bmode:1; 1794 uint64_t reserved_46_63:18; 1795 #endif 1796 } cn31xx; 1797 struct cvmx_npi_output_control_cn38xxp2 { 1798 #ifdef __BIG_ENDIAN_BITFIELD 1799 uint64_t reserved_48_63:16; 1800 uint64_t p3_bmode:1; 1801 uint64_t p2_bmode:1; 1802 uint64_t p1_bmode:1; 1803 uint64_t p0_bmode:1; 1804 uint64_t o3_es:2; 1805 uint64_t o3_ns:1; 1806 uint64_t o3_ro:1; 1807 uint64_t o2_es:2; 1808 uint64_t o2_ns:1; 1809 uint64_t o2_ro:1; 1810 uint64_t o1_es:2; 1811 uint64_t o1_ns:1; 1812 uint64_t o1_ro:1; 1813 uint64_t o0_es:2; 1814 uint64_t o0_ns:1; 1815 uint64_t o0_ro:1; 1816 uint64_t o3_csrm:1; 1817 uint64_t o2_csrm:1; 1818 uint64_t o1_csrm:1; 1819 uint64_t o0_csrm:1; 1820 uint64_t reserved_20_23:4; 1821 uint64_t iptr_o3:1; 1822 uint64_t iptr_o2:1; 1823 uint64_t iptr_o1:1; 1824 uint64_t iptr_o0:1; 1825 uint64_t esr_sl3:2; 1826 uint64_t nsr_sl3:1; 1827 uint64_t ror_sl3:1; 1828 uint64_t esr_sl2:2; 1829 uint64_t nsr_sl2:1; 1830 uint64_t ror_sl2:1; 1831 uint64_t esr_sl1:2; 1832 uint64_t nsr_sl1:1; 1833 uint64_t ror_sl1:1; 1834 uint64_t esr_sl0:2; 1835 uint64_t nsr_sl0:1; 1836 uint64_t ror_sl0:1; 1837 #else 1838 uint64_t ror_sl0:1; 1839 uint64_t nsr_sl0:1; 1840 uint64_t esr_sl0:2; 1841 uint64_t ror_sl1:1; 1842 uint64_t nsr_sl1:1; 1843 uint64_t esr_sl1:2; 1844 uint64_t ror_sl2:1; 1845 uint64_t nsr_sl2:1; 1846 uint64_t esr_sl2:2; 1847 uint64_t ror_sl3:1; 1848 uint64_t nsr_sl3:1; 1849 uint64_t esr_sl3:2; 1850 uint64_t iptr_o0:1; 1851 uint64_t iptr_o1:1; 1852 uint64_t iptr_o2:1; 1853 uint64_t iptr_o3:1; 1854 uint64_t reserved_20_23:4; 1855 uint64_t o0_csrm:1; 1856 uint64_t o1_csrm:1; 1857 uint64_t o2_csrm:1; 1858 uint64_t o3_csrm:1; 1859 uint64_t o0_ro:1; 1860 uint64_t o0_ns:1; 1861 uint64_t o0_es:2; 1862 uint64_t o1_ro:1; 1863 uint64_t o1_ns:1; 1864 uint64_t o1_es:2; 1865 uint64_t o2_ro:1; 1866 uint64_t o2_ns:1; 1867 uint64_t o2_es:2; 1868 uint64_t o3_ro:1; 1869 uint64_t o3_ns:1; 1870 uint64_t o3_es:2; 1871 uint64_t p0_bmode:1; 1872 uint64_t p1_bmode:1; 1873 uint64_t p2_bmode:1; 1874 uint64_t p3_bmode:1; 1875 uint64_t reserved_48_63:16; 1876 #endif 1877 } cn38xxp2; 1878 struct cvmx_npi_output_control_cn50xx { 1879 #ifdef __BIG_ENDIAN_BITFIELD 1880 uint64_t reserved_49_63:15; 1881 uint64_t pkt_rr:1; 1882 uint64_t reserved_46_47:2; 1883 uint64_t p1_bmode:1; 1884 uint64_t p0_bmode:1; 1885 uint64_t reserved_36_43:8; 1886 uint64_t o1_es:2; 1887 uint64_t o1_ns:1; 1888 uint64_t o1_ro:1; 1889 uint64_t o0_es:2; 1890 uint64_t o0_ns:1; 1891 uint64_t o0_ro:1; 1892 uint64_t reserved_26_27:2; 1893 uint64_t o1_csrm:1; 1894 uint64_t o0_csrm:1; 1895 uint64_t reserved_18_23:6; 1896 uint64_t iptr_o1:1; 1897 uint64_t iptr_o0:1; 1898 uint64_t reserved_8_15:8; 1899 uint64_t esr_sl1:2; 1900 uint64_t nsr_sl1:1; 1901 uint64_t ror_sl1:1; 1902 uint64_t esr_sl0:2; 1903 uint64_t nsr_sl0:1; 1904 uint64_t ror_sl0:1; 1905 #else 1906 uint64_t ror_sl0:1; 1907 uint64_t nsr_sl0:1; 1908 uint64_t esr_sl0:2; 1909 uint64_t ror_sl1:1; 1910 uint64_t nsr_sl1:1; 1911 uint64_t esr_sl1:2; 1912 uint64_t reserved_8_15:8; 1913 uint64_t iptr_o0:1; 1914 uint64_t iptr_o1:1; 1915 uint64_t reserved_18_23:6; 1916 uint64_t o0_csrm:1; 1917 uint64_t o1_csrm:1; 1918 uint64_t reserved_26_27:2; 1919 uint64_t o0_ro:1; 1920 uint64_t o0_ns:1; 1921 uint64_t o0_es:2; 1922 uint64_t o1_ro:1; 1923 uint64_t o1_ns:1; 1924 uint64_t o1_es:2; 1925 uint64_t reserved_36_43:8; 1926 uint64_t p0_bmode:1; 1927 uint64_t p1_bmode:1; 1928 uint64_t reserved_46_47:2; 1929 uint64_t pkt_rr:1; 1930 uint64_t reserved_49_63:15; 1931 #endif 1932 } cn50xx; 1933 }; 1934 1935 union cvmx_npi_px_dbpair_addr { 1936 uint64_t u64; 1937 struct cvmx_npi_px_dbpair_addr_s { 1938 #ifdef __BIG_ENDIAN_BITFIELD 1939 uint64_t reserved_63_63:1; 1940 uint64_t state:2; 1941 uint64_t naddr:61; 1942 #else 1943 uint64_t naddr:61; 1944 uint64_t state:2; 1945 uint64_t reserved_63_63:1; 1946 #endif 1947 } s; 1948 }; 1949 1950 union cvmx_npi_px_instr_addr { 1951 uint64_t u64; 1952 struct cvmx_npi_px_instr_addr_s { 1953 #ifdef __BIG_ENDIAN_BITFIELD 1954 uint64_t state:3; 1955 uint64_t naddr:61; 1956 #else 1957 uint64_t naddr:61; 1958 uint64_t state:3; 1959 #endif 1960 } s; 1961 }; 1962 1963 union cvmx_npi_px_instr_cnts { 1964 uint64_t u64; 1965 struct cvmx_npi_px_instr_cnts_s { 1966 #ifdef __BIG_ENDIAN_BITFIELD 1967 uint64_t reserved_38_63:26; 1968 uint64_t fcnt:6; 1969 uint64_t avail:32; 1970 #else 1971 uint64_t avail:32; 1972 uint64_t fcnt:6; 1973 uint64_t reserved_38_63:26; 1974 #endif 1975 } s; 1976 }; 1977 1978 union cvmx_npi_px_pair_cnts { 1979 uint64_t u64; 1980 struct cvmx_npi_px_pair_cnts_s { 1981 #ifdef __BIG_ENDIAN_BITFIELD 1982 uint64_t reserved_37_63:27; 1983 uint64_t fcnt:5; 1984 uint64_t avail:32; 1985 #else 1986 uint64_t avail:32; 1987 uint64_t fcnt:5; 1988 uint64_t reserved_37_63:27; 1989 #endif 1990 } s; 1991 }; 1992 1993 union cvmx_npi_pci_burst_size { 1994 uint64_t u64; 1995 struct cvmx_npi_pci_burst_size_s { 1996 #ifdef __BIG_ENDIAN_BITFIELD 1997 uint64_t reserved_14_63:50; 1998 uint64_t wr_brst:7; 1999 uint64_t rd_brst:7; 2000 #else 2001 uint64_t rd_brst:7; 2002 uint64_t wr_brst:7; 2003 uint64_t reserved_14_63:50; 2004 #endif 2005 } s; 2006 }; 2007 2008 union cvmx_npi_pci_int_arb_cfg { 2009 uint64_t u64; 2010 struct cvmx_npi_pci_int_arb_cfg_s { 2011 #ifdef __BIG_ENDIAN_BITFIELD 2012 uint64_t reserved_13_63:51; 2013 uint64_t hostmode:1; 2014 uint64_t pci_ovr:4; 2015 uint64_t reserved_5_7:3; 2016 uint64_t en:1; 2017 uint64_t park_mod:1; 2018 uint64_t park_dev:3; 2019 #else 2020 uint64_t park_dev:3; 2021 uint64_t park_mod:1; 2022 uint64_t en:1; 2023 uint64_t reserved_5_7:3; 2024 uint64_t pci_ovr:4; 2025 uint64_t hostmode:1; 2026 uint64_t reserved_13_63:51; 2027 #endif 2028 } s; 2029 struct cvmx_npi_pci_int_arb_cfg_cn30xx { 2030 #ifdef __BIG_ENDIAN_BITFIELD 2031 uint64_t reserved_5_63:59; 2032 uint64_t en:1; 2033 uint64_t park_mod:1; 2034 uint64_t park_dev:3; 2035 #else 2036 uint64_t park_dev:3; 2037 uint64_t park_mod:1; 2038 uint64_t en:1; 2039 uint64_t reserved_5_63:59; 2040 #endif 2041 } cn30xx; 2042 }; 2043 2044 union cvmx_npi_pci_read_cmd { 2045 uint64_t u64; 2046 struct cvmx_npi_pci_read_cmd_s { 2047 #ifdef __BIG_ENDIAN_BITFIELD 2048 uint64_t reserved_11_63:53; 2049 uint64_t cmd_size:11; 2050 #else 2051 uint64_t cmd_size:11; 2052 uint64_t reserved_11_63:53; 2053 #endif 2054 } s; 2055 }; 2056 2057 union cvmx_npi_port32_instr_hdr { 2058 uint64_t u64; 2059 struct cvmx_npi_port32_instr_hdr_s { 2060 #ifdef __BIG_ENDIAN_BITFIELD 2061 uint64_t reserved_44_63:20; 2062 uint64_t pbp:1; 2063 uint64_t rsv_f:5; 2064 uint64_t rparmode:2; 2065 uint64_t rsv_e:1; 2066 uint64_t rskp_len:7; 2067 uint64_t rsv_d:6; 2068 uint64_t use_ihdr:1; 2069 uint64_t rsv_c:5; 2070 uint64_t par_mode:2; 2071 uint64_t rsv_b:1; 2072 uint64_t skp_len:7; 2073 uint64_t rsv_a:6; 2074 #else 2075 uint64_t rsv_a:6; 2076 uint64_t skp_len:7; 2077 uint64_t rsv_b:1; 2078 uint64_t par_mode:2; 2079 uint64_t rsv_c:5; 2080 uint64_t use_ihdr:1; 2081 uint64_t rsv_d:6; 2082 uint64_t rskp_len:7; 2083 uint64_t rsv_e:1; 2084 uint64_t rparmode:2; 2085 uint64_t rsv_f:5; 2086 uint64_t pbp:1; 2087 uint64_t reserved_44_63:20; 2088 #endif 2089 } s; 2090 }; 2091 2092 union cvmx_npi_port33_instr_hdr { 2093 uint64_t u64; 2094 struct cvmx_npi_port33_instr_hdr_s { 2095 #ifdef __BIG_ENDIAN_BITFIELD 2096 uint64_t reserved_44_63:20; 2097 uint64_t pbp:1; 2098 uint64_t rsv_f:5; 2099 uint64_t rparmode:2; 2100 uint64_t rsv_e:1; 2101 uint64_t rskp_len:7; 2102 uint64_t rsv_d:6; 2103 uint64_t use_ihdr:1; 2104 uint64_t rsv_c:5; 2105 uint64_t par_mode:2; 2106 uint64_t rsv_b:1; 2107 uint64_t skp_len:7; 2108 uint64_t rsv_a:6; 2109 #else 2110 uint64_t rsv_a:6; 2111 uint64_t skp_len:7; 2112 uint64_t rsv_b:1; 2113 uint64_t par_mode:2; 2114 uint64_t rsv_c:5; 2115 uint64_t use_ihdr:1; 2116 uint64_t rsv_d:6; 2117 uint64_t rskp_len:7; 2118 uint64_t rsv_e:1; 2119 uint64_t rparmode:2; 2120 uint64_t rsv_f:5; 2121 uint64_t pbp:1; 2122 uint64_t reserved_44_63:20; 2123 #endif 2124 } s; 2125 }; 2126 2127 union cvmx_npi_port34_instr_hdr { 2128 uint64_t u64; 2129 struct cvmx_npi_port34_instr_hdr_s { 2130 #ifdef __BIG_ENDIAN_BITFIELD 2131 uint64_t reserved_44_63:20; 2132 uint64_t pbp:1; 2133 uint64_t rsv_f:5; 2134 uint64_t rparmode:2; 2135 uint64_t rsv_e:1; 2136 uint64_t rskp_len:7; 2137 uint64_t rsv_d:6; 2138 uint64_t use_ihdr:1; 2139 uint64_t rsv_c:5; 2140 uint64_t par_mode:2; 2141 uint64_t rsv_b:1; 2142 uint64_t skp_len:7; 2143 uint64_t rsv_a:6; 2144 #else 2145 uint64_t rsv_a:6; 2146 uint64_t skp_len:7; 2147 uint64_t rsv_b:1; 2148 uint64_t par_mode:2; 2149 uint64_t rsv_c:5; 2150 uint64_t use_ihdr:1; 2151 uint64_t rsv_d:6; 2152 uint64_t rskp_len:7; 2153 uint64_t rsv_e:1; 2154 uint64_t rparmode:2; 2155 uint64_t rsv_f:5; 2156 uint64_t pbp:1; 2157 uint64_t reserved_44_63:20; 2158 #endif 2159 } s; 2160 }; 2161 2162 union cvmx_npi_port35_instr_hdr { 2163 uint64_t u64; 2164 struct cvmx_npi_port35_instr_hdr_s { 2165 #ifdef __BIG_ENDIAN_BITFIELD 2166 uint64_t reserved_44_63:20; 2167 uint64_t pbp:1; 2168 uint64_t rsv_f:5; 2169 uint64_t rparmode:2; 2170 uint64_t rsv_e:1; 2171 uint64_t rskp_len:7; 2172 uint64_t rsv_d:6; 2173 uint64_t use_ihdr:1; 2174 uint64_t rsv_c:5; 2175 uint64_t par_mode:2; 2176 uint64_t rsv_b:1; 2177 uint64_t skp_len:7; 2178 uint64_t rsv_a:6; 2179 #else 2180 uint64_t rsv_a:6; 2181 uint64_t skp_len:7; 2182 uint64_t rsv_b:1; 2183 uint64_t par_mode:2; 2184 uint64_t rsv_c:5; 2185 uint64_t use_ihdr:1; 2186 uint64_t rsv_d:6; 2187 uint64_t rskp_len:7; 2188 uint64_t rsv_e:1; 2189 uint64_t rparmode:2; 2190 uint64_t rsv_f:5; 2191 uint64_t pbp:1; 2192 uint64_t reserved_44_63:20; 2193 #endif 2194 } s; 2195 }; 2196 2197 union cvmx_npi_port_bp_control { 2198 uint64_t u64; 2199 struct cvmx_npi_port_bp_control_s { 2200 #ifdef __BIG_ENDIAN_BITFIELD 2201 uint64_t reserved_8_63:56; 2202 uint64_t bp_on:4; 2203 uint64_t enb:4; 2204 #else 2205 uint64_t enb:4; 2206 uint64_t bp_on:4; 2207 uint64_t reserved_8_63:56; 2208 #endif 2209 } s; 2210 }; 2211 2212 union cvmx_npi_rsl_int_blocks { 2213 uint64_t u64; 2214 struct cvmx_npi_rsl_int_blocks_s { 2215 #ifdef __BIG_ENDIAN_BITFIELD 2216 uint64_t reserved_32_63:32; 2217 uint64_t rint_31:1; 2218 uint64_t iob:1; 2219 uint64_t reserved_28_29:2; 2220 uint64_t rint_27:1; 2221 uint64_t rint_26:1; 2222 uint64_t rint_25:1; 2223 uint64_t rint_24:1; 2224 uint64_t asx1:1; 2225 uint64_t asx0:1; 2226 uint64_t rint_21:1; 2227 uint64_t pip:1; 2228 uint64_t spx1:1; 2229 uint64_t spx0:1; 2230 uint64_t lmc:1; 2231 uint64_t l2c:1; 2232 uint64_t rint_15:1; 2233 uint64_t reserved_13_14:2; 2234 uint64_t pow:1; 2235 uint64_t tim:1; 2236 uint64_t pko:1; 2237 uint64_t ipd:1; 2238 uint64_t rint_8:1; 2239 uint64_t zip:1; 2240 uint64_t dfa:1; 2241 uint64_t fpa:1; 2242 uint64_t key:1; 2243 uint64_t npi:1; 2244 uint64_t gmx1:1; 2245 uint64_t gmx0:1; 2246 uint64_t mio:1; 2247 #else 2248 uint64_t mio:1; 2249 uint64_t gmx0:1; 2250 uint64_t gmx1:1; 2251 uint64_t npi:1; 2252 uint64_t key:1; 2253 uint64_t fpa:1; 2254 uint64_t dfa:1; 2255 uint64_t zip:1; 2256 uint64_t rint_8:1; 2257 uint64_t ipd:1; 2258 uint64_t pko:1; 2259 uint64_t tim:1; 2260 uint64_t pow:1; 2261 uint64_t reserved_13_14:2; 2262 uint64_t rint_15:1; 2263 uint64_t l2c:1; 2264 uint64_t lmc:1; 2265 uint64_t spx0:1; 2266 uint64_t spx1:1; 2267 uint64_t pip:1; 2268 uint64_t rint_21:1; 2269 uint64_t asx0:1; 2270 uint64_t asx1:1; 2271 uint64_t rint_24:1; 2272 uint64_t rint_25:1; 2273 uint64_t rint_26:1; 2274 uint64_t rint_27:1; 2275 uint64_t reserved_28_29:2; 2276 uint64_t iob:1; 2277 uint64_t rint_31:1; 2278 uint64_t reserved_32_63:32; 2279 #endif 2280 } s; 2281 struct cvmx_npi_rsl_int_blocks_cn30xx { 2282 #ifdef __BIG_ENDIAN_BITFIELD 2283 uint64_t reserved_32_63:32; 2284 uint64_t rint_31:1; 2285 uint64_t iob:1; 2286 uint64_t rint_29:1; 2287 uint64_t rint_28:1; 2288 uint64_t rint_27:1; 2289 uint64_t rint_26:1; 2290 uint64_t rint_25:1; 2291 uint64_t rint_24:1; 2292 uint64_t asx1:1; 2293 uint64_t asx0:1; 2294 uint64_t rint_21:1; 2295 uint64_t pip:1; 2296 uint64_t spx1:1; 2297 uint64_t spx0:1; 2298 uint64_t lmc:1; 2299 uint64_t l2c:1; 2300 uint64_t rint_15:1; 2301 uint64_t rint_14:1; 2302 uint64_t usb:1; 2303 uint64_t pow:1; 2304 uint64_t tim:1; 2305 uint64_t pko:1; 2306 uint64_t ipd:1; 2307 uint64_t rint_8:1; 2308 uint64_t zip:1; 2309 uint64_t dfa:1; 2310 uint64_t fpa:1; 2311 uint64_t key:1; 2312 uint64_t npi:1; 2313 uint64_t gmx1:1; 2314 uint64_t gmx0:1; 2315 uint64_t mio:1; 2316 #else 2317 uint64_t mio:1; 2318 uint64_t gmx0:1; 2319 uint64_t gmx1:1; 2320 uint64_t npi:1; 2321 uint64_t key:1; 2322 uint64_t fpa:1; 2323 uint64_t dfa:1; 2324 uint64_t zip:1; 2325 uint64_t rint_8:1; 2326 uint64_t ipd:1; 2327 uint64_t pko:1; 2328 uint64_t tim:1; 2329 uint64_t pow:1; 2330 uint64_t usb:1; 2331 uint64_t rint_14:1; 2332 uint64_t rint_15:1; 2333 uint64_t l2c:1; 2334 uint64_t lmc:1; 2335 uint64_t spx0:1; 2336 uint64_t spx1:1; 2337 uint64_t pip:1; 2338 uint64_t rint_21:1; 2339 uint64_t asx0:1; 2340 uint64_t asx1:1; 2341 uint64_t rint_24:1; 2342 uint64_t rint_25:1; 2343 uint64_t rint_26:1; 2344 uint64_t rint_27:1; 2345 uint64_t rint_28:1; 2346 uint64_t rint_29:1; 2347 uint64_t iob:1; 2348 uint64_t rint_31:1; 2349 uint64_t reserved_32_63:32; 2350 #endif 2351 } cn30xx; 2352 struct cvmx_npi_rsl_int_blocks_cn38xx { 2353 #ifdef __BIG_ENDIAN_BITFIELD 2354 uint64_t reserved_32_63:32; 2355 uint64_t rint_31:1; 2356 uint64_t iob:1; 2357 uint64_t rint_29:1; 2358 uint64_t rint_28:1; 2359 uint64_t rint_27:1; 2360 uint64_t rint_26:1; 2361 uint64_t rint_25:1; 2362 uint64_t rint_24:1; 2363 uint64_t asx1:1; 2364 uint64_t asx0:1; 2365 uint64_t rint_21:1; 2366 uint64_t pip:1; 2367 uint64_t spx1:1; 2368 uint64_t spx0:1; 2369 uint64_t lmc:1; 2370 uint64_t l2c:1; 2371 uint64_t rint_15:1; 2372 uint64_t rint_14:1; 2373 uint64_t rint_13:1; 2374 uint64_t pow:1; 2375 uint64_t tim:1; 2376 uint64_t pko:1; 2377 uint64_t ipd:1; 2378 uint64_t rint_8:1; 2379 uint64_t zip:1; 2380 uint64_t dfa:1; 2381 uint64_t fpa:1; 2382 uint64_t key:1; 2383 uint64_t npi:1; 2384 uint64_t gmx1:1; 2385 uint64_t gmx0:1; 2386 uint64_t mio:1; 2387 #else 2388 uint64_t mio:1; 2389 uint64_t gmx0:1; 2390 uint64_t gmx1:1; 2391 uint64_t npi:1; 2392 uint64_t key:1; 2393 uint64_t fpa:1; 2394 uint64_t dfa:1; 2395 uint64_t zip:1; 2396 uint64_t rint_8:1; 2397 uint64_t ipd:1; 2398 uint64_t pko:1; 2399 uint64_t tim:1; 2400 uint64_t pow:1; 2401 uint64_t rint_13:1; 2402 uint64_t rint_14:1; 2403 uint64_t rint_15:1; 2404 uint64_t l2c:1; 2405 uint64_t lmc:1; 2406 uint64_t spx0:1; 2407 uint64_t spx1:1; 2408 uint64_t pip:1; 2409 uint64_t rint_21:1; 2410 uint64_t asx0:1; 2411 uint64_t asx1:1; 2412 uint64_t rint_24:1; 2413 uint64_t rint_25:1; 2414 uint64_t rint_26:1; 2415 uint64_t rint_27:1; 2416 uint64_t rint_28:1; 2417 uint64_t rint_29:1; 2418 uint64_t iob:1; 2419 uint64_t rint_31:1; 2420 uint64_t reserved_32_63:32; 2421 #endif 2422 } cn38xx; 2423 struct cvmx_npi_rsl_int_blocks_cn50xx { 2424 #ifdef __BIG_ENDIAN_BITFIELD 2425 uint64_t reserved_31_63:33; 2426 uint64_t iob:1; 2427 uint64_t lmc1:1; 2428 uint64_t agl:1; 2429 uint64_t reserved_24_27:4; 2430 uint64_t asx1:1; 2431 uint64_t asx0:1; 2432 uint64_t reserved_21_21:1; 2433 uint64_t pip:1; 2434 uint64_t spx1:1; 2435 uint64_t spx0:1; 2436 uint64_t lmc:1; 2437 uint64_t l2c:1; 2438 uint64_t reserved_15_15:1; 2439 uint64_t rad:1; 2440 uint64_t usb:1; 2441 uint64_t pow:1; 2442 uint64_t tim:1; 2443 uint64_t pko:1; 2444 uint64_t ipd:1; 2445 uint64_t reserved_8_8:1; 2446 uint64_t zip:1; 2447 uint64_t dfa:1; 2448 uint64_t fpa:1; 2449 uint64_t key:1; 2450 uint64_t npi:1; 2451 uint64_t gmx1:1; 2452 uint64_t gmx0:1; 2453 uint64_t mio:1; 2454 #else 2455 uint64_t mio:1; 2456 uint64_t gmx0:1; 2457 uint64_t gmx1:1; 2458 uint64_t npi:1; 2459 uint64_t key:1; 2460 uint64_t fpa:1; 2461 uint64_t dfa:1; 2462 uint64_t zip:1; 2463 uint64_t reserved_8_8:1; 2464 uint64_t ipd:1; 2465 uint64_t pko:1; 2466 uint64_t tim:1; 2467 uint64_t pow:1; 2468 uint64_t usb:1; 2469 uint64_t rad:1; 2470 uint64_t reserved_15_15:1; 2471 uint64_t l2c:1; 2472 uint64_t lmc:1; 2473 uint64_t spx0:1; 2474 uint64_t spx1:1; 2475 uint64_t pip:1; 2476 uint64_t reserved_21_21:1; 2477 uint64_t asx0:1; 2478 uint64_t asx1:1; 2479 uint64_t reserved_24_27:4; 2480 uint64_t agl:1; 2481 uint64_t lmc1:1; 2482 uint64_t iob:1; 2483 uint64_t reserved_31_63:33; 2484 #endif 2485 } cn50xx; 2486 }; 2487 2488 union cvmx_npi_size_inputx { 2489 uint64_t u64; 2490 struct cvmx_npi_size_inputx_s { 2491 #ifdef __BIG_ENDIAN_BITFIELD 2492 uint64_t reserved_32_63:32; 2493 uint64_t size:32; 2494 #else 2495 uint64_t size:32; 2496 uint64_t reserved_32_63:32; 2497 #endif 2498 } s; 2499 }; 2500 2501 union cvmx_npi_win_read_to { 2502 uint64_t u64; 2503 struct cvmx_npi_win_read_to_s { 2504 #ifdef __BIG_ENDIAN_BITFIELD 2505 uint64_t reserved_32_63:32; 2506 uint64_t time:32; 2507 #else 2508 uint64_t time:32; 2509 uint64_t reserved_32_63:32; 2510 #endif 2511 } s; 2512 }; 2513 2514 #endif 2515