1 /***********************license start*************** 2 * Author: Cavium Inc. 3 * 4 * Contact: support@cavium.com 5 * This file is part of the OCTEON SDK 6 * 7 * Copyright (c) 2003-2012 Cavium Inc. 8 * 9 * This file is free software; you can redistribute it and/or modify 10 * it under the terms of the GNU General Public License, Version 2, as 11 * published by the Free Software Foundation. 12 * 13 * This file is distributed in the hope that it will be useful, but 14 * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty 15 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or 16 * NONINFRINGEMENT. See the GNU General Public License for more 17 * details. 18 * 19 * You should have received a copy of the GNU General Public License 20 * along with this file; if not, write to the Free Software 21 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA 22 * or visit http://www.gnu.org/licenses/. 23 * 24 * This file may also be available under a different license from Cavium. 25 * Contact Cavium Inc. for more information 26 ***********************license end**************************************/ 27 28 #ifndef __CVMX_LMCX_DEFS_H__ 29 #define __CVMX_LMCX_DEFS_H__ 30 31 #define CVMX_LMCX_BIST_CTL(block_id) (CVMX_ADD_IO_SEG(0x00011800880000F0ull) + ((block_id) & 1) * 0x60000000ull) 32 #define CVMX_LMCX_BIST_RESULT(block_id) (CVMX_ADD_IO_SEG(0x00011800880000F8ull) + ((block_id) & 1) * 0x60000000ull) 33 #define CVMX_LMCX_CHAR_CTL(block_id) (CVMX_ADD_IO_SEG(0x0001180088000220ull) + ((block_id) & 3) * 0x1000000ull) 34 #define CVMX_LMCX_CHAR_MASK0(block_id) (CVMX_ADD_IO_SEG(0x0001180088000228ull) + ((block_id) & 3) * 0x1000000ull) 35 #define CVMX_LMCX_CHAR_MASK1(block_id) (CVMX_ADD_IO_SEG(0x0001180088000230ull) + ((block_id) & 3) * 0x1000000ull) 36 #define CVMX_LMCX_CHAR_MASK2(block_id) (CVMX_ADD_IO_SEG(0x0001180088000238ull) + ((block_id) & 3) * 0x1000000ull) 37 #define CVMX_LMCX_CHAR_MASK3(block_id) (CVMX_ADD_IO_SEG(0x0001180088000240ull) + ((block_id) & 3) * 0x1000000ull) 38 #define CVMX_LMCX_CHAR_MASK4(block_id) (CVMX_ADD_IO_SEG(0x0001180088000318ull) + ((block_id) & 3) * 0x1000000ull) 39 #define CVMX_LMCX_COMP_CTL(block_id) (CVMX_ADD_IO_SEG(0x0001180088000028ull) + ((block_id) & 1) * 0x60000000ull) 40 #define CVMX_LMCX_COMP_CTL2(block_id) (CVMX_ADD_IO_SEG(0x00011800880001B8ull) + ((block_id) & 3) * 0x1000000ull) 41 #define CVMX_LMCX_CONFIG(block_id) (CVMX_ADD_IO_SEG(0x0001180088000188ull) + ((block_id) & 3) * 0x1000000ull) 42 #define CVMX_LMCX_CONTROL(block_id) (CVMX_ADD_IO_SEG(0x0001180088000190ull) + ((block_id) & 3) * 0x1000000ull) 43 #define CVMX_LMCX_CTL(block_id) (CVMX_ADD_IO_SEG(0x0001180088000010ull) + ((block_id) & 1) * 0x60000000ull) 44 #define CVMX_LMCX_CTL1(block_id) (CVMX_ADD_IO_SEG(0x0001180088000090ull) + ((block_id) & 1) * 0x60000000ull) 45 #define CVMX_LMCX_DCLK_CNT(block_id) (CVMX_ADD_IO_SEG(0x00011800880001E0ull) + ((block_id) & 3) * 0x1000000ull) 46 #define CVMX_LMCX_DCLK_CNT_HI(block_id) (CVMX_ADD_IO_SEG(0x0001180088000070ull) + ((block_id) & 1) * 0x60000000ull) 47 #define CVMX_LMCX_DCLK_CNT_LO(block_id) (CVMX_ADD_IO_SEG(0x0001180088000068ull) + ((block_id) & 1) * 0x60000000ull) 48 #define CVMX_LMCX_DCLK_CTL(block_id) (CVMX_ADD_IO_SEG(0x00011800880000B8ull) + ((block_id) & 1) * 0x60000000ull) 49 #define CVMX_LMCX_DDR2_CTL(block_id) (CVMX_ADD_IO_SEG(0x0001180088000018ull) + ((block_id) & 1) * 0x60000000ull) 50 #define CVMX_LMCX_DDR_PLL_CTL(block_id) (CVMX_ADD_IO_SEG(0x0001180088000258ull) + ((block_id) & 3) * 0x1000000ull) 51 #define CVMX_LMCX_DELAY_CFG(block_id) (CVMX_ADD_IO_SEG(0x0001180088000088ull) + ((block_id) & 1) * 0x60000000ull) 52 #define CVMX_LMCX_DIMMX_PARAMS(offset, block_id) (CVMX_ADD_IO_SEG(0x0001180088000270ull) + (((offset) & 1) + ((block_id) & 3) * 0x200000ull) * 8) 53 #define CVMX_LMCX_DIMM_CTL(block_id) (CVMX_ADD_IO_SEG(0x0001180088000310ull) + ((block_id) & 3) * 0x1000000ull) 54 #define CVMX_LMCX_DLL_CTL(block_id) (CVMX_ADD_IO_SEG(0x00011800880000C0ull) + ((block_id) & 1) * 0x60000000ull) 55 #define CVMX_LMCX_DLL_CTL2(block_id) (CVMX_ADD_IO_SEG(0x00011800880001C8ull) + ((block_id) & 3) * 0x1000000ull) 56 #define CVMX_LMCX_DLL_CTL3(block_id) (CVMX_ADD_IO_SEG(0x0001180088000218ull) + ((block_id) & 3) * 0x1000000ull) 57 static inline uint64_t CVMX_LMCX_DUAL_MEMCFG(unsigned long block_id) 58 { 59 switch (cvmx_get_octeon_family()) { 60 case OCTEON_CNF71XX & OCTEON_FAMILY_MASK: 61 case OCTEON_CN50XX & OCTEON_FAMILY_MASK: 62 case OCTEON_CN58XX & OCTEON_FAMILY_MASK: 63 case OCTEON_CN66XX & OCTEON_FAMILY_MASK: 64 case OCTEON_CN52XX & OCTEON_FAMILY_MASK: 65 case OCTEON_CN61XX & OCTEON_FAMILY_MASK: 66 case OCTEON_CN63XX & OCTEON_FAMILY_MASK: 67 return CVMX_ADD_IO_SEG(0x0001180088000098ull) + (block_id) * 0x60000000ull; 68 case OCTEON_CN56XX & OCTEON_FAMILY_MASK: 69 return CVMX_ADD_IO_SEG(0x0001180088000098ull) + (block_id) * 0x60000000ull; 70 case OCTEON_CN68XX & OCTEON_FAMILY_MASK: 71 return CVMX_ADD_IO_SEG(0x0001180088000098ull) + (block_id) * 0x1000000ull; 72 } 73 return CVMX_ADD_IO_SEG(0x0001180088000098ull) + (block_id) * 0x60000000ull; 74 } 75 76 static inline uint64_t CVMX_LMCX_ECC_SYND(unsigned long block_id) 77 { 78 switch (cvmx_get_octeon_family()) { 79 case OCTEON_CN30XX & OCTEON_FAMILY_MASK: 80 case OCTEON_CN50XX & OCTEON_FAMILY_MASK: 81 case OCTEON_CN38XX & OCTEON_FAMILY_MASK: 82 case OCTEON_CN31XX & OCTEON_FAMILY_MASK: 83 case OCTEON_CN58XX & OCTEON_FAMILY_MASK: 84 case OCTEON_CN66XX & OCTEON_FAMILY_MASK: 85 case OCTEON_CN52XX & OCTEON_FAMILY_MASK: 86 case OCTEON_CN61XX & OCTEON_FAMILY_MASK: 87 case OCTEON_CNF71XX & OCTEON_FAMILY_MASK: 88 case OCTEON_CN63XX & OCTEON_FAMILY_MASK: 89 return CVMX_ADD_IO_SEG(0x0001180088000038ull) + (block_id) * 0x60000000ull; 90 case OCTEON_CN56XX & OCTEON_FAMILY_MASK: 91 return CVMX_ADD_IO_SEG(0x0001180088000038ull) + (block_id) * 0x60000000ull; 92 case OCTEON_CN68XX & OCTEON_FAMILY_MASK: 93 return CVMX_ADD_IO_SEG(0x0001180088000038ull) + (block_id) * 0x1000000ull; 94 } 95 return CVMX_ADD_IO_SEG(0x0001180088000038ull) + (block_id) * 0x60000000ull; 96 } 97 98 static inline uint64_t CVMX_LMCX_FADR(unsigned long block_id) 99 { 100 switch (cvmx_get_octeon_family()) { 101 case OCTEON_CN30XX & OCTEON_FAMILY_MASK: 102 case OCTEON_CN50XX & OCTEON_FAMILY_MASK: 103 case OCTEON_CN38XX & OCTEON_FAMILY_MASK: 104 case OCTEON_CN31XX & OCTEON_FAMILY_MASK: 105 case OCTEON_CN58XX & OCTEON_FAMILY_MASK: 106 case OCTEON_CN66XX & OCTEON_FAMILY_MASK: 107 case OCTEON_CN52XX & OCTEON_FAMILY_MASK: 108 case OCTEON_CN61XX & OCTEON_FAMILY_MASK: 109 case OCTEON_CNF71XX & OCTEON_FAMILY_MASK: 110 case OCTEON_CN63XX & OCTEON_FAMILY_MASK: 111 return CVMX_ADD_IO_SEG(0x0001180088000020ull) + (block_id) * 0x60000000ull; 112 case OCTEON_CN56XX & OCTEON_FAMILY_MASK: 113 return CVMX_ADD_IO_SEG(0x0001180088000020ull) + (block_id) * 0x60000000ull; 114 case OCTEON_CN68XX & OCTEON_FAMILY_MASK: 115 return CVMX_ADD_IO_SEG(0x0001180088000020ull) + (block_id) * 0x1000000ull; 116 } 117 return CVMX_ADD_IO_SEG(0x0001180088000020ull) + (block_id) * 0x60000000ull; 118 } 119 120 #define CVMX_LMCX_IFB_CNT(block_id) (CVMX_ADD_IO_SEG(0x00011800880001D0ull) + ((block_id) & 3) * 0x1000000ull) 121 #define CVMX_LMCX_IFB_CNT_HI(block_id) (CVMX_ADD_IO_SEG(0x0001180088000050ull) + ((block_id) & 1) * 0x60000000ull) 122 #define CVMX_LMCX_IFB_CNT_LO(block_id) (CVMX_ADD_IO_SEG(0x0001180088000048ull) + ((block_id) & 1) * 0x60000000ull) 123 #define CVMX_LMCX_INT(block_id) (CVMX_ADD_IO_SEG(0x00011800880001F0ull) + ((block_id) & 3) * 0x1000000ull) 124 #define CVMX_LMCX_INT_EN(block_id) (CVMX_ADD_IO_SEG(0x00011800880001E8ull) + ((block_id) & 3) * 0x1000000ull) 125 #define CVMX_LMCX_MEM_CFG0(block_id) (CVMX_ADD_IO_SEG(0x0001180088000000ull) + ((block_id) & 1) * 0x60000000ull) 126 #define CVMX_LMCX_MEM_CFG1(block_id) (CVMX_ADD_IO_SEG(0x0001180088000008ull) + ((block_id) & 1) * 0x60000000ull) 127 #define CVMX_LMCX_MODEREG_PARAMS0(block_id) (CVMX_ADD_IO_SEG(0x00011800880001A8ull) + ((block_id) & 3) * 0x1000000ull) 128 #define CVMX_LMCX_MODEREG_PARAMS1(block_id) (CVMX_ADD_IO_SEG(0x0001180088000260ull) + ((block_id) & 3) * 0x1000000ull) 129 static inline uint64_t CVMX_LMCX_NXM(unsigned long block_id) 130 { 131 switch (cvmx_get_octeon_family()) { 132 case OCTEON_CNF71XX & OCTEON_FAMILY_MASK: 133 case OCTEON_CN61XX & OCTEON_FAMILY_MASK: 134 case OCTEON_CN66XX & OCTEON_FAMILY_MASK: 135 case OCTEON_CN52XX & OCTEON_FAMILY_MASK: 136 case OCTEON_CN58XX & OCTEON_FAMILY_MASK: 137 case OCTEON_CN63XX & OCTEON_FAMILY_MASK: 138 return CVMX_ADD_IO_SEG(0x00011800880000C8ull) + (block_id) * 0x60000000ull; 139 case OCTEON_CN56XX & OCTEON_FAMILY_MASK: 140 return CVMX_ADD_IO_SEG(0x00011800880000C8ull) + (block_id) * 0x60000000ull; 141 case OCTEON_CN68XX & OCTEON_FAMILY_MASK: 142 return CVMX_ADD_IO_SEG(0x00011800880000C8ull) + (block_id) * 0x1000000ull; 143 } 144 return CVMX_ADD_IO_SEG(0x00011800880000C8ull) + (block_id) * 0x60000000ull; 145 } 146 147 #define CVMX_LMCX_OPS_CNT(block_id) (CVMX_ADD_IO_SEG(0x00011800880001D8ull) + ((block_id) & 3) * 0x1000000ull) 148 #define CVMX_LMCX_OPS_CNT_HI(block_id) (CVMX_ADD_IO_SEG(0x0001180088000060ull) + ((block_id) & 1) * 0x60000000ull) 149 #define CVMX_LMCX_OPS_CNT_LO(block_id) (CVMX_ADD_IO_SEG(0x0001180088000058ull) + ((block_id) & 1) * 0x60000000ull) 150 #define CVMX_LMCX_PHY_CTL(block_id) (CVMX_ADD_IO_SEG(0x0001180088000210ull) + ((block_id) & 3) * 0x1000000ull) 151 #define CVMX_LMCX_PLL_BWCTL(block_id) (CVMX_ADD_IO_SEG(0x0001180088000040ull)) 152 #define CVMX_LMCX_PLL_CTL(block_id) (CVMX_ADD_IO_SEG(0x00011800880000A8ull) + ((block_id) & 1) * 0x60000000ull) 153 #define CVMX_LMCX_PLL_STATUS(block_id) (CVMX_ADD_IO_SEG(0x00011800880000B0ull) + ((block_id) & 1) * 0x60000000ull) 154 #define CVMX_LMCX_READ_LEVEL_CTL(block_id) (CVMX_ADD_IO_SEG(0x0001180088000140ull) + ((block_id) & 1) * 0x60000000ull) 155 #define CVMX_LMCX_READ_LEVEL_DBG(block_id) (CVMX_ADD_IO_SEG(0x0001180088000148ull) + ((block_id) & 1) * 0x60000000ull) 156 #define CVMX_LMCX_READ_LEVEL_RANKX(offset, block_id) (CVMX_ADD_IO_SEG(0x0001180088000100ull) + (((offset) & 3) + ((block_id) & 1) * 0xC000000ull) * 8) 157 #define CVMX_LMCX_RESET_CTL(block_id) (CVMX_ADD_IO_SEG(0x0001180088000180ull) + ((block_id) & 3) * 0x1000000ull) 158 #define CVMX_LMCX_RLEVEL_CTL(block_id) (CVMX_ADD_IO_SEG(0x00011800880002A0ull) + ((block_id) & 3) * 0x1000000ull) 159 #define CVMX_LMCX_RLEVEL_DBG(block_id) (CVMX_ADD_IO_SEG(0x00011800880002A8ull) + ((block_id) & 3) * 0x1000000ull) 160 #define CVMX_LMCX_RLEVEL_RANKX(offset, block_id) (CVMX_ADD_IO_SEG(0x0001180088000280ull) + (((offset) & 3) + ((block_id) & 3) * 0x200000ull) * 8) 161 #define CVMX_LMCX_RODT_COMP_CTL(block_id) (CVMX_ADD_IO_SEG(0x00011800880000A0ull) + ((block_id) & 1) * 0x60000000ull) 162 #define CVMX_LMCX_RODT_CTL(block_id) (CVMX_ADD_IO_SEG(0x0001180088000078ull) + ((block_id) & 1) * 0x60000000ull) 163 #define CVMX_LMCX_RODT_MASK(block_id) (CVMX_ADD_IO_SEG(0x0001180088000268ull) + ((block_id) & 3) * 0x1000000ull) 164 #define CVMX_LMCX_SCRAMBLED_FADR(block_id) (CVMX_ADD_IO_SEG(0x0001180088000330ull)) 165 #define CVMX_LMCX_SCRAMBLE_CFG0(block_id) (CVMX_ADD_IO_SEG(0x0001180088000320ull)) 166 #define CVMX_LMCX_SCRAMBLE_CFG1(block_id) (CVMX_ADD_IO_SEG(0x0001180088000328ull)) 167 #define CVMX_LMCX_SLOT_CTL0(block_id) (CVMX_ADD_IO_SEG(0x00011800880001F8ull) + ((block_id) & 3) * 0x1000000ull) 168 #define CVMX_LMCX_SLOT_CTL1(block_id) (CVMX_ADD_IO_SEG(0x0001180088000200ull) + ((block_id) & 3) * 0x1000000ull) 169 #define CVMX_LMCX_SLOT_CTL2(block_id) (CVMX_ADD_IO_SEG(0x0001180088000208ull) + ((block_id) & 3) * 0x1000000ull) 170 #define CVMX_LMCX_TIMING_PARAMS0(block_id) (CVMX_ADD_IO_SEG(0x0001180088000198ull) + ((block_id) & 3) * 0x1000000ull) 171 #define CVMX_LMCX_TIMING_PARAMS1(block_id) (CVMX_ADD_IO_SEG(0x00011800880001A0ull) + ((block_id) & 3) * 0x1000000ull) 172 #define CVMX_LMCX_TRO_CTL(block_id) (CVMX_ADD_IO_SEG(0x0001180088000248ull) + ((block_id) & 3) * 0x1000000ull) 173 #define CVMX_LMCX_TRO_STAT(block_id) (CVMX_ADD_IO_SEG(0x0001180088000250ull) + ((block_id) & 3) * 0x1000000ull) 174 #define CVMX_LMCX_WLEVEL_CTL(block_id) (CVMX_ADD_IO_SEG(0x0001180088000300ull) + ((block_id) & 3) * 0x1000000ull) 175 #define CVMX_LMCX_WLEVEL_DBG(block_id) (CVMX_ADD_IO_SEG(0x0001180088000308ull) + ((block_id) & 3) * 0x1000000ull) 176 #define CVMX_LMCX_WLEVEL_RANKX(offset, block_id) (CVMX_ADD_IO_SEG(0x00011800880002B0ull) + (((offset) & 3) + ((block_id) & 3) * 0x200000ull) * 8) 177 #define CVMX_LMCX_WODT_CTL0(block_id) (CVMX_ADD_IO_SEG(0x0001180088000030ull) + ((block_id) & 1) * 0x60000000ull) 178 #define CVMX_LMCX_WODT_CTL1(block_id) (CVMX_ADD_IO_SEG(0x0001180088000080ull) + ((block_id) & 1) * 0x60000000ull) 179 #define CVMX_LMCX_WODT_MASK(block_id) (CVMX_ADD_IO_SEG(0x00011800880001B0ull) + ((block_id) & 3) * 0x1000000ull) 180 181 union cvmx_lmcx_bist_ctl { 182 uint64_t u64; 183 struct cvmx_lmcx_bist_ctl_s { 184 #ifdef __BIG_ENDIAN_BITFIELD 185 uint64_t reserved_1_63:63; 186 uint64_t start:1; 187 #else 188 uint64_t start:1; 189 uint64_t reserved_1_63:63; 190 #endif 191 } s; 192 struct cvmx_lmcx_bist_ctl_s cn50xx; 193 struct cvmx_lmcx_bist_ctl_s cn52xx; 194 struct cvmx_lmcx_bist_ctl_s cn52xxp1; 195 struct cvmx_lmcx_bist_ctl_s cn56xx; 196 struct cvmx_lmcx_bist_ctl_s cn56xxp1; 197 }; 198 199 union cvmx_lmcx_bist_result { 200 uint64_t u64; 201 struct cvmx_lmcx_bist_result_s { 202 #ifdef __BIG_ENDIAN_BITFIELD 203 uint64_t reserved_11_63:53; 204 uint64_t csrd2e:1; 205 uint64_t csre2d:1; 206 uint64_t mwf:1; 207 uint64_t mwd:3; 208 uint64_t mwc:1; 209 uint64_t mrf:1; 210 uint64_t mrd:3; 211 #else 212 uint64_t mrd:3; 213 uint64_t mrf:1; 214 uint64_t mwc:1; 215 uint64_t mwd:3; 216 uint64_t mwf:1; 217 uint64_t csre2d:1; 218 uint64_t csrd2e:1; 219 uint64_t reserved_11_63:53; 220 #endif 221 } s; 222 struct cvmx_lmcx_bist_result_cn50xx { 223 #ifdef __BIG_ENDIAN_BITFIELD 224 uint64_t reserved_9_63:55; 225 uint64_t mwf:1; 226 uint64_t mwd:3; 227 uint64_t mwc:1; 228 uint64_t mrf:1; 229 uint64_t mrd:3; 230 #else 231 uint64_t mrd:3; 232 uint64_t mrf:1; 233 uint64_t mwc:1; 234 uint64_t mwd:3; 235 uint64_t mwf:1; 236 uint64_t reserved_9_63:55; 237 #endif 238 } cn50xx; 239 struct cvmx_lmcx_bist_result_s cn52xx; 240 struct cvmx_lmcx_bist_result_s cn52xxp1; 241 struct cvmx_lmcx_bist_result_s cn56xx; 242 struct cvmx_lmcx_bist_result_s cn56xxp1; 243 }; 244 245 union cvmx_lmcx_char_ctl { 246 uint64_t u64; 247 struct cvmx_lmcx_char_ctl_s { 248 #ifdef __BIG_ENDIAN_BITFIELD 249 uint64_t reserved_44_63:20; 250 uint64_t dr:1; 251 uint64_t skew_on:1; 252 uint64_t en:1; 253 uint64_t sel:1; 254 uint64_t prog:8; 255 uint64_t prbs:32; 256 #else 257 uint64_t prbs:32; 258 uint64_t prog:8; 259 uint64_t sel:1; 260 uint64_t en:1; 261 uint64_t skew_on:1; 262 uint64_t dr:1; 263 uint64_t reserved_44_63:20; 264 #endif 265 } s; 266 struct cvmx_lmcx_char_ctl_s cn61xx; 267 struct cvmx_lmcx_char_ctl_cn63xx { 268 #ifdef __BIG_ENDIAN_BITFIELD 269 uint64_t reserved_42_63:22; 270 uint64_t en:1; 271 uint64_t sel:1; 272 uint64_t prog:8; 273 uint64_t prbs:32; 274 #else 275 uint64_t prbs:32; 276 uint64_t prog:8; 277 uint64_t sel:1; 278 uint64_t en:1; 279 uint64_t reserved_42_63:22; 280 #endif 281 } cn63xx; 282 struct cvmx_lmcx_char_ctl_cn63xx cn63xxp1; 283 struct cvmx_lmcx_char_ctl_s cn66xx; 284 struct cvmx_lmcx_char_ctl_s cn68xx; 285 struct cvmx_lmcx_char_ctl_cn63xx cn68xxp1; 286 struct cvmx_lmcx_char_ctl_s cnf71xx; 287 }; 288 289 union cvmx_lmcx_char_mask0 { 290 uint64_t u64; 291 struct cvmx_lmcx_char_mask0_s { 292 #ifdef __BIG_ENDIAN_BITFIELD 293 uint64_t mask:64; 294 #else 295 uint64_t mask:64; 296 #endif 297 } s; 298 struct cvmx_lmcx_char_mask0_s cn61xx; 299 struct cvmx_lmcx_char_mask0_s cn63xx; 300 struct cvmx_lmcx_char_mask0_s cn63xxp1; 301 struct cvmx_lmcx_char_mask0_s cn66xx; 302 struct cvmx_lmcx_char_mask0_s cn68xx; 303 struct cvmx_lmcx_char_mask0_s cn68xxp1; 304 struct cvmx_lmcx_char_mask0_s cnf71xx; 305 }; 306 307 union cvmx_lmcx_char_mask1 { 308 uint64_t u64; 309 struct cvmx_lmcx_char_mask1_s { 310 #ifdef __BIG_ENDIAN_BITFIELD 311 uint64_t reserved_8_63:56; 312 uint64_t mask:8; 313 #else 314 uint64_t mask:8; 315 uint64_t reserved_8_63:56; 316 #endif 317 } s; 318 struct cvmx_lmcx_char_mask1_s cn61xx; 319 struct cvmx_lmcx_char_mask1_s cn63xx; 320 struct cvmx_lmcx_char_mask1_s cn63xxp1; 321 struct cvmx_lmcx_char_mask1_s cn66xx; 322 struct cvmx_lmcx_char_mask1_s cn68xx; 323 struct cvmx_lmcx_char_mask1_s cn68xxp1; 324 struct cvmx_lmcx_char_mask1_s cnf71xx; 325 }; 326 327 union cvmx_lmcx_char_mask2 { 328 uint64_t u64; 329 struct cvmx_lmcx_char_mask2_s { 330 #ifdef __BIG_ENDIAN_BITFIELD 331 uint64_t mask:64; 332 #else 333 uint64_t mask:64; 334 #endif 335 } s; 336 struct cvmx_lmcx_char_mask2_s cn61xx; 337 struct cvmx_lmcx_char_mask2_s cn63xx; 338 struct cvmx_lmcx_char_mask2_s cn63xxp1; 339 struct cvmx_lmcx_char_mask2_s cn66xx; 340 struct cvmx_lmcx_char_mask2_s cn68xx; 341 struct cvmx_lmcx_char_mask2_s cn68xxp1; 342 struct cvmx_lmcx_char_mask2_s cnf71xx; 343 }; 344 345 union cvmx_lmcx_char_mask3 { 346 uint64_t u64; 347 struct cvmx_lmcx_char_mask3_s { 348 #ifdef __BIG_ENDIAN_BITFIELD 349 uint64_t reserved_8_63:56; 350 uint64_t mask:8; 351 #else 352 uint64_t mask:8; 353 uint64_t reserved_8_63:56; 354 #endif 355 } s; 356 struct cvmx_lmcx_char_mask3_s cn61xx; 357 struct cvmx_lmcx_char_mask3_s cn63xx; 358 struct cvmx_lmcx_char_mask3_s cn63xxp1; 359 struct cvmx_lmcx_char_mask3_s cn66xx; 360 struct cvmx_lmcx_char_mask3_s cn68xx; 361 struct cvmx_lmcx_char_mask3_s cn68xxp1; 362 struct cvmx_lmcx_char_mask3_s cnf71xx; 363 }; 364 365 union cvmx_lmcx_char_mask4 { 366 uint64_t u64; 367 struct cvmx_lmcx_char_mask4_s { 368 #ifdef __BIG_ENDIAN_BITFIELD 369 uint64_t reserved_33_63:31; 370 uint64_t reset_n_mask:1; 371 uint64_t a_mask:16; 372 uint64_t ba_mask:3; 373 uint64_t we_n_mask:1; 374 uint64_t cas_n_mask:1; 375 uint64_t ras_n_mask:1; 376 uint64_t odt1_mask:2; 377 uint64_t odt0_mask:2; 378 uint64_t cs1_n_mask:2; 379 uint64_t cs0_n_mask:2; 380 uint64_t cke_mask:2; 381 #else 382 uint64_t cke_mask:2; 383 uint64_t cs0_n_mask:2; 384 uint64_t cs1_n_mask:2; 385 uint64_t odt0_mask:2; 386 uint64_t odt1_mask:2; 387 uint64_t ras_n_mask:1; 388 uint64_t cas_n_mask:1; 389 uint64_t we_n_mask:1; 390 uint64_t ba_mask:3; 391 uint64_t a_mask:16; 392 uint64_t reset_n_mask:1; 393 uint64_t reserved_33_63:31; 394 #endif 395 } s; 396 struct cvmx_lmcx_char_mask4_s cn61xx; 397 struct cvmx_lmcx_char_mask4_s cn63xx; 398 struct cvmx_lmcx_char_mask4_s cn63xxp1; 399 struct cvmx_lmcx_char_mask4_s cn66xx; 400 struct cvmx_lmcx_char_mask4_s cn68xx; 401 struct cvmx_lmcx_char_mask4_s cn68xxp1; 402 struct cvmx_lmcx_char_mask4_s cnf71xx; 403 }; 404 405 union cvmx_lmcx_comp_ctl { 406 uint64_t u64; 407 struct cvmx_lmcx_comp_ctl_s { 408 #ifdef __BIG_ENDIAN_BITFIELD 409 uint64_t reserved_32_63:32; 410 uint64_t nctl_csr:4; 411 uint64_t nctl_clk:4; 412 uint64_t nctl_cmd:4; 413 uint64_t nctl_dat:4; 414 uint64_t pctl_csr:4; 415 uint64_t pctl_clk:4; 416 uint64_t reserved_0_7:8; 417 #else 418 uint64_t reserved_0_7:8; 419 uint64_t pctl_clk:4; 420 uint64_t pctl_csr:4; 421 uint64_t nctl_dat:4; 422 uint64_t nctl_cmd:4; 423 uint64_t nctl_clk:4; 424 uint64_t nctl_csr:4; 425 uint64_t reserved_32_63:32; 426 #endif 427 } s; 428 struct cvmx_lmcx_comp_ctl_cn30xx { 429 #ifdef __BIG_ENDIAN_BITFIELD 430 uint64_t reserved_32_63:32; 431 uint64_t nctl_csr:4; 432 uint64_t nctl_clk:4; 433 uint64_t nctl_cmd:4; 434 uint64_t nctl_dat:4; 435 uint64_t pctl_csr:4; 436 uint64_t pctl_clk:4; 437 uint64_t pctl_cmd:4; 438 uint64_t pctl_dat:4; 439 #else 440 uint64_t pctl_dat:4; 441 uint64_t pctl_cmd:4; 442 uint64_t pctl_clk:4; 443 uint64_t pctl_csr:4; 444 uint64_t nctl_dat:4; 445 uint64_t nctl_cmd:4; 446 uint64_t nctl_clk:4; 447 uint64_t nctl_csr:4; 448 uint64_t reserved_32_63:32; 449 #endif 450 } cn30xx; 451 struct cvmx_lmcx_comp_ctl_cn30xx cn31xx; 452 struct cvmx_lmcx_comp_ctl_cn30xx cn38xx; 453 struct cvmx_lmcx_comp_ctl_cn30xx cn38xxp2; 454 struct cvmx_lmcx_comp_ctl_cn50xx { 455 #ifdef __BIG_ENDIAN_BITFIELD 456 uint64_t reserved_32_63:32; 457 uint64_t nctl_csr:4; 458 uint64_t reserved_20_27:8; 459 uint64_t nctl_dat:4; 460 uint64_t pctl_csr:4; 461 uint64_t reserved_5_11:7; 462 uint64_t pctl_dat:5; 463 #else 464 uint64_t pctl_dat:5; 465 uint64_t reserved_5_11:7; 466 uint64_t pctl_csr:4; 467 uint64_t nctl_dat:4; 468 uint64_t reserved_20_27:8; 469 uint64_t nctl_csr:4; 470 uint64_t reserved_32_63:32; 471 #endif 472 } cn50xx; 473 struct cvmx_lmcx_comp_ctl_cn50xx cn52xx; 474 struct cvmx_lmcx_comp_ctl_cn50xx cn52xxp1; 475 struct cvmx_lmcx_comp_ctl_cn50xx cn56xx; 476 struct cvmx_lmcx_comp_ctl_cn50xx cn56xxp1; 477 struct cvmx_lmcx_comp_ctl_cn50xx cn58xx; 478 struct cvmx_lmcx_comp_ctl_cn58xxp1 { 479 #ifdef __BIG_ENDIAN_BITFIELD 480 uint64_t reserved_32_63:32; 481 uint64_t nctl_csr:4; 482 uint64_t reserved_20_27:8; 483 uint64_t nctl_dat:4; 484 uint64_t pctl_csr:4; 485 uint64_t reserved_4_11:8; 486 uint64_t pctl_dat:4; 487 #else 488 uint64_t pctl_dat:4; 489 uint64_t reserved_4_11:8; 490 uint64_t pctl_csr:4; 491 uint64_t nctl_dat:4; 492 uint64_t reserved_20_27:8; 493 uint64_t nctl_csr:4; 494 uint64_t reserved_32_63:32; 495 #endif 496 } cn58xxp1; 497 }; 498 499 union cvmx_lmcx_comp_ctl2 { 500 uint64_t u64; 501 struct cvmx_lmcx_comp_ctl2_s { 502 #ifdef __BIG_ENDIAN_BITFIELD 503 uint64_t reserved_34_63:30; 504 uint64_t ddr__ptune:4; 505 uint64_t ddr__ntune:4; 506 uint64_t m180:1; 507 uint64_t byp:1; 508 uint64_t ptune:4; 509 uint64_t ntune:4; 510 uint64_t rodt_ctl:4; 511 uint64_t cmd_ctl:4; 512 uint64_t ck_ctl:4; 513 uint64_t dqx_ctl:4; 514 #else 515 uint64_t dqx_ctl:4; 516 uint64_t ck_ctl:4; 517 uint64_t cmd_ctl:4; 518 uint64_t rodt_ctl:4; 519 uint64_t ntune:4; 520 uint64_t ptune:4; 521 uint64_t byp:1; 522 uint64_t m180:1; 523 uint64_t ddr__ntune:4; 524 uint64_t ddr__ptune:4; 525 uint64_t reserved_34_63:30; 526 #endif 527 } s; 528 struct cvmx_lmcx_comp_ctl2_s cn61xx; 529 struct cvmx_lmcx_comp_ctl2_s cn63xx; 530 struct cvmx_lmcx_comp_ctl2_s cn63xxp1; 531 struct cvmx_lmcx_comp_ctl2_s cn66xx; 532 struct cvmx_lmcx_comp_ctl2_s cn68xx; 533 struct cvmx_lmcx_comp_ctl2_s cn68xxp1; 534 struct cvmx_lmcx_comp_ctl2_s cnf71xx; 535 }; 536 537 union cvmx_lmcx_config { 538 uint64_t u64; 539 struct cvmx_lmcx_config_s { 540 #ifdef __BIG_ENDIAN_BITFIELD 541 uint64_t reserved_61_63:3; 542 uint64_t mode32b:1; 543 uint64_t scrz:1; 544 uint64_t early_unload_d1_r1:1; 545 uint64_t early_unload_d1_r0:1; 546 uint64_t early_unload_d0_r1:1; 547 uint64_t early_unload_d0_r0:1; 548 uint64_t init_status:4; 549 uint64_t mirrmask:4; 550 uint64_t rankmask:4; 551 uint64_t rank_ena:1; 552 uint64_t sref_with_dll:1; 553 uint64_t early_dqx:1; 554 uint64_t sequence:3; 555 uint64_t ref_zqcs_int:19; 556 uint64_t reset:1; 557 uint64_t ecc_adr:1; 558 uint64_t forcewrite:4; 559 uint64_t idlepower:3; 560 uint64_t pbank_lsb:4; 561 uint64_t row_lsb:3; 562 uint64_t ecc_ena:1; 563 uint64_t init_start:1; 564 #else 565 uint64_t init_start:1; 566 uint64_t ecc_ena:1; 567 uint64_t row_lsb:3; 568 uint64_t pbank_lsb:4; 569 uint64_t idlepower:3; 570 uint64_t forcewrite:4; 571 uint64_t ecc_adr:1; 572 uint64_t reset:1; 573 uint64_t ref_zqcs_int:19; 574 uint64_t sequence:3; 575 uint64_t early_dqx:1; 576 uint64_t sref_with_dll:1; 577 uint64_t rank_ena:1; 578 uint64_t rankmask:4; 579 uint64_t mirrmask:4; 580 uint64_t init_status:4; 581 uint64_t early_unload_d0_r0:1; 582 uint64_t early_unload_d0_r1:1; 583 uint64_t early_unload_d1_r0:1; 584 uint64_t early_unload_d1_r1:1; 585 uint64_t scrz:1; 586 uint64_t mode32b:1; 587 uint64_t reserved_61_63:3; 588 #endif 589 } s; 590 struct cvmx_lmcx_config_s cn61xx; 591 struct cvmx_lmcx_config_cn63xx { 592 #ifdef __BIG_ENDIAN_BITFIELD 593 uint64_t reserved_59_63:5; 594 uint64_t early_unload_d1_r1:1; 595 uint64_t early_unload_d1_r0:1; 596 uint64_t early_unload_d0_r1:1; 597 uint64_t early_unload_d0_r0:1; 598 uint64_t init_status:4; 599 uint64_t mirrmask:4; 600 uint64_t rankmask:4; 601 uint64_t rank_ena:1; 602 uint64_t sref_with_dll:1; 603 uint64_t early_dqx:1; 604 uint64_t sequence:3; 605 uint64_t ref_zqcs_int:19; 606 uint64_t reset:1; 607 uint64_t ecc_adr:1; 608 uint64_t forcewrite:4; 609 uint64_t idlepower:3; 610 uint64_t pbank_lsb:4; 611 uint64_t row_lsb:3; 612 uint64_t ecc_ena:1; 613 uint64_t init_start:1; 614 #else 615 uint64_t init_start:1; 616 uint64_t ecc_ena:1; 617 uint64_t row_lsb:3; 618 uint64_t pbank_lsb:4; 619 uint64_t idlepower:3; 620 uint64_t forcewrite:4; 621 uint64_t ecc_adr:1; 622 uint64_t reset:1; 623 uint64_t ref_zqcs_int:19; 624 uint64_t sequence:3; 625 uint64_t early_dqx:1; 626 uint64_t sref_with_dll:1; 627 uint64_t rank_ena:1; 628 uint64_t rankmask:4; 629 uint64_t mirrmask:4; 630 uint64_t init_status:4; 631 uint64_t early_unload_d0_r0:1; 632 uint64_t early_unload_d0_r1:1; 633 uint64_t early_unload_d1_r0:1; 634 uint64_t early_unload_d1_r1:1; 635 uint64_t reserved_59_63:5; 636 #endif 637 } cn63xx; 638 struct cvmx_lmcx_config_cn63xxp1 { 639 #ifdef __BIG_ENDIAN_BITFIELD 640 uint64_t reserved_55_63:9; 641 uint64_t init_status:4; 642 uint64_t mirrmask:4; 643 uint64_t rankmask:4; 644 uint64_t rank_ena:1; 645 uint64_t sref_with_dll:1; 646 uint64_t early_dqx:1; 647 uint64_t sequence:3; 648 uint64_t ref_zqcs_int:19; 649 uint64_t reset:1; 650 uint64_t ecc_adr:1; 651 uint64_t forcewrite:4; 652 uint64_t idlepower:3; 653 uint64_t pbank_lsb:4; 654 uint64_t row_lsb:3; 655 uint64_t ecc_ena:1; 656 uint64_t init_start:1; 657 #else 658 uint64_t init_start:1; 659 uint64_t ecc_ena:1; 660 uint64_t row_lsb:3; 661 uint64_t pbank_lsb:4; 662 uint64_t idlepower:3; 663 uint64_t forcewrite:4; 664 uint64_t ecc_adr:1; 665 uint64_t reset:1; 666 uint64_t ref_zqcs_int:19; 667 uint64_t sequence:3; 668 uint64_t early_dqx:1; 669 uint64_t sref_with_dll:1; 670 uint64_t rank_ena:1; 671 uint64_t rankmask:4; 672 uint64_t mirrmask:4; 673 uint64_t init_status:4; 674 uint64_t reserved_55_63:9; 675 #endif 676 } cn63xxp1; 677 struct cvmx_lmcx_config_cn66xx { 678 #ifdef __BIG_ENDIAN_BITFIELD 679 uint64_t reserved_60_63:4; 680 uint64_t scrz:1; 681 uint64_t early_unload_d1_r1:1; 682 uint64_t early_unload_d1_r0:1; 683 uint64_t early_unload_d0_r1:1; 684 uint64_t early_unload_d0_r0:1; 685 uint64_t init_status:4; 686 uint64_t mirrmask:4; 687 uint64_t rankmask:4; 688 uint64_t rank_ena:1; 689 uint64_t sref_with_dll:1; 690 uint64_t early_dqx:1; 691 uint64_t sequence:3; 692 uint64_t ref_zqcs_int:19; 693 uint64_t reset:1; 694 uint64_t ecc_adr:1; 695 uint64_t forcewrite:4; 696 uint64_t idlepower:3; 697 uint64_t pbank_lsb:4; 698 uint64_t row_lsb:3; 699 uint64_t ecc_ena:1; 700 uint64_t init_start:1; 701 #else 702 uint64_t init_start:1; 703 uint64_t ecc_ena:1; 704 uint64_t row_lsb:3; 705 uint64_t pbank_lsb:4; 706 uint64_t idlepower:3; 707 uint64_t forcewrite:4; 708 uint64_t ecc_adr:1; 709 uint64_t reset:1; 710 uint64_t ref_zqcs_int:19; 711 uint64_t sequence:3; 712 uint64_t early_dqx:1; 713 uint64_t sref_with_dll:1; 714 uint64_t rank_ena:1; 715 uint64_t rankmask:4; 716 uint64_t mirrmask:4; 717 uint64_t init_status:4; 718 uint64_t early_unload_d0_r0:1; 719 uint64_t early_unload_d0_r1:1; 720 uint64_t early_unload_d1_r0:1; 721 uint64_t early_unload_d1_r1:1; 722 uint64_t scrz:1; 723 uint64_t reserved_60_63:4; 724 #endif 725 } cn66xx; 726 struct cvmx_lmcx_config_cn63xx cn68xx; 727 struct cvmx_lmcx_config_cn63xx cn68xxp1; 728 struct cvmx_lmcx_config_s cnf71xx; 729 }; 730 731 union cvmx_lmcx_control { 732 uint64_t u64; 733 struct cvmx_lmcx_control_s { 734 #ifdef __BIG_ENDIAN_BITFIELD 735 uint64_t scramble_ena:1; 736 uint64_t thrcnt:12; 737 uint64_t persub:8; 738 uint64_t thrmax:4; 739 uint64_t crm_cnt:5; 740 uint64_t crm_thr:5; 741 uint64_t crm_max:5; 742 uint64_t rodt_bprch:1; 743 uint64_t wodt_bprch:1; 744 uint64_t bprch:2; 745 uint64_t ext_zqcs_dis:1; 746 uint64_t int_zqcs_dis:1; 747 uint64_t auto_dclkdis:1; 748 uint64_t xor_bank:1; 749 uint64_t max_write_batch:4; 750 uint64_t nxm_write_en:1; 751 uint64_t elev_prio_dis:1; 752 uint64_t inorder_wr:1; 753 uint64_t inorder_rd:1; 754 uint64_t throttle_wr:1; 755 uint64_t throttle_rd:1; 756 uint64_t fprch2:2; 757 uint64_t pocas:1; 758 uint64_t ddr2t:1; 759 uint64_t bwcnt:1; 760 uint64_t rdimm_ena:1; 761 #else 762 uint64_t rdimm_ena:1; 763 uint64_t bwcnt:1; 764 uint64_t ddr2t:1; 765 uint64_t pocas:1; 766 uint64_t fprch2:2; 767 uint64_t throttle_rd:1; 768 uint64_t throttle_wr:1; 769 uint64_t inorder_rd:1; 770 uint64_t inorder_wr:1; 771 uint64_t elev_prio_dis:1; 772 uint64_t nxm_write_en:1; 773 uint64_t max_write_batch:4; 774 uint64_t xor_bank:1; 775 uint64_t auto_dclkdis:1; 776 uint64_t int_zqcs_dis:1; 777 uint64_t ext_zqcs_dis:1; 778 uint64_t bprch:2; 779 uint64_t wodt_bprch:1; 780 uint64_t rodt_bprch:1; 781 uint64_t crm_max:5; 782 uint64_t crm_thr:5; 783 uint64_t crm_cnt:5; 784 uint64_t thrmax:4; 785 uint64_t persub:8; 786 uint64_t thrcnt:12; 787 uint64_t scramble_ena:1; 788 #endif 789 } s; 790 struct cvmx_lmcx_control_s cn61xx; 791 struct cvmx_lmcx_control_cn63xx { 792 #ifdef __BIG_ENDIAN_BITFIELD 793 uint64_t reserved_24_63:40; 794 uint64_t rodt_bprch:1; 795 uint64_t wodt_bprch:1; 796 uint64_t bprch:2; 797 uint64_t ext_zqcs_dis:1; 798 uint64_t int_zqcs_dis:1; 799 uint64_t auto_dclkdis:1; 800 uint64_t xor_bank:1; 801 uint64_t max_write_batch:4; 802 uint64_t nxm_write_en:1; 803 uint64_t elev_prio_dis:1; 804 uint64_t inorder_wr:1; 805 uint64_t inorder_rd:1; 806 uint64_t throttle_wr:1; 807 uint64_t throttle_rd:1; 808 uint64_t fprch2:2; 809 uint64_t pocas:1; 810 uint64_t ddr2t:1; 811 uint64_t bwcnt:1; 812 uint64_t rdimm_ena:1; 813 #else 814 uint64_t rdimm_ena:1; 815 uint64_t bwcnt:1; 816 uint64_t ddr2t:1; 817 uint64_t pocas:1; 818 uint64_t fprch2:2; 819 uint64_t throttle_rd:1; 820 uint64_t throttle_wr:1; 821 uint64_t inorder_rd:1; 822 uint64_t inorder_wr:1; 823 uint64_t elev_prio_dis:1; 824 uint64_t nxm_write_en:1; 825 uint64_t max_write_batch:4; 826 uint64_t xor_bank:1; 827 uint64_t auto_dclkdis:1; 828 uint64_t int_zqcs_dis:1; 829 uint64_t ext_zqcs_dis:1; 830 uint64_t bprch:2; 831 uint64_t wodt_bprch:1; 832 uint64_t rodt_bprch:1; 833 uint64_t reserved_24_63:40; 834 #endif 835 } cn63xx; 836 struct cvmx_lmcx_control_cn63xx cn63xxp1; 837 struct cvmx_lmcx_control_cn66xx { 838 #ifdef __BIG_ENDIAN_BITFIELD 839 uint64_t scramble_ena:1; 840 uint64_t reserved_24_62:39; 841 uint64_t rodt_bprch:1; 842 uint64_t wodt_bprch:1; 843 uint64_t bprch:2; 844 uint64_t ext_zqcs_dis:1; 845 uint64_t int_zqcs_dis:1; 846 uint64_t auto_dclkdis:1; 847 uint64_t xor_bank:1; 848 uint64_t max_write_batch:4; 849 uint64_t nxm_write_en:1; 850 uint64_t elev_prio_dis:1; 851 uint64_t inorder_wr:1; 852 uint64_t inorder_rd:1; 853 uint64_t throttle_wr:1; 854 uint64_t throttle_rd:1; 855 uint64_t fprch2:2; 856 uint64_t pocas:1; 857 uint64_t ddr2t:1; 858 uint64_t bwcnt:1; 859 uint64_t rdimm_ena:1; 860 #else 861 uint64_t rdimm_ena:1; 862 uint64_t bwcnt:1; 863 uint64_t ddr2t:1; 864 uint64_t pocas:1; 865 uint64_t fprch2:2; 866 uint64_t throttle_rd:1; 867 uint64_t throttle_wr:1; 868 uint64_t inorder_rd:1; 869 uint64_t inorder_wr:1; 870 uint64_t elev_prio_dis:1; 871 uint64_t nxm_write_en:1; 872 uint64_t max_write_batch:4; 873 uint64_t xor_bank:1; 874 uint64_t auto_dclkdis:1; 875 uint64_t int_zqcs_dis:1; 876 uint64_t ext_zqcs_dis:1; 877 uint64_t bprch:2; 878 uint64_t wodt_bprch:1; 879 uint64_t rodt_bprch:1; 880 uint64_t reserved_24_62:39; 881 uint64_t scramble_ena:1; 882 #endif 883 } cn66xx; 884 struct cvmx_lmcx_control_cn68xx { 885 #ifdef __BIG_ENDIAN_BITFIELD 886 uint64_t reserved_63_63:1; 887 uint64_t thrcnt:12; 888 uint64_t persub:8; 889 uint64_t thrmax:4; 890 uint64_t crm_cnt:5; 891 uint64_t crm_thr:5; 892 uint64_t crm_max:5; 893 uint64_t rodt_bprch:1; 894 uint64_t wodt_bprch:1; 895 uint64_t bprch:2; 896 uint64_t ext_zqcs_dis:1; 897 uint64_t int_zqcs_dis:1; 898 uint64_t auto_dclkdis:1; 899 uint64_t xor_bank:1; 900 uint64_t max_write_batch:4; 901 uint64_t nxm_write_en:1; 902 uint64_t elev_prio_dis:1; 903 uint64_t inorder_wr:1; 904 uint64_t inorder_rd:1; 905 uint64_t throttle_wr:1; 906 uint64_t throttle_rd:1; 907 uint64_t fprch2:2; 908 uint64_t pocas:1; 909 uint64_t ddr2t:1; 910 uint64_t bwcnt:1; 911 uint64_t rdimm_ena:1; 912 #else 913 uint64_t rdimm_ena:1; 914 uint64_t bwcnt:1; 915 uint64_t ddr2t:1; 916 uint64_t pocas:1; 917 uint64_t fprch2:2; 918 uint64_t throttle_rd:1; 919 uint64_t throttle_wr:1; 920 uint64_t inorder_rd:1; 921 uint64_t inorder_wr:1; 922 uint64_t elev_prio_dis:1; 923 uint64_t nxm_write_en:1; 924 uint64_t max_write_batch:4; 925 uint64_t xor_bank:1; 926 uint64_t auto_dclkdis:1; 927 uint64_t int_zqcs_dis:1; 928 uint64_t ext_zqcs_dis:1; 929 uint64_t bprch:2; 930 uint64_t wodt_bprch:1; 931 uint64_t rodt_bprch:1; 932 uint64_t crm_max:5; 933 uint64_t crm_thr:5; 934 uint64_t crm_cnt:5; 935 uint64_t thrmax:4; 936 uint64_t persub:8; 937 uint64_t thrcnt:12; 938 uint64_t reserved_63_63:1; 939 #endif 940 } cn68xx; 941 struct cvmx_lmcx_control_cn68xx cn68xxp1; 942 struct cvmx_lmcx_control_cn66xx cnf71xx; 943 }; 944 945 union cvmx_lmcx_ctl { 946 uint64_t u64; 947 struct cvmx_lmcx_ctl_s { 948 #ifdef __BIG_ENDIAN_BITFIELD 949 uint64_t reserved_32_63:32; 950 uint64_t ddr__nctl:4; 951 uint64_t ddr__pctl:4; 952 uint64_t slow_scf:1; 953 uint64_t xor_bank:1; 954 uint64_t max_write_batch:4; 955 uint64_t pll_div2:1; 956 uint64_t pll_bypass:1; 957 uint64_t rdimm_ena:1; 958 uint64_t r2r_slot:1; 959 uint64_t inorder_mwf:1; 960 uint64_t inorder_mrf:1; 961 uint64_t reserved_10_11:2; 962 uint64_t fprch2:1; 963 uint64_t bprch:1; 964 uint64_t sil_lat:2; 965 uint64_t tskw:2; 966 uint64_t qs_dic:2; 967 uint64_t dic:2; 968 #else 969 uint64_t dic:2; 970 uint64_t qs_dic:2; 971 uint64_t tskw:2; 972 uint64_t sil_lat:2; 973 uint64_t bprch:1; 974 uint64_t fprch2:1; 975 uint64_t reserved_10_11:2; 976 uint64_t inorder_mrf:1; 977 uint64_t inorder_mwf:1; 978 uint64_t r2r_slot:1; 979 uint64_t rdimm_ena:1; 980 uint64_t pll_bypass:1; 981 uint64_t pll_div2:1; 982 uint64_t max_write_batch:4; 983 uint64_t xor_bank:1; 984 uint64_t slow_scf:1; 985 uint64_t ddr__pctl:4; 986 uint64_t ddr__nctl:4; 987 uint64_t reserved_32_63:32; 988 #endif 989 } s; 990 struct cvmx_lmcx_ctl_cn30xx { 991 #ifdef __BIG_ENDIAN_BITFIELD 992 uint64_t reserved_32_63:32; 993 uint64_t ddr__nctl:4; 994 uint64_t ddr__pctl:4; 995 uint64_t slow_scf:1; 996 uint64_t xor_bank:1; 997 uint64_t max_write_batch:4; 998 uint64_t pll_div2:1; 999 uint64_t pll_bypass:1; 1000 uint64_t rdimm_ena:1; 1001 uint64_t r2r_slot:1; 1002 uint64_t inorder_mwf:1; 1003 uint64_t inorder_mrf:1; 1004 uint64_t dreset:1; 1005 uint64_t mode32b:1; 1006 uint64_t fprch2:1; 1007 uint64_t bprch:1; 1008 uint64_t sil_lat:2; 1009 uint64_t tskw:2; 1010 uint64_t qs_dic:2; 1011 uint64_t dic:2; 1012 #else 1013 uint64_t dic:2; 1014 uint64_t qs_dic:2; 1015 uint64_t tskw:2; 1016 uint64_t sil_lat:2; 1017 uint64_t bprch:1; 1018 uint64_t fprch2:1; 1019 uint64_t mode32b:1; 1020 uint64_t dreset:1; 1021 uint64_t inorder_mrf:1; 1022 uint64_t inorder_mwf:1; 1023 uint64_t r2r_slot:1; 1024 uint64_t rdimm_ena:1; 1025 uint64_t pll_bypass:1; 1026 uint64_t pll_div2:1; 1027 uint64_t max_write_batch:4; 1028 uint64_t xor_bank:1; 1029 uint64_t slow_scf:1; 1030 uint64_t ddr__pctl:4; 1031 uint64_t ddr__nctl:4; 1032 uint64_t reserved_32_63:32; 1033 #endif 1034 } cn30xx; 1035 struct cvmx_lmcx_ctl_cn30xx cn31xx; 1036 struct cvmx_lmcx_ctl_cn38xx { 1037 #ifdef __BIG_ENDIAN_BITFIELD 1038 uint64_t reserved_32_63:32; 1039 uint64_t ddr__nctl:4; 1040 uint64_t ddr__pctl:4; 1041 uint64_t slow_scf:1; 1042 uint64_t xor_bank:1; 1043 uint64_t max_write_batch:4; 1044 uint64_t reserved_16_17:2; 1045 uint64_t rdimm_ena:1; 1046 uint64_t r2r_slot:1; 1047 uint64_t inorder_mwf:1; 1048 uint64_t inorder_mrf:1; 1049 uint64_t set_zero:1; 1050 uint64_t mode128b:1; 1051 uint64_t fprch2:1; 1052 uint64_t bprch:1; 1053 uint64_t sil_lat:2; 1054 uint64_t tskw:2; 1055 uint64_t qs_dic:2; 1056 uint64_t dic:2; 1057 #else 1058 uint64_t dic:2; 1059 uint64_t qs_dic:2; 1060 uint64_t tskw:2; 1061 uint64_t sil_lat:2; 1062 uint64_t bprch:1; 1063 uint64_t fprch2:1; 1064 uint64_t mode128b:1; 1065 uint64_t set_zero:1; 1066 uint64_t inorder_mrf:1; 1067 uint64_t inorder_mwf:1; 1068 uint64_t r2r_slot:1; 1069 uint64_t rdimm_ena:1; 1070 uint64_t reserved_16_17:2; 1071 uint64_t max_write_batch:4; 1072 uint64_t xor_bank:1; 1073 uint64_t slow_scf:1; 1074 uint64_t ddr__pctl:4; 1075 uint64_t ddr__nctl:4; 1076 uint64_t reserved_32_63:32; 1077 #endif 1078 } cn38xx; 1079 struct cvmx_lmcx_ctl_cn38xx cn38xxp2; 1080 struct cvmx_lmcx_ctl_cn50xx { 1081 #ifdef __BIG_ENDIAN_BITFIELD 1082 uint64_t reserved_32_63:32; 1083 uint64_t ddr__nctl:4; 1084 uint64_t ddr__pctl:4; 1085 uint64_t slow_scf:1; 1086 uint64_t xor_bank:1; 1087 uint64_t max_write_batch:4; 1088 uint64_t reserved_17_17:1; 1089 uint64_t pll_bypass:1; 1090 uint64_t rdimm_ena:1; 1091 uint64_t r2r_slot:1; 1092 uint64_t inorder_mwf:1; 1093 uint64_t inorder_mrf:1; 1094 uint64_t dreset:1; 1095 uint64_t mode32b:1; 1096 uint64_t fprch2:1; 1097 uint64_t bprch:1; 1098 uint64_t sil_lat:2; 1099 uint64_t tskw:2; 1100 uint64_t qs_dic:2; 1101 uint64_t dic:2; 1102 #else 1103 uint64_t dic:2; 1104 uint64_t qs_dic:2; 1105 uint64_t tskw:2; 1106 uint64_t sil_lat:2; 1107 uint64_t bprch:1; 1108 uint64_t fprch2:1; 1109 uint64_t mode32b:1; 1110 uint64_t dreset:1; 1111 uint64_t inorder_mrf:1; 1112 uint64_t inorder_mwf:1; 1113 uint64_t r2r_slot:1; 1114 uint64_t rdimm_ena:1; 1115 uint64_t pll_bypass:1; 1116 uint64_t reserved_17_17:1; 1117 uint64_t max_write_batch:4; 1118 uint64_t xor_bank:1; 1119 uint64_t slow_scf:1; 1120 uint64_t ddr__pctl:4; 1121 uint64_t ddr__nctl:4; 1122 uint64_t reserved_32_63:32; 1123 #endif 1124 } cn50xx; 1125 struct cvmx_lmcx_ctl_cn52xx { 1126 #ifdef __BIG_ENDIAN_BITFIELD 1127 uint64_t reserved_32_63:32; 1128 uint64_t ddr__nctl:4; 1129 uint64_t ddr__pctl:4; 1130 uint64_t slow_scf:1; 1131 uint64_t xor_bank:1; 1132 uint64_t max_write_batch:4; 1133 uint64_t reserved_16_17:2; 1134 uint64_t rdimm_ena:1; 1135 uint64_t r2r_slot:1; 1136 uint64_t inorder_mwf:1; 1137 uint64_t inorder_mrf:1; 1138 uint64_t dreset:1; 1139 uint64_t mode32b:1; 1140 uint64_t fprch2:1; 1141 uint64_t bprch:1; 1142 uint64_t sil_lat:2; 1143 uint64_t tskw:2; 1144 uint64_t qs_dic:2; 1145 uint64_t dic:2; 1146 #else 1147 uint64_t dic:2; 1148 uint64_t qs_dic:2; 1149 uint64_t tskw:2; 1150 uint64_t sil_lat:2; 1151 uint64_t bprch:1; 1152 uint64_t fprch2:1; 1153 uint64_t mode32b:1; 1154 uint64_t dreset:1; 1155 uint64_t inorder_mrf:1; 1156 uint64_t inorder_mwf:1; 1157 uint64_t r2r_slot:1; 1158 uint64_t rdimm_ena:1; 1159 uint64_t reserved_16_17:2; 1160 uint64_t max_write_batch:4; 1161 uint64_t xor_bank:1; 1162 uint64_t slow_scf:1; 1163 uint64_t ddr__pctl:4; 1164 uint64_t ddr__nctl:4; 1165 uint64_t reserved_32_63:32; 1166 #endif 1167 } cn52xx; 1168 struct cvmx_lmcx_ctl_cn52xx cn52xxp1; 1169 struct cvmx_lmcx_ctl_cn52xx cn56xx; 1170 struct cvmx_lmcx_ctl_cn52xx cn56xxp1; 1171 struct cvmx_lmcx_ctl_cn58xx { 1172 #ifdef __BIG_ENDIAN_BITFIELD 1173 uint64_t reserved_32_63:32; 1174 uint64_t ddr__nctl:4; 1175 uint64_t ddr__pctl:4; 1176 uint64_t slow_scf:1; 1177 uint64_t xor_bank:1; 1178 uint64_t max_write_batch:4; 1179 uint64_t reserved_16_17:2; 1180 uint64_t rdimm_ena:1; 1181 uint64_t r2r_slot:1; 1182 uint64_t inorder_mwf:1; 1183 uint64_t inorder_mrf:1; 1184 uint64_t dreset:1; 1185 uint64_t mode128b:1; 1186 uint64_t fprch2:1; 1187 uint64_t bprch:1; 1188 uint64_t sil_lat:2; 1189 uint64_t tskw:2; 1190 uint64_t qs_dic:2; 1191 uint64_t dic:2; 1192 #else 1193 uint64_t dic:2; 1194 uint64_t qs_dic:2; 1195 uint64_t tskw:2; 1196 uint64_t sil_lat:2; 1197 uint64_t bprch:1; 1198 uint64_t fprch2:1; 1199 uint64_t mode128b:1; 1200 uint64_t dreset:1; 1201 uint64_t inorder_mrf:1; 1202 uint64_t inorder_mwf:1; 1203 uint64_t r2r_slot:1; 1204 uint64_t rdimm_ena:1; 1205 uint64_t reserved_16_17:2; 1206 uint64_t max_write_batch:4; 1207 uint64_t xor_bank:1; 1208 uint64_t slow_scf:1; 1209 uint64_t ddr__pctl:4; 1210 uint64_t ddr__nctl:4; 1211 uint64_t reserved_32_63:32; 1212 #endif 1213 } cn58xx; 1214 struct cvmx_lmcx_ctl_cn58xx cn58xxp1; 1215 }; 1216 1217 union cvmx_lmcx_ctl1 { 1218 uint64_t u64; 1219 struct cvmx_lmcx_ctl1_s { 1220 #ifdef __BIG_ENDIAN_BITFIELD 1221 uint64_t reserved_21_63:43; 1222 uint64_t ecc_adr:1; 1223 uint64_t forcewrite:4; 1224 uint64_t idlepower:3; 1225 uint64_t sequence:3; 1226 uint64_t sil_mode:1; 1227 uint64_t dcc_enable:1; 1228 uint64_t reserved_2_7:6; 1229 uint64_t data_layout:2; 1230 #else 1231 uint64_t data_layout:2; 1232 uint64_t reserved_2_7:6; 1233 uint64_t dcc_enable:1; 1234 uint64_t sil_mode:1; 1235 uint64_t sequence:3; 1236 uint64_t idlepower:3; 1237 uint64_t forcewrite:4; 1238 uint64_t ecc_adr:1; 1239 uint64_t reserved_21_63:43; 1240 #endif 1241 } s; 1242 struct cvmx_lmcx_ctl1_cn30xx { 1243 #ifdef __BIG_ENDIAN_BITFIELD 1244 uint64_t reserved_2_63:62; 1245 uint64_t data_layout:2; 1246 #else 1247 uint64_t data_layout:2; 1248 uint64_t reserved_2_63:62; 1249 #endif 1250 } cn30xx; 1251 struct cvmx_lmcx_ctl1_cn50xx { 1252 #ifdef __BIG_ENDIAN_BITFIELD 1253 uint64_t reserved_10_63:54; 1254 uint64_t sil_mode:1; 1255 uint64_t dcc_enable:1; 1256 uint64_t reserved_2_7:6; 1257 uint64_t data_layout:2; 1258 #else 1259 uint64_t data_layout:2; 1260 uint64_t reserved_2_7:6; 1261 uint64_t dcc_enable:1; 1262 uint64_t sil_mode:1; 1263 uint64_t reserved_10_63:54; 1264 #endif 1265 } cn50xx; 1266 struct cvmx_lmcx_ctl1_cn52xx { 1267 #ifdef __BIG_ENDIAN_BITFIELD 1268 uint64_t reserved_21_63:43; 1269 uint64_t ecc_adr:1; 1270 uint64_t forcewrite:4; 1271 uint64_t idlepower:3; 1272 uint64_t sequence:3; 1273 uint64_t sil_mode:1; 1274 uint64_t dcc_enable:1; 1275 uint64_t reserved_0_7:8; 1276 #else 1277 uint64_t reserved_0_7:8; 1278 uint64_t dcc_enable:1; 1279 uint64_t sil_mode:1; 1280 uint64_t sequence:3; 1281 uint64_t idlepower:3; 1282 uint64_t forcewrite:4; 1283 uint64_t ecc_adr:1; 1284 uint64_t reserved_21_63:43; 1285 #endif 1286 } cn52xx; 1287 struct cvmx_lmcx_ctl1_cn52xx cn52xxp1; 1288 struct cvmx_lmcx_ctl1_cn52xx cn56xx; 1289 struct cvmx_lmcx_ctl1_cn52xx cn56xxp1; 1290 struct cvmx_lmcx_ctl1_cn58xx { 1291 #ifdef __BIG_ENDIAN_BITFIELD 1292 uint64_t reserved_10_63:54; 1293 uint64_t sil_mode:1; 1294 uint64_t dcc_enable:1; 1295 uint64_t reserved_0_7:8; 1296 #else 1297 uint64_t reserved_0_7:8; 1298 uint64_t dcc_enable:1; 1299 uint64_t sil_mode:1; 1300 uint64_t reserved_10_63:54; 1301 #endif 1302 } cn58xx; 1303 struct cvmx_lmcx_ctl1_cn58xx cn58xxp1; 1304 }; 1305 1306 union cvmx_lmcx_dclk_cnt { 1307 uint64_t u64; 1308 struct cvmx_lmcx_dclk_cnt_s { 1309 #ifdef __BIG_ENDIAN_BITFIELD 1310 uint64_t dclkcnt:64; 1311 #else 1312 uint64_t dclkcnt:64; 1313 #endif 1314 } s; 1315 struct cvmx_lmcx_dclk_cnt_s cn61xx; 1316 struct cvmx_lmcx_dclk_cnt_s cn63xx; 1317 struct cvmx_lmcx_dclk_cnt_s cn63xxp1; 1318 struct cvmx_lmcx_dclk_cnt_s cn66xx; 1319 struct cvmx_lmcx_dclk_cnt_s cn68xx; 1320 struct cvmx_lmcx_dclk_cnt_s cn68xxp1; 1321 struct cvmx_lmcx_dclk_cnt_s cnf71xx; 1322 }; 1323 1324 union cvmx_lmcx_dclk_cnt_hi { 1325 uint64_t u64; 1326 struct cvmx_lmcx_dclk_cnt_hi_s { 1327 #ifdef __BIG_ENDIAN_BITFIELD 1328 uint64_t reserved_32_63:32; 1329 uint64_t dclkcnt_hi:32; 1330 #else 1331 uint64_t dclkcnt_hi:32; 1332 uint64_t reserved_32_63:32; 1333 #endif 1334 } s; 1335 struct cvmx_lmcx_dclk_cnt_hi_s cn30xx; 1336 struct cvmx_lmcx_dclk_cnt_hi_s cn31xx; 1337 struct cvmx_lmcx_dclk_cnt_hi_s cn38xx; 1338 struct cvmx_lmcx_dclk_cnt_hi_s cn38xxp2; 1339 struct cvmx_lmcx_dclk_cnt_hi_s cn50xx; 1340 struct cvmx_lmcx_dclk_cnt_hi_s cn52xx; 1341 struct cvmx_lmcx_dclk_cnt_hi_s cn52xxp1; 1342 struct cvmx_lmcx_dclk_cnt_hi_s cn56xx; 1343 struct cvmx_lmcx_dclk_cnt_hi_s cn56xxp1; 1344 struct cvmx_lmcx_dclk_cnt_hi_s cn58xx; 1345 struct cvmx_lmcx_dclk_cnt_hi_s cn58xxp1; 1346 }; 1347 1348 union cvmx_lmcx_dclk_cnt_lo { 1349 uint64_t u64; 1350 struct cvmx_lmcx_dclk_cnt_lo_s { 1351 #ifdef __BIG_ENDIAN_BITFIELD 1352 uint64_t reserved_32_63:32; 1353 uint64_t dclkcnt_lo:32; 1354 #else 1355 uint64_t dclkcnt_lo:32; 1356 uint64_t reserved_32_63:32; 1357 #endif 1358 } s; 1359 struct cvmx_lmcx_dclk_cnt_lo_s cn30xx; 1360 struct cvmx_lmcx_dclk_cnt_lo_s cn31xx; 1361 struct cvmx_lmcx_dclk_cnt_lo_s cn38xx; 1362 struct cvmx_lmcx_dclk_cnt_lo_s cn38xxp2; 1363 struct cvmx_lmcx_dclk_cnt_lo_s cn50xx; 1364 struct cvmx_lmcx_dclk_cnt_lo_s cn52xx; 1365 struct cvmx_lmcx_dclk_cnt_lo_s cn52xxp1; 1366 struct cvmx_lmcx_dclk_cnt_lo_s cn56xx; 1367 struct cvmx_lmcx_dclk_cnt_lo_s cn56xxp1; 1368 struct cvmx_lmcx_dclk_cnt_lo_s cn58xx; 1369 struct cvmx_lmcx_dclk_cnt_lo_s cn58xxp1; 1370 }; 1371 1372 union cvmx_lmcx_dclk_ctl { 1373 uint64_t u64; 1374 struct cvmx_lmcx_dclk_ctl_s { 1375 #ifdef __BIG_ENDIAN_BITFIELD 1376 uint64_t reserved_8_63:56; 1377 uint64_t off90_ena:1; 1378 uint64_t dclk90_byp:1; 1379 uint64_t dclk90_ld:1; 1380 uint64_t dclk90_vlu:5; 1381 #else 1382 uint64_t dclk90_vlu:5; 1383 uint64_t dclk90_ld:1; 1384 uint64_t dclk90_byp:1; 1385 uint64_t off90_ena:1; 1386 uint64_t reserved_8_63:56; 1387 #endif 1388 } s; 1389 struct cvmx_lmcx_dclk_ctl_s cn56xx; 1390 struct cvmx_lmcx_dclk_ctl_s cn56xxp1; 1391 }; 1392 1393 union cvmx_lmcx_ddr2_ctl { 1394 uint64_t u64; 1395 struct cvmx_lmcx_ddr2_ctl_s { 1396 #ifdef __BIG_ENDIAN_BITFIELD 1397 uint64_t reserved_32_63:32; 1398 uint64_t bank8:1; 1399 uint64_t burst8:1; 1400 uint64_t addlat:3; 1401 uint64_t pocas:1; 1402 uint64_t bwcnt:1; 1403 uint64_t twr:3; 1404 uint64_t silo_hc:1; 1405 uint64_t ddr_eof:4; 1406 uint64_t tfaw:5; 1407 uint64_t crip_mode:1; 1408 uint64_t ddr2t:1; 1409 uint64_t odt_ena:1; 1410 uint64_t qdll_ena:1; 1411 uint64_t dll90_vlu:5; 1412 uint64_t dll90_byp:1; 1413 uint64_t rdqs:1; 1414 uint64_t ddr2:1; 1415 #else 1416 uint64_t ddr2:1; 1417 uint64_t rdqs:1; 1418 uint64_t dll90_byp:1; 1419 uint64_t dll90_vlu:5; 1420 uint64_t qdll_ena:1; 1421 uint64_t odt_ena:1; 1422 uint64_t ddr2t:1; 1423 uint64_t crip_mode:1; 1424 uint64_t tfaw:5; 1425 uint64_t ddr_eof:4; 1426 uint64_t silo_hc:1; 1427 uint64_t twr:3; 1428 uint64_t bwcnt:1; 1429 uint64_t pocas:1; 1430 uint64_t addlat:3; 1431 uint64_t burst8:1; 1432 uint64_t bank8:1; 1433 uint64_t reserved_32_63:32; 1434 #endif 1435 } s; 1436 struct cvmx_lmcx_ddr2_ctl_cn30xx { 1437 #ifdef __BIG_ENDIAN_BITFIELD 1438 uint64_t reserved_32_63:32; 1439 uint64_t bank8:1; 1440 uint64_t burst8:1; 1441 uint64_t addlat:3; 1442 uint64_t pocas:1; 1443 uint64_t bwcnt:1; 1444 uint64_t twr:3; 1445 uint64_t silo_hc:1; 1446 uint64_t ddr_eof:4; 1447 uint64_t tfaw:5; 1448 uint64_t crip_mode:1; 1449 uint64_t ddr2t:1; 1450 uint64_t odt_ena:1; 1451 uint64_t qdll_ena:1; 1452 uint64_t dll90_vlu:5; 1453 uint64_t dll90_byp:1; 1454 uint64_t reserved_1_1:1; 1455 uint64_t ddr2:1; 1456 #else 1457 uint64_t ddr2:1; 1458 uint64_t reserved_1_1:1; 1459 uint64_t dll90_byp:1; 1460 uint64_t dll90_vlu:5; 1461 uint64_t qdll_ena:1; 1462 uint64_t odt_ena:1; 1463 uint64_t ddr2t:1; 1464 uint64_t crip_mode:1; 1465 uint64_t tfaw:5; 1466 uint64_t ddr_eof:4; 1467 uint64_t silo_hc:1; 1468 uint64_t twr:3; 1469 uint64_t bwcnt:1; 1470 uint64_t pocas:1; 1471 uint64_t addlat:3; 1472 uint64_t burst8:1; 1473 uint64_t bank8:1; 1474 uint64_t reserved_32_63:32; 1475 #endif 1476 } cn30xx; 1477 struct cvmx_lmcx_ddr2_ctl_cn30xx cn31xx; 1478 struct cvmx_lmcx_ddr2_ctl_s cn38xx; 1479 struct cvmx_lmcx_ddr2_ctl_s cn38xxp2; 1480 struct cvmx_lmcx_ddr2_ctl_s cn50xx; 1481 struct cvmx_lmcx_ddr2_ctl_s cn52xx; 1482 struct cvmx_lmcx_ddr2_ctl_s cn52xxp1; 1483 struct cvmx_lmcx_ddr2_ctl_s cn56xx; 1484 struct cvmx_lmcx_ddr2_ctl_s cn56xxp1; 1485 struct cvmx_lmcx_ddr2_ctl_s cn58xx; 1486 struct cvmx_lmcx_ddr2_ctl_s cn58xxp1; 1487 }; 1488 1489 union cvmx_lmcx_ddr_pll_ctl { 1490 uint64_t u64; 1491 struct cvmx_lmcx_ddr_pll_ctl_s { 1492 #ifdef __BIG_ENDIAN_BITFIELD 1493 uint64_t reserved_27_63:37; 1494 uint64_t jtg_test_mode:1; 1495 uint64_t dfm_div_reset:1; 1496 uint64_t dfm_ps_en:3; 1497 uint64_t ddr_div_reset:1; 1498 uint64_t ddr_ps_en:3; 1499 uint64_t diffamp:4; 1500 uint64_t cps:3; 1501 uint64_t cpb:3; 1502 uint64_t reset_n:1; 1503 uint64_t clkf:7; 1504 #else 1505 uint64_t clkf:7; 1506 uint64_t reset_n:1; 1507 uint64_t cpb:3; 1508 uint64_t cps:3; 1509 uint64_t diffamp:4; 1510 uint64_t ddr_ps_en:3; 1511 uint64_t ddr_div_reset:1; 1512 uint64_t dfm_ps_en:3; 1513 uint64_t dfm_div_reset:1; 1514 uint64_t jtg_test_mode:1; 1515 uint64_t reserved_27_63:37; 1516 #endif 1517 } s; 1518 struct cvmx_lmcx_ddr_pll_ctl_s cn61xx; 1519 struct cvmx_lmcx_ddr_pll_ctl_s cn63xx; 1520 struct cvmx_lmcx_ddr_pll_ctl_s cn63xxp1; 1521 struct cvmx_lmcx_ddr_pll_ctl_s cn66xx; 1522 struct cvmx_lmcx_ddr_pll_ctl_s cn68xx; 1523 struct cvmx_lmcx_ddr_pll_ctl_s cn68xxp1; 1524 struct cvmx_lmcx_ddr_pll_ctl_s cnf71xx; 1525 }; 1526 1527 union cvmx_lmcx_delay_cfg { 1528 uint64_t u64; 1529 struct cvmx_lmcx_delay_cfg_s { 1530 #ifdef __BIG_ENDIAN_BITFIELD 1531 uint64_t reserved_15_63:49; 1532 uint64_t dq:5; 1533 uint64_t cmd:5; 1534 uint64_t clk:5; 1535 #else 1536 uint64_t clk:5; 1537 uint64_t cmd:5; 1538 uint64_t dq:5; 1539 uint64_t reserved_15_63:49; 1540 #endif 1541 } s; 1542 struct cvmx_lmcx_delay_cfg_s cn30xx; 1543 struct cvmx_lmcx_delay_cfg_cn38xx { 1544 #ifdef __BIG_ENDIAN_BITFIELD 1545 uint64_t reserved_14_63:50; 1546 uint64_t dq:4; 1547 uint64_t reserved_9_9:1; 1548 uint64_t cmd:4; 1549 uint64_t reserved_4_4:1; 1550 uint64_t clk:4; 1551 #else 1552 uint64_t clk:4; 1553 uint64_t reserved_4_4:1; 1554 uint64_t cmd:4; 1555 uint64_t reserved_9_9:1; 1556 uint64_t dq:4; 1557 uint64_t reserved_14_63:50; 1558 #endif 1559 } cn38xx; 1560 struct cvmx_lmcx_delay_cfg_cn38xx cn50xx; 1561 struct cvmx_lmcx_delay_cfg_cn38xx cn52xx; 1562 struct cvmx_lmcx_delay_cfg_cn38xx cn52xxp1; 1563 struct cvmx_lmcx_delay_cfg_cn38xx cn56xx; 1564 struct cvmx_lmcx_delay_cfg_cn38xx cn56xxp1; 1565 struct cvmx_lmcx_delay_cfg_cn38xx cn58xx; 1566 struct cvmx_lmcx_delay_cfg_cn38xx cn58xxp1; 1567 }; 1568 1569 union cvmx_lmcx_dimmx_params { 1570 uint64_t u64; 1571 struct cvmx_lmcx_dimmx_params_s { 1572 #ifdef __BIG_ENDIAN_BITFIELD 1573 uint64_t rc15:4; 1574 uint64_t rc14:4; 1575 uint64_t rc13:4; 1576 uint64_t rc12:4; 1577 uint64_t rc11:4; 1578 uint64_t rc10:4; 1579 uint64_t rc9:4; 1580 uint64_t rc8:4; 1581 uint64_t rc7:4; 1582 uint64_t rc6:4; 1583 uint64_t rc5:4; 1584 uint64_t rc4:4; 1585 uint64_t rc3:4; 1586 uint64_t rc2:4; 1587 uint64_t rc1:4; 1588 uint64_t rc0:4; 1589 #else 1590 uint64_t rc0:4; 1591 uint64_t rc1:4; 1592 uint64_t rc2:4; 1593 uint64_t rc3:4; 1594 uint64_t rc4:4; 1595 uint64_t rc5:4; 1596 uint64_t rc6:4; 1597 uint64_t rc7:4; 1598 uint64_t rc8:4; 1599 uint64_t rc9:4; 1600 uint64_t rc10:4; 1601 uint64_t rc11:4; 1602 uint64_t rc12:4; 1603 uint64_t rc13:4; 1604 uint64_t rc14:4; 1605 uint64_t rc15:4; 1606 #endif 1607 } s; 1608 struct cvmx_lmcx_dimmx_params_s cn61xx; 1609 struct cvmx_lmcx_dimmx_params_s cn63xx; 1610 struct cvmx_lmcx_dimmx_params_s cn63xxp1; 1611 struct cvmx_lmcx_dimmx_params_s cn66xx; 1612 struct cvmx_lmcx_dimmx_params_s cn68xx; 1613 struct cvmx_lmcx_dimmx_params_s cn68xxp1; 1614 struct cvmx_lmcx_dimmx_params_s cnf71xx; 1615 }; 1616 1617 union cvmx_lmcx_dimm_ctl { 1618 uint64_t u64; 1619 struct cvmx_lmcx_dimm_ctl_s { 1620 #ifdef __BIG_ENDIAN_BITFIELD 1621 uint64_t reserved_46_63:18; 1622 uint64_t parity:1; 1623 uint64_t tcws:13; 1624 uint64_t dimm1_wmask:16; 1625 uint64_t dimm0_wmask:16; 1626 #else 1627 uint64_t dimm0_wmask:16; 1628 uint64_t dimm1_wmask:16; 1629 uint64_t tcws:13; 1630 uint64_t parity:1; 1631 uint64_t reserved_46_63:18; 1632 #endif 1633 } s; 1634 struct cvmx_lmcx_dimm_ctl_s cn61xx; 1635 struct cvmx_lmcx_dimm_ctl_s cn63xx; 1636 struct cvmx_lmcx_dimm_ctl_s cn63xxp1; 1637 struct cvmx_lmcx_dimm_ctl_s cn66xx; 1638 struct cvmx_lmcx_dimm_ctl_s cn68xx; 1639 struct cvmx_lmcx_dimm_ctl_s cn68xxp1; 1640 struct cvmx_lmcx_dimm_ctl_s cnf71xx; 1641 }; 1642 1643 union cvmx_lmcx_dll_ctl { 1644 uint64_t u64; 1645 struct cvmx_lmcx_dll_ctl_s { 1646 #ifdef __BIG_ENDIAN_BITFIELD 1647 uint64_t reserved_8_63:56; 1648 uint64_t dreset:1; 1649 uint64_t dll90_byp:1; 1650 uint64_t dll90_ena:1; 1651 uint64_t dll90_vlu:5; 1652 #else 1653 uint64_t dll90_vlu:5; 1654 uint64_t dll90_ena:1; 1655 uint64_t dll90_byp:1; 1656 uint64_t dreset:1; 1657 uint64_t reserved_8_63:56; 1658 #endif 1659 } s; 1660 struct cvmx_lmcx_dll_ctl_s cn52xx; 1661 struct cvmx_lmcx_dll_ctl_s cn52xxp1; 1662 struct cvmx_lmcx_dll_ctl_s cn56xx; 1663 struct cvmx_lmcx_dll_ctl_s cn56xxp1; 1664 }; 1665 1666 union cvmx_lmcx_dll_ctl2 { 1667 uint64_t u64; 1668 struct cvmx_lmcx_dll_ctl2_s { 1669 #ifdef __BIG_ENDIAN_BITFIELD 1670 uint64_t reserved_16_63:48; 1671 uint64_t intf_en:1; 1672 uint64_t dll_bringup:1; 1673 uint64_t dreset:1; 1674 uint64_t quad_dll_ena:1; 1675 uint64_t byp_sel:4; 1676 uint64_t byp_setting:8; 1677 #else 1678 uint64_t byp_setting:8; 1679 uint64_t byp_sel:4; 1680 uint64_t quad_dll_ena:1; 1681 uint64_t dreset:1; 1682 uint64_t dll_bringup:1; 1683 uint64_t intf_en:1; 1684 uint64_t reserved_16_63:48; 1685 #endif 1686 } s; 1687 struct cvmx_lmcx_dll_ctl2_s cn61xx; 1688 struct cvmx_lmcx_dll_ctl2_cn63xx { 1689 #ifdef __BIG_ENDIAN_BITFIELD 1690 uint64_t reserved_15_63:49; 1691 uint64_t dll_bringup:1; 1692 uint64_t dreset:1; 1693 uint64_t quad_dll_ena:1; 1694 uint64_t byp_sel:4; 1695 uint64_t byp_setting:8; 1696 #else 1697 uint64_t byp_setting:8; 1698 uint64_t byp_sel:4; 1699 uint64_t quad_dll_ena:1; 1700 uint64_t dreset:1; 1701 uint64_t dll_bringup:1; 1702 uint64_t reserved_15_63:49; 1703 #endif 1704 } cn63xx; 1705 struct cvmx_lmcx_dll_ctl2_cn63xx cn63xxp1; 1706 struct cvmx_lmcx_dll_ctl2_cn63xx cn66xx; 1707 struct cvmx_lmcx_dll_ctl2_s cn68xx; 1708 struct cvmx_lmcx_dll_ctl2_s cn68xxp1; 1709 struct cvmx_lmcx_dll_ctl2_s cnf71xx; 1710 }; 1711 1712 union cvmx_lmcx_dll_ctl3 { 1713 uint64_t u64; 1714 struct cvmx_lmcx_dll_ctl3_s { 1715 #ifdef __BIG_ENDIAN_BITFIELD 1716 uint64_t reserved_41_63:23; 1717 uint64_t dclk90_fwd:1; 1718 uint64_t ddr_90_dly_byp:1; 1719 uint64_t dclk90_recal_dis:1; 1720 uint64_t dclk90_byp_sel:1; 1721 uint64_t dclk90_byp_setting:8; 1722 uint64_t dll_fast:1; 1723 uint64_t dll90_setting:8; 1724 uint64_t fine_tune_mode:1; 1725 uint64_t dll_mode:1; 1726 uint64_t dll90_byte_sel:4; 1727 uint64_t offset_ena:1; 1728 uint64_t load_offset:1; 1729 uint64_t mode_sel:2; 1730 uint64_t byte_sel:4; 1731 uint64_t offset:6; 1732 #else 1733 uint64_t offset:6; 1734 uint64_t byte_sel:4; 1735 uint64_t mode_sel:2; 1736 uint64_t load_offset:1; 1737 uint64_t offset_ena:1; 1738 uint64_t dll90_byte_sel:4; 1739 uint64_t dll_mode:1; 1740 uint64_t fine_tune_mode:1; 1741 uint64_t dll90_setting:8; 1742 uint64_t dll_fast:1; 1743 uint64_t dclk90_byp_setting:8; 1744 uint64_t dclk90_byp_sel:1; 1745 uint64_t dclk90_recal_dis:1; 1746 uint64_t ddr_90_dly_byp:1; 1747 uint64_t dclk90_fwd:1; 1748 uint64_t reserved_41_63:23; 1749 #endif 1750 } s; 1751 struct cvmx_lmcx_dll_ctl3_s cn61xx; 1752 struct cvmx_lmcx_dll_ctl3_cn63xx { 1753 #ifdef __BIG_ENDIAN_BITFIELD 1754 uint64_t reserved_29_63:35; 1755 uint64_t dll_fast:1; 1756 uint64_t dll90_setting:8; 1757 uint64_t fine_tune_mode:1; 1758 uint64_t dll_mode:1; 1759 uint64_t dll90_byte_sel:4; 1760 uint64_t offset_ena:1; 1761 uint64_t load_offset:1; 1762 uint64_t mode_sel:2; 1763 uint64_t byte_sel:4; 1764 uint64_t offset:6; 1765 #else 1766 uint64_t offset:6; 1767 uint64_t byte_sel:4; 1768 uint64_t mode_sel:2; 1769 uint64_t load_offset:1; 1770 uint64_t offset_ena:1; 1771 uint64_t dll90_byte_sel:4; 1772 uint64_t dll_mode:1; 1773 uint64_t fine_tune_mode:1; 1774 uint64_t dll90_setting:8; 1775 uint64_t dll_fast:1; 1776 uint64_t reserved_29_63:35; 1777 #endif 1778 } cn63xx; 1779 struct cvmx_lmcx_dll_ctl3_cn63xx cn63xxp1; 1780 struct cvmx_lmcx_dll_ctl3_cn63xx cn66xx; 1781 struct cvmx_lmcx_dll_ctl3_s cn68xx; 1782 struct cvmx_lmcx_dll_ctl3_s cn68xxp1; 1783 struct cvmx_lmcx_dll_ctl3_s cnf71xx; 1784 }; 1785 1786 union cvmx_lmcx_dual_memcfg { 1787 uint64_t u64; 1788 struct cvmx_lmcx_dual_memcfg_s { 1789 #ifdef __BIG_ENDIAN_BITFIELD 1790 uint64_t reserved_20_63:44; 1791 uint64_t bank8:1; 1792 uint64_t row_lsb:3; 1793 uint64_t reserved_8_15:8; 1794 uint64_t cs_mask:8; 1795 #else 1796 uint64_t cs_mask:8; 1797 uint64_t reserved_8_15:8; 1798 uint64_t row_lsb:3; 1799 uint64_t bank8:1; 1800 uint64_t reserved_20_63:44; 1801 #endif 1802 } s; 1803 struct cvmx_lmcx_dual_memcfg_s cn50xx; 1804 struct cvmx_lmcx_dual_memcfg_s cn52xx; 1805 struct cvmx_lmcx_dual_memcfg_s cn52xxp1; 1806 struct cvmx_lmcx_dual_memcfg_s cn56xx; 1807 struct cvmx_lmcx_dual_memcfg_s cn56xxp1; 1808 struct cvmx_lmcx_dual_memcfg_s cn58xx; 1809 struct cvmx_lmcx_dual_memcfg_s cn58xxp1; 1810 struct cvmx_lmcx_dual_memcfg_cn61xx { 1811 #ifdef __BIG_ENDIAN_BITFIELD 1812 uint64_t reserved_19_63:45; 1813 uint64_t row_lsb:3; 1814 uint64_t reserved_8_15:8; 1815 uint64_t cs_mask:8; 1816 #else 1817 uint64_t cs_mask:8; 1818 uint64_t reserved_8_15:8; 1819 uint64_t row_lsb:3; 1820 uint64_t reserved_19_63:45; 1821 #endif 1822 } cn61xx; 1823 struct cvmx_lmcx_dual_memcfg_cn61xx cn63xx; 1824 struct cvmx_lmcx_dual_memcfg_cn61xx cn63xxp1; 1825 struct cvmx_lmcx_dual_memcfg_cn61xx cn66xx; 1826 struct cvmx_lmcx_dual_memcfg_cn61xx cn68xx; 1827 struct cvmx_lmcx_dual_memcfg_cn61xx cn68xxp1; 1828 struct cvmx_lmcx_dual_memcfg_cn61xx cnf71xx; 1829 }; 1830 1831 union cvmx_lmcx_ecc_synd { 1832 uint64_t u64; 1833 struct cvmx_lmcx_ecc_synd_s { 1834 #ifdef __BIG_ENDIAN_BITFIELD 1835 uint64_t reserved_32_63:32; 1836 uint64_t mrdsyn3:8; 1837 uint64_t mrdsyn2:8; 1838 uint64_t mrdsyn1:8; 1839 uint64_t mrdsyn0:8; 1840 #else 1841 uint64_t mrdsyn0:8; 1842 uint64_t mrdsyn1:8; 1843 uint64_t mrdsyn2:8; 1844 uint64_t mrdsyn3:8; 1845 uint64_t reserved_32_63:32; 1846 #endif 1847 } s; 1848 struct cvmx_lmcx_ecc_synd_s cn30xx; 1849 struct cvmx_lmcx_ecc_synd_s cn31xx; 1850 struct cvmx_lmcx_ecc_synd_s cn38xx; 1851 struct cvmx_lmcx_ecc_synd_s cn38xxp2; 1852 struct cvmx_lmcx_ecc_synd_s cn50xx; 1853 struct cvmx_lmcx_ecc_synd_s cn52xx; 1854 struct cvmx_lmcx_ecc_synd_s cn52xxp1; 1855 struct cvmx_lmcx_ecc_synd_s cn56xx; 1856 struct cvmx_lmcx_ecc_synd_s cn56xxp1; 1857 struct cvmx_lmcx_ecc_synd_s cn58xx; 1858 struct cvmx_lmcx_ecc_synd_s cn58xxp1; 1859 struct cvmx_lmcx_ecc_synd_s cn61xx; 1860 struct cvmx_lmcx_ecc_synd_s cn63xx; 1861 struct cvmx_lmcx_ecc_synd_s cn63xxp1; 1862 struct cvmx_lmcx_ecc_synd_s cn66xx; 1863 struct cvmx_lmcx_ecc_synd_s cn68xx; 1864 struct cvmx_lmcx_ecc_synd_s cn68xxp1; 1865 struct cvmx_lmcx_ecc_synd_s cnf71xx; 1866 }; 1867 1868 union cvmx_lmcx_fadr { 1869 uint64_t u64; 1870 struct cvmx_lmcx_fadr_s { 1871 #ifdef __BIG_ENDIAN_BITFIELD 1872 uint64_t reserved_0_63:64; 1873 #else 1874 uint64_t reserved_0_63:64; 1875 #endif 1876 } s; 1877 struct cvmx_lmcx_fadr_cn30xx { 1878 #ifdef __BIG_ENDIAN_BITFIELD 1879 uint64_t reserved_32_63:32; 1880 uint64_t fdimm:2; 1881 uint64_t fbunk:1; 1882 uint64_t fbank:3; 1883 uint64_t frow:14; 1884 uint64_t fcol:12; 1885 #else 1886 uint64_t fcol:12; 1887 uint64_t frow:14; 1888 uint64_t fbank:3; 1889 uint64_t fbunk:1; 1890 uint64_t fdimm:2; 1891 uint64_t reserved_32_63:32; 1892 #endif 1893 } cn30xx; 1894 struct cvmx_lmcx_fadr_cn30xx cn31xx; 1895 struct cvmx_lmcx_fadr_cn30xx cn38xx; 1896 struct cvmx_lmcx_fadr_cn30xx cn38xxp2; 1897 struct cvmx_lmcx_fadr_cn30xx cn50xx; 1898 struct cvmx_lmcx_fadr_cn30xx cn52xx; 1899 struct cvmx_lmcx_fadr_cn30xx cn52xxp1; 1900 struct cvmx_lmcx_fadr_cn30xx cn56xx; 1901 struct cvmx_lmcx_fadr_cn30xx cn56xxp1; 1902 struct cvmx_lmcx_fadr_cn30xx cn58xx; 1903 struct cvmx_lmcx_fadr_cn30xx cn58xxp1; 1904 struct cvmx_lmcx_fadr_cn61xx { 1905 #ifdef __BIG_ENDIAN_BITFIELD 1906 uint64_t reserved_36_63:28; 1907 uint64_t fdimm:2; 1908 uint64_t fbunk:1; 1909 uint64_t fbank:3; 1910 uint64_t frow:16; 1911 uint64_t fcol:14; 1912 #else 1913 uint64_t fcol:14; 1914 uint64_t frow:16; 1915 uint64_t fbank:3; 1916 uint64_t fbunk:1; 1917 uint64_t fdimm:2; 1918 uint64_t reserved_36_63:28; 1919 #endif 1920 } cn61xx; 1921 struct cvmx_lmcx_fadr_cn61xx cn63xx; 1922 struct cvmx_lmcx_fadr_cn61xx cn63xxp1; 1923 struct cvmx_lmcx_fadr_cn61xx cn66xx; 1924 struct cvmx_lmcx_fadr_cn61xx cn68xx; 1925 struct cvmx_lmcx_fadr_cn61xx cn68xxp1; 1926 struct cvmx_lmcx_fadr_cn61xx cnf71xx; 1927 }; 1928 1929 union cvmx_lmcx_ifb_cnt { 1930 uint64_t u64; 1931 struct cvmx_lmcx_ifb_cnt_s { 1932 #ifdef __BIG_ENDIAN_BITFIELD 1933 uint64_t ifbcnt:64; 1934 #else 1935 uint64_t ifbcnt:64; 1936 #endif 1937 } s; 1938 struct cvmx_lmcx_ifb_cnt_s cn61xx; 1939 struct cvmx_lmcx_ifb_cnt_s cn63xx; 1940 struct cvmx_lmcx_ifb_cnt_s cn63xxp1; 1941 struct cvmx_lmcx_ifb_cnt_s cn66xx; 1942 struct cvmx_lmcx_ifb_cnt_s cn68xx; 1943 struct cvmx_lmcx_ifb_cnt_s cn68xxp1; 1944 struct cvmx_lmcx_ifb_cnt_s cnf71xx; 1945 }; 1946 1947 union cvmx_lmcx_ifb_cnt_hi { 1948 uint64_t u64; 1949 struct cvmx_lmcx_ifb_cnt_hi_s { 1950 #ifdef __BIG_ENDIAN_BITFIELD 1951 uint64_t reserved_32_63:32; 1952 uint64_t ifbcnt_hi:32; 1953 #else 1954 uint64_t ifbcnt_hi:32; 1955 uint64_t reserved_32_63:32; 1956 #endif 1957 } s; 1958 struct cvmx_lmcx_ifb_cnt_hi_s cn30xx; 1959 struct cvmx_lmcx_ifb_cnt_hi_s cn31xx; 1960 struct cvmx_lmcx_ifb_cnt_hi_s cn38xx; 1961 struct cvmx_lmcx_ifb_cnt_hi_s cn38xxp2; 1962 struct cvmx_lmcx_ifb_cnt_hi_s cn50xx; 1963 struct cvmx_lmcx_ifb_cnt_hi_s cn52xx; 1964 struct cvmx_lmcx_ifb_cnt_hi_s cn52xxp1; 1965 struct cvmx_lmcx_ifb_cnt_hi_s cn56xx; 1966 struct cvmx_lmcx_ifb_cnt_hi_s cn56xxp1; 1967 struct cvmx_lmcx_ifb_cnt_hi_s cn58xx; 1968 struct cvmx_lmcx_ifb_cnt_hi_s cn58xxp1; 1969 }; 1970 1971 union cvmx_lmcx_ifb_cnt_lo { 1972 uint64_t u64; 1973 struct cvmx_lmcx_ifb_cnt_lo_s { 1974 #ifdef __BIG_ENDIAN_BITFIELD 1975 uint64_t reserved_32_63:32; 1976 uint64_t ifbcnt_lo:32; 1977 #else 1978 uint64_t ifbcnt_lo:32; 1979 uint64_t reserved_32_63:32; 1980 #endif 1981 } s; 1982 struct cvmx_lmcx_ifb_cnt_lo_s cn30xx; 1983 struct cvmx_lmcx_ifb_cnt_lo_s cn31xx; 1984 struct cvmx_lmcx_ifb_cnt_lo_s cn38xx; 1985 struct cvmx_lmcx_ifb_cnt_lo_s cn38xxp2; 1986 struct cvmx_lmcx_ifb_cnt_lo_s cn50xx; 1987 struct cvmx_lmcx_ifb_cnt_lo_s cn52xx; 1988 struct cvmx_lmcx_ifb_cnt_lo_s cn52xxp1; 1989 struct cvmx_lmcx_ifb_cnt_lo_s cn56xx; 1990 struct cvmx_lmcx_ifb_cnt_lo_s cn56xxp1; 1991 struct cvmx_lmcx_ifb_cnt_lo_s cn58xx; 1992 struct cvmx_lmcx_ifb_cnt_lo_s cn58xxp1; 1993 }; 1994 1995 union cvmx_lmcx_int { 1996 uint64_t u64; 1997 struct cvmx_lmcx_int_s { 1998 #ifdef __BIG_ENDIAN_BITFIELD 1999 uint64_t reserved_9_63:55; 2000 uint64_t ded_err:4; 2001 uint64_t sec_err:4; 2002 uint64_t nxm_wr_err:1; 2003 #else 2004 uint64_t nxm_wr_err:1; 2005 uint64_t sec_err:4; 2006 uint64_t ded_err:4; 2007 uint64_t reserved_9_63:55; 2008 #endif 2009 } s; 2010 struct cvmx_lmcx_int_s cn61xx; 2011 struct cvmx_lmcx_int_s cn63xx; 2012 struct cvmx_lmcx_int_s cn63xxp1; 2013 struct cvmx_lmcx_int_s cn66xx; 2014 struct cvmx_lmcx_int_s cn68xx; 2015 struct cvmx_lmcx_int_s cn68xxp1; 2016 struct cvmx_lmcx_int_s cnf71xx; 2017 }; 2018 2019 union cvmx_lmcx_int_en { 2020 uint64_t u64; 2021 struct cvmx_lmcx_int_en_s { 2022 #ifdef __BIG_ENDIAN_BITFIELD 2023 uint64_t reserved_3_63:61; 2024 uint64_t intr_ded_ena:1; 2025 uint64_t intr_sec_ena:1; 2026 uint64_t intr_nxm_wr_ena:1; 2027 #else 2028 uint64_t intr_nxm_wr_ena:1; 2029 uint64_t intr_sec_ena:1; 2030 uint64_t intr_ded_ena:1; 2031 uint64_t reserved_3_63:61; 2032 #endif 2033 } s; 2034 struct cvmx_lmcx_int_en_s cn61xx; 2035 struct cvmx_lmcx_int_en_s cn63xx; 2036 struct cvmx_lmcx_int_en_s cn63xxp1; 2037 struct cvmx_lmcx_int_en_s cn66xx; 2038 struct cvmx_lmcx_int_en_s cn68xx; 2039 struct cvmx_lmcx_int_en_s cn68xxp1; 2040 struct cvmx_lmcx_int_en_s cnf71xx; 2041 }; 2042 2043 union cvmx_lmcx_mem_cfg0 { 2044 uint64_t u64; 2045 struct cvmx_lmcx_mem_cfg0_s { 2046 #ifdef __BIG_ENDIAN_BITFIELD 2047 uint64_t reserved_32_63:32; 2048 uint64_t reset:1; 2049 uint64_t silo_qc:1; 2050 uint64_t bunk_ena:1; 2051 uint64_t ded_err:4; 2052 uint64_t sec_err:4; 2053 uint64_t intr_ded_ena:1; 2054 uint64_t intr_sec_ena:1; 2055 uint64_t tcl:4; 2056 uint64_t ref_int:6; 2057 uint64_t pbank_lsb:4; 2058 uint64_t row_lsb:3; 2059 uint64_t ecc_ena:1; 2060 uint64_t init_start:1; 2061 #else 2062 uint64_t init_start:1; 2063 uint64_t ecc_ena:1; 2064 uint64_t row_lsb:3; 2065 uint64_t pbank_lsb:4; 2066 uint64_t ref_int:6; 2067 uint64_t tcl:4; 2068 uint64_t intr_sec_ena:1; 2069 uint64_t intr_ded_ena:1; 2070 uint64_t sec_err:4; 2071 uint64_t ded_err:4; 2072 uint64_t bunk_ena:1; 2073 uint64_t silo_qc:1; 2074 uint64_t reset:1; 2075 uint64_t reserved_32_63:32; 2076 #endif 2077 } s; 2078 struct cvmx_lmcx_mem_cfg0_s cn30xx; 2079 struct cvmx_lmcx_mem_cfg0_s cn31xx; 2080 struct cvmx_lmcx_mem_cfg0_s cn38xx; 2081 struct cvmx_lmcx_mem_cfg0_s cn38xxp2; 2082 struct cvmx_lmcx_mem_cfg0_s cn50xx; 2083 struct cvmx_lmcx_mem_cfg0_s cn52xx; 2084 struct cvmx_lmcx_mem_cfg0_s cn52xxp1; 2085 struct cvmx_lmcx_mem_cfg0_s cn56xx; 2086 struct cvmx_lmcx_mem_cfg0_s cn56xxp1; 2087 struct cvmx_lmcx_mem_cfg0_s cn58xx; 2088 struct cvmx_lmcx_mem_cfg0_s cn58xxp1; 2089 }; 2090 2091 union cvmx_lmcx_mem_cfg1 { 2092 uint64_t u64; 2093 struct cvmx_lmcx_mem_cfg1_s { 2094 #ifdef __BIG_ENDIAN_BITFIELD 2095 uint64_t reserved_32_63:32; 2096 uint64_t comp_bypass:1; 2097 uint64_t trrd:3; 2098 uint64_t caslat:3; 2099 uint64_t tmrd:3; 2100 uint64_t trfc:5; 2101 uint64_t trp:4; 2102 uint64_t twtr:4; 2103 uint64_t trcd:4; 2104 uint64_t tras:5; 2105 #else 2106 uint64_t tras:5; 2107 uint64_t trcd:4; 2108 uint64_t twtr:4; 2109 uint64_t trp:4; 2110 uint64_t trfc:5; 2111 uint64_t tmrd:3; 2112 uint64_t caslat:3; 2113 uint64_t trrd:3; 2114 uint64_t comp_bypass:1; 2115 uint64_t reserved_32_63:32; 2116 #endif 2117 } s; 2118 struct cvmx_lmcx_mem_cfg1_s cn30xx; 2119 struct cvmx_lmcx_mem_cfg1_s cn31xx; 2120 struct cvmx_lmcx_mem_cfg1_cn38xx { 2121 #ifdef __BIG_ENDIAN_BITFIELD 2122 uint64_t reserved_31_63:33; 2123 uint64_t trrd:3; 2124 uint64_t caslat:3; 2125 uint64_t tmrd:3; 2126 uint64_t trfc:5; 2127 uint64_t trp:4; 2128 uint64_t twtr:4; 2129 uint64_t trcd:4; 2130 uint64_t tras:5; 2131 #else 2132 uint64_t tras:5; 2133 uint64_t trcd:4; 2134 uint64_t twtr:4; 2135 uint64_t trp:4; 2136 uint64_t trfc:5; 2137 uint64_t tmrd:3; 2138 uint64_t caslat:3; 2139 uint64_t trrd:3; 2140 uint64_t reserved_31_63:33; 2141 #endif 2142 } cn38xx; 2143 struct cvmx_lmcx_mem_cfg1_cn38xx cn38xxp2; 2144 struct cvmx_lmcx_mem_cfg1_s cn50xx; 2145 struct cvmx_lmcx_mem_cfg1_cn38xx cn52xx; 2146 struct cvmx_lmcx_mem_cfg1_cn38xx cn52xxp1; 2147 struct cvmx_lmcx_mem_cfg1_cn38xx cn56xx; 2148 struct cvmx_lmcx_mem_cfg1_cn38xx cn56xxp1; 2149 struct cvmx_lmcx_mem_cfg1_cn38xx cn58xx; 2150 struct cvmx_lmcx_mem_cfg1_cn38xx cn58xxp1; 2151 }; 2152 2153 union cvmx_lmcx_modereg_params0 { 2154 uint64_t u64; 2155 struct cvmx_lmcx_modereg_params0_s { 2156 #ifdef __BIG_ENDIAN_BITFIELD 2157 uint64_t reserved_25_63:39; 2158 uint64_t ppd:1; 2159 uint64_t wrp:3; 2160 uint64_t dllr:1; 2161 uint64_t tm:1; 2162 uint64_t rbt:1; 2163 uint64_t cl:4; 2164 uint64_t bl:2; 2165 uint64_t qoff:1; 2166 uint64_t tdqs:1; 2167 uint64_t wlev:1; 2168 uint64_t al:2; 2169 uint64_t dll:1; 2170 uint64_t mpr:1; 2171 uint64_t mprloc:2; 2172 uint64_t cwl:3; 2173 #else 2174 uint64_t cwl:3; 2175 uint64_t mprloc:2; 2176 uint64_t mpr:1; 2177 uint64_t dll:1; 2178 uint64_t al:2; 2179 uint64_t wlev:1; 2180 uint64_t tdqs:1; 2181 uint64_t qoff:1; 2182 uint64_t bl:2; 2183 uint64_t cl:4; 2184 uint64_t rbt:1; 2185 uint64_t tm:1; 2186 uint64_t dllr:1; 2187 uint64_t wrp:3; 2188 uint64_t ppd:1; 2189 uint64_t reserved_25_63:39; 2190 #endif 2191 } s; 2192 struct cvmx_lmcx_modereg_params0_s cn61xx; 2193 struct cvmx_lmcx_modereg_params0_s cn63xx; 2194 struct cvmx_lmcx_modereg_params0_s cn63xxp1; 2195 struct cvmx_lmcx_modereg_params0_s cn66xx; 2196 struct cvmx_lmcx_modereg_params0_s cn68xx; 2197 struct cvmx_lmcx_modereg_params0_s cn68xxp1; 2198 struct cvmx_lmcx_modereg_params0_s cnf71xx; 2199 }; 2200 2201 union cvmx_lmcx_modereg_params1 { 2202 uint64_t u64; 2203 struct cvmx_lmcx_modereg_params1_s { 2204 #ifdef __BIG_ENDIAN_BITFIELD 2205 uint64_t reserved_48_63:16; 2206 uint64_t rtt_nom_11:3; 2207 uint64_t dic_11:2; 2208 uint64_t rtt_wr_11:2; 2209 uint64_t srt_11:1; 2210 uint64_t asr_11:1; 2211 uint64_t pasr_11:3; 2212 uint64_t rtt_nom_10:3; 2213 uint64_t dic_10:2; 2214 uint64_t rtt_wr_10:2; 2215 uint64_t srt_10:1; 2216 uint64_t asr_10:1; 2217 uint64_t pasr_10:3; 2218 uint64_t rtt_nom_01:3; 2219 uint64_t dic_01:2; 2220 uint64_t rtt_wr_01:2; 2221 uint64_t srt_01:1; 2222 uint64_t asr_01:1; 2223 uint64_t pasr_01:3; 2224 uint64_t rtt_nom_00:3; 2225 uint64_t dic_00:2; 2226 uint64_t rtt_wr_00:2; 2227 uint64_t srt_00:1; 2228 uint64_t asr_00:1; 2229 uint64_t pasr_00:3; 2230 #else 2231 uint64_t pasr_00:3; 2232 uint64_t asr_00:1; 2233 uint64_t srt_00:1; 2234 uint64_t rtt_wr_00:2; 2235 uint64_t dic_00:2; 2236 uint64_t rtt_nom_00:3; 2237 uint64_t pasr_01:3; 2238 uint64_t asr_01:1; 2239 uint64_t srt_01:1; 2240 uint64_t rtt_wr_01:2; 2241 uint64_t dic_01:2; 2242 uint64_t rtt_nom_01:3; 2243 uint64_t pasr_10:3; 2244 uint64_t asr_10:1; 2245 uint64_t srt_10:1; 2246 uint64_t rtt_wr_10:2; 2247 uint64_t dic_10:2; 2248 uint64_t rtt_nom_10:3; 2249 uint64_t pasr_11:3; 2250 uint64_t asr_11:1; 2251 uint64_t srt_11:1; 2252 uint64_t rtt_wr_11:2; 2253 uint64_t dic_11:2; 2254 uint64_t rtt_nom_11:3; 2255 uint64_t reserved_48_63:16; 2256 #endif 2257 } s; 2258 struct cvmx_lmcx_modereg_params1_s cn61xx; 2259 struct cvmx_lmcx_modereg_params1_s cn63xx; 2260 struct cvmx_lmcx_modereg_params1_s cn63xxp1; 2261 struct cvmx_lmcx_modereg_params1_s cn66xx; 2262 struct cvmx_lmcx_modereg_params1_s cn68xx; 2263 struct cvmx_lmcx_modereg_params1_s cn68xxp1; 2264 struct cvmx_lmcx_modereg_params1_s cnf71xx; 2265 }; 2266 2267 union cvmx_lmcx_nxm { 2268 uint64_t u64; 2269 struct cvmx_lmcx_nxm_s { 2270 #ifdef __BIG_ENDIAN_BITFIELD 2271 uint64_t reserved_40_63:24; 2272 uint64_t mem_msb_d3_r1:4; 2273 uint64_t mem_msb_d3_r0:4; 2274 uint64_t mem_msb_d2_r1:4; 2275 uint64_t mem_msb_d2_r0:4; 2276 uint64_t mem_msb_d1_r1:4; 2277 uint64_t mem_msb_d1_r0:4; 2278 uint64_t mem_msb_d0_r1:4; 2279 uint64_t mem_msb_d0_r0:4; 2280 uint64_t cs_mask:8; 2281 #else 2282 uint64_t cs_mask:8; 2283 uint64_t mem_msb_d0_r0:4; 2284 uint64_t mem_msb_d0_r1:4; 2285 uint64_t mem_msb_d1_r0:4; 2286 uint64_t mem_msb_d1_r1:4; 2287 uint64_t mem_msb_d2_r0:4; 2288 uint64_t mem_msb_d2_r1:4; 2289 uint64_t mem_msb_d3_r0:4; 2290 uint64_t mem_msb_d3_r1:4; 2291 uint64_t reserved_40_63:24; 2292 #endif 2293 } s; 2294 struct cvmx_lmcx_nxm_cn52xx { 2295 #ifdef __BIG_ENDIAN_BITFIELD 2296 uint64_t reserved_8_63:56; 2297 uint64_t cs_mask:8; 2298 #else 2299 uint64_t cs_mask:8; 2300 uint64_t reserved_8_63:56; 2301 #endif 2302 } cn52xx; 2303 struct cvmx_lmcx_nxm_cn52xx cn56xx; 2304 struct cvmx_lmcx_nxm_cn52xx cn58xx; 2305 struct cvmx_lmcx_nxm_s cn61xx; 2306 struct cvmx_lmcx_nxm_s cn63xx; 2307 struct cvmx_lmcx_nxm_s cn63xxp1; 2308 struct cvmx_lmcx_nxm_s cn66xx; 2309 struct cvmx_lmcx_nxm_s cn68xx; 2310 struct cvmx_lmcx_nxm_s cn68xxp1; 2311 struct cvmx_lmcx_nxm_s cnf71xx; 2312 }; 2313 2314 union cvmx_lmcx_ops_cnt { 2315 uint64_t u64; 2316 struct cvmx_lmcx_ops_cnt_s { 2317 #ifdef __BIG_ENDIAN_BITFIELD 2318 uint64_t opscnt:64; 2319 #else 2320 uint64_t opscnt:64; 2321 #endif 2322 } s; 2323 struct cvmx_lmcx_ops_cnt_s cn61xx; 2324 struct cvmx_lmcx_ops_cnt_s cn63xx; 2325 struct cvmx_lmcx_ops_cnt_s cn63xxp1; 2326 struct cvmx_lmcx_ops_cnt_s cn66xx; 2327 struct cvmx_lmcx_ops_cnt_s cn68xx; 2328 struct cvmx_lmcx_ops_cnt_s cn68xxp1; 2329 struct cvmx_lmcx_ops_cnt_s cnf71xx; 2330 }; 2331 2332 union cvmx_lmcx_ops_cnt_hi { 2333 uint64_t u64; 2334 struct cvmx_lmcx_ops_cnt_hi_s { 2335 #ifdef __BIG_ENDIAN_BITFIELD 2336 uint64_t reserved_32_63:32; 2337 uint64_t opscnt_hi:32; 2338 #else 2339 uint64_t opscnt_hi:32; 2340 uint64_t reserved_32_63:32; 2341 #endif 2342 } s; 2343 struct cvmx_lmcx_ops_cnt_hi_s cn30xx; 2344 struct cvmx_lmcx_ops_cnt_hi_s cn31xx; 2345 struct cvmx_lmcx_ops_cnt_hi_s cn38xx; 2346 struct cvmx_lmcx_ops_cnt_hi_s cn38xxp2; 2347 struct cvmx_lmcx_ops_cnt_hi_s cn50xx; 2348 struct cvmx_lmcx_ops_cnt_hi_s cn52xx; 2349 struct cvmx_lmcx_ops_cnt_hi_s cn52xxp1; 2350 struct cvmx_lmcx_ops_cnt_hi_s cn56xx; 2351 struct cvmx_lmcx_ops_cnt_hi_s cn56xxp1; 2352 struct cvmx_lmcx_ops_cnt_hi_s cn58xx; 2353 struct cvmx_lmcx_ops_cnt_hi_s cn58xxp1; 2354 }; 2355 2356 union cvmx_lmcx_ops_cnt_lo { 2357 uint64_t u64; 2358 struct cvmx_lmcx_ops_cnt_lo_s { 2359 #ifdef __BIG_ENDIAN_BITFIELD 2360 uint64_t reserved_32_63:32; 2361 uint64_t opscnt_lo:32; 2362 #else 2363 uint64_t opscnt_lo:32; 2364 uint64_t reserved_32_63:32; 2365 #endif 2366 } s; 2367 struct cvmx_lmcx_ops_cnt_lo_s cn30xx; 2368 struct cvmx_lmcx_ops_cnt_lo_s cn31xx; 2369 struct cvmx_lmcx_ops_cnt_lo_s cn38xx; 2370 struct cvmx_lmcx_ops_cnt_lo_s cn38xxp2; 2371 struct cvmx_lmcx_ops_cnt_lo_s cn50xx; 2372 struct cvmx_lmcx_ops_cnt_lo_s cn52xx; 2373 struct cvmx_lmcx_ops_cnt_lo_s cn52xxp1; 2374 struct cvmx_lmcx_ops_cnt_lo_s cn56xx; 2375 struct cvmx_lmcx_ops_cnt_lo_s cn56xxp1; 2376 struct cvmx_lmcx_ops_cnt_lo_s cn58xx; 2377 struct cvmx_lmcx_ops_cnt_lo_s cn58xxp1; 2378 }; 2379 2380 union cvmx_lmcx_phy_ctl { 2381 uint64_t u64; 2382 struct cvmx_lmcx_phy_ctl_s { 2383 #ifdef __BIG_ENDIAN_BITFIELD 2384 uint64_t reserved_15_63:49; 2385 uint64_t rx_always_on:1; 2386 uint64_t lv_mode:1; 2387 uint64_t ck_tune1:1; 2388 uint64_t ck_dlyout1:4; 2389 uint64_t ck_tune0:1; 2390 uint64_t ck_dlyout0:4; 2391 uint64_t loopback:1; 2392 uint64_t loopback_pos:1; 2393 uint64_t ts_stagger:1; 2394 #else 2395 uint64_t ts_stagger:1; 2396 uint64_t loopback_pos:1; 2397 uint64_t loopback:1; 2398 uint64_t ck_dlyout0:4; 2399 uint64_t ck_tune0:1; 2400 uint64_t ck_dlyout1:4; 2401 uint64_t ck_tune1:1; 2402 uint64_t lv_mode:1; 2403 uint64_t rx_always_on:1; 2404 uint64_t reserved_15_63:49; 2405 #endif 2406 } s; 2407 struct cvmx_lmcx_phy_ctl_s cn61xx; 2408 struct cvmx_lmcx_phy_ctl_s cn63xx; 2409 struct cvmx_lmcx_phy_ctl_cn63xxp1 { 2410 #ifdef __BIG_ENDIAN_BITFIELD 2411 uint64_t reserved_14_63:50; 2412 uint64_t lv_mode:1; 2413 uint64_t ck_tune1:1; 2414 uint64_t ck_dlyout1:4; 2415 uint64_t ck_tune0:1; 2416 uint64_t ck_dlyout0:4; 2417 uint64_t loopback:1; 2418 uint64_t loopback_pos:1; 2419 uint64_t ts_stagger:1; 2420 #else 2421 uint64_t ts_stagger:1; 2422 uint64_t loopback_pos:1; 2423 uint64_t loopback:1; 2424 uint64_t ck_dlyout0:4; 2425 uint64_t ck_tune0:1; 2426 uint64_t ck_dlyout1:4; 2427 uint64_t ck_tune1:1; 2428 uint64_t lv_mode:1; 2429 uint64_t reserved_14_63:50; 2430 #endif 2431 } cn63xxp1; 2432 struct cvmx_lmcx_phy_ctl_s cn66xx; 2433 struct cvmx_lmcx_phy_ctl_s cn68xx; 2434 struct cvmx_lmcx_phy_ctl_s cn68xxp1; 2435 struct cvmx_lmcx_phy_ctl_s cnf71xx; 2436 }; 2437 2438 union cvmx_lmcx_pll_bwctl { 2439 uint64_t u64; 2440 struct cvmx_lmcx_pll_bwctl_s { 2441 #ifdef __BIG_ENDIAN_BITFIELD 2442 uint64_t reserved_5_63:59; 2443 uint64_t bwupd:1; 2444 uint64_t bwctl:4; 2445 #else 2446 uint64_t bwctl:4; 2447 uint64_t bwupd:1; 2448 uint64_t reserved_5_63:59; 2449 #endif 2450 } s; 2451 struct cvmx_lmcx_pll_bwctl_s cn30xx; 2452 struct cvmx_lmcx_pll_bwctl_s cn31xx; 2453 struct cvmx_lmcx_pll_bwctl_s cn38xx; 2454 struct cvmx_lmcx_pll_bwctl_s cn38xxp2; 2455 }; 2456 2457 union cvmx_lmcx_pll_ctl { 2458 uint64_t u64; 2459 struct cvmx_lmcx_pll_ctl_s { 2460 #ifdef __BIG_ENDIAN_BITFIELD 2461 uint64_t reserved_30_63:34; 2462 uint64_t bypass:1; 2463 uint64_t fasten_n:1; 2464 uint64_t div_reset:1; 2465 uint64_t reset_n:1; 2466 uint64_t clkf:12; 2467 uint64_t clkr:6; 2468 uint64_t reserved_6_7:2; 2469 uint64_t en16:1; 2470 uint64_t en12:1; 2471 uint64_t en8:1; 2472 uint64_t en6:1; 2473 uint64_t en4:1; 2474 uint64_t en2:1; 2475 #else 2476 uint64_t en2:1; 2477 uint64_t en4:1; 2478 uint64_t en6:1; 2479 uint64_t en8:1; 2480 uint64_t en12:1; 2481 uint64_t en16:1; 2482 uint64_t reserved_6_7:2; 2483 uint64_t clkr:6; 2484 uint64_t clkf:12; 2485 uint64_t reset_n:1; 2486 uint64_t div_reset:1; 2487 uint64_t fasten_n:1; 2488 uint64_t bypass:1; 2489 uint64_t reserved_30_63:34; 2490 #endif 2491 } s; 2492 struct cvmx_lmcx_pll_ctl_cn50xx { 2493 #ifdef __BIG_ENDIAN_BITFIELD 2494 uint64_t reserved_29_63:35; 2495 uint64_t fasten_n:1; 2496 uint64_t div_reset:1; 2497 uint64_t reset_n:1; 2498 uint64_t clkf:12; 2499 uint64_t clkr:6; 2500 uint64_t reserved_6_7:2; 2501 uint64_t en16:1; 2502 uint64_t en12:1; 2503 uint64_t en8:1; 2504 uint64_t en6:1; 2505 uint64_t en4:1; 2506 uint64_t en2:1; 2507 #else 2508 uint64_t en2:1; 2509 uint64_t en4:1; 2510 uint64_t en6:1; 2511 uint64_t en8:1; 2512 uint64_t en12:1; 2513 uint64_t en16:1; 2514 uint64_t reserved_6_7:2; 2515 uint64_t clkr:6; 2516 uint64_t clkf:12; 2517 uint64_t reset_n:1; 2518 uint64_t div_reset:1; 2519 uint64_t fasten_n:1; 2520 uint64_t reserved_29_63:35; 2521 #endif 2522 } cn50xx; 2523 struct cvmx_lmcx_pll_ctl_s cn52xx; 2524 struct cvmx_lmcx_pll_ctl_s cn52xxp1; 2525 struct cvmx_lmcx_pll_ctl_cn50xx cn56xx; 2526 struct cvmx_lmcx_pll_ctl_cn56xxp1 { 2527 #ifdef __BIG_ENDIAN_BITFIELD 2528 uint64_t reserved_28_63:36; 2529 uint64_t div_reset:1; 2530 uint64_t reset_n:1; 2531 uint64_t clkf:12; 2532 uint64_t clkr:6; 2533 uint64_t reserved_6_7:2; 2534 uint64_t en16:1; 2535 uint64_t en12:1; 2536 uint64_t en8:1; 2537 uint64_t en6:1; 2538 uint64_t en4:1; 2539 uint64_t en2:1; 2540 #else 2541 uint64_t en2:1; 2542 uint64_t en4:1; 2543 uint64_t en6:1; 2544 uint64_t en8:1; 2545 uint64_t en12:1; 2546 uint64_t en16:1; 2547 uint64_t reserved_6_7:2; 2548 uint64_t clkr:6; 2549 uint64_t clkf:12; 2550 uint64_t reset_n:1; 2551 uint64_t div_reset:1; 2552 uint64_t reserved_28_63:36; 2553 #endif 2554 } cn56xxp1; 2555 struct cvmx_lmcx_pll_ctl_cn56xxp1 cn58xx; 2556 struct cvmx_lmcx_pll_ctl_cn56xxp1 cn58xxp1; 2557 }; 2558 2559 union cvmx_lmcx_pll_status { 2560 uint64_t u64; 2561 struct cvmx_lmcx_pll_status_s { 2562 #ifdef __BIG_ENDIAN_BITFIELD 2563 uint64_t reserved_32_63:32; 2564 uint64_t ddr__nctl:5; 2565 uint64_t ddr__pctl:5; 2566 uint64_t reserved_2_21:20; 2567 uint64_t rfslip:1; 2568 uint64_t fbslip:1; 2569 #else 2570 uint64_t fbslip:1; 2571 uint64_t rfslip:1; 2572 uint64_t reserved_2_21:20; 2573 uint64_t ddr__pctl:5; 2574 uint64_t ddr__nctl:5; 2575 uint64_t reserved_32_63:32; 2576 #endif 2577 } s; 2578 struct cvmx_lmcx_pll_status_s cn50xx; 2579 struct cvmx_lmcx_pll_status_s cn52xx; 2580 struct cvmx_lmcx_pll_status_s cn52xxp1; 2581 struct cvmx_lmcx_pll_status_s cn56xx; 2582 struct cvmx_lmcx_pll_status_s cn56xxp1; 2583 struct cvmx_lmcx_pll_status_s cn58xx; 2584 struct cvmx_lmcx_pll_status_cn58xxp1 { 2585 #ifdef __BIG_ENDIAN_BITFIELD 2586 uint64_t reserved_2_63:62; 2587 uint64_t rfslip:1; 2588 uint64_t fbslip:1; 2589 #else 2590 uint64_t fbslip:1; 2591 uint64_t rfslip:1; 2592 uint64_t reserved_2_63:62; 2593 #endif 2594 } cn58xxp1; 2595 }; 2596 2597 union cvmx_lmcx_read_level_ctl { 2598 uint64_t u64; 2599 struct cvmx_lmcx_read_level_ctl_s { 2600 #ifdef __BIG_ENDIAN_BITFIELD 2601 uint64_t reserved_44_63:20; 2602 uint64_t rankmask:4; 2603 uint64_t pattern:8; 2604 uint64_t row:16; 2605 uint64_t col:12; 2606 uint64_t reserved_3_3:1; 2607 uint64_t bnk:3; 2608 #else 2609 uint64_t bnk:3; 2610 uint64_t reserved_3_3:1; 2611 uint64_t col:12; 2612 uint64_t row:16; 2613 uint64_t pattern:8; 2614 uint64_t rankmask:4; 2615 uint64_t reserved_44_63:20; 2616 #endif 2617 } s; 2618 struct cvmx_lmcx_read_level_ctl_s cn52xx; 2619 struct cvmx_lmcx_read_level_ctl_s cn52xxp1; 2620 struct cvmx_lmcx_read_level_ctl_s cn56xx; 2621 struct cvmx_lmcx_read_level_ctl_s cn56xxp1; 2622 }; 2623 2624 union cvmx_lmcx_read_level_dbg { 2625 uint64_t u64; 2626 struct cvmx_lmcx_read_level_dbg_s { 2627 #ifdef __BIG_ENDIAN_BITFIELD 2628 uint64_t reserved_32_63:32; 2629 uint64_t bitmask:16; 2630 uint64_t reserved_4_15:12; 2631 uint64_t byte:4; 2632 #else 2633 uint64_t byte:4; 2634 uint64_t reserved_4_15:12; 2635 uint64_t bitmask:16; 2636 uint64_t reserved_32_63:32; 2637 #endif 2638 } s; 2639 struct cvmx_lmcx_read_level_dbg_s cn52xx; 2640 struct cvmx_lmcx_read_level_dbg_s cn52xxp1; 2641 struct cvmx_lmcx_read_level_dbg_s cn56xx; 2642 struct cvmx_lmcx_read_level_dbg_s cn56xxp1; 2643 }; 2644 2645 union cvmx_lmcx_read_level_rankx { 2646 uint64_t u64; 2647 struct cvmx_lmcx_read_level_rankx_s { 2648 #ifdef __BIG_ENDIAN_BITFIELD 2649 uint64_t reserved_38_63:26; 2650 uint64_t status:2; 2651 uint64_t byte8:4; 2652 uint64_t byte7:4; 2653 uint64_t byte6:4; 2654 uint64_t byte5:4; 2655 uint64_t byte4:4; 2656 uint64_t byte3:4; 2657 uint64_t byte2:4; 2658 uint64_t byte1:4; 2659 uint64_t byte0:4; 2660 #else 2661 uint64_t byte0:4; 2662 uint64_t byte1:4; 2663 uint64_t byte2:4; 2664 uint64_t byte3:4; 2665 uint64_t byte4:4; 2666 uint64_t byte5:4; 2667 uint64_t byte6:4; 2668 uint64_t byte7:4; 2669 uint64_t byte8:4; 2670 uint64_t status:2; 2671 uint64_t reserved_38_63:26; 2672 #endif 2673 } s; 2674 struct cvmx_lmcx_read_level_rankx_s cn52xx; 2675 struct cvmx_lmcx_read_level_rankx_s cn52xxp1; 2676 struct cvmx_lmcx_read_level_rankx_s cn56xx; 2677 struct cvmx_lmcx_read_level_rankx_s cn56xxp1; 2678 }; 2679 2680 union cvmx_lmcx_reset_ctl { 2681 uint64_t u64; 2682 struct cvmx_lmcx_reset_ctl_s { 2683 #ifdef __BIG_ENDIAN_BITFIELD 2684 uint64_t reserved_4_63:60; 2685 uint64_t ddr3psv:1; 2686 uint64_t ddr3psoft:1; 2687 uint64_t ddr3pwarm:1; 2688 uint64_t ddr3rst:1; 2689 #else 2690 uint64_t ddr3rst:1; 2691 uint64_t ddr3pwarm:1; 2692 uint64_t ddr3psoft:1; 2693 uint64_t ddr3psv:1; 2694 uint64_t reserved_4_63:60; 2695 #endif 2696 } s; 2697 struct cvmx_lmcx_reset_ctl_s cn61xx; 2698 struct cvmx_lmcx_reset_ctl_s cn63xx; 2699 struct cvmx_lmcx_reset_ctl_s cn63xxp1; 2700 struct cvmx_lmcx_reset_ctl_s cn66xx; 2701 struct cvmx_lmcx_reset_ctl_s cn68xx; 2702 struct cvmx_lmcx_reset_ctl_s cn68xxp1; 2703 struct cvmx_lmcx_reset_ctl_s cnf71xx; 2704 }; 2705 2706 union cvmx_lmcx_rlevel_ctl { 2707 uint64_t u64; 2708 struct cvmx_lmcx_rlevel_ctl_s { 2709 #ifdef __BIG_ENDIAN_BITFIELD 2710 uint64_t reserved_22_63:42; 2711 uint64_t delay_unload_3:1; 2712 uint64_t delay_unload_2:1; 2713 uint64_t delay_unload_1:1; 2714 uint64_t delay_unload_0:1; 2715 uint64_t bitmask:8; 2716 uint64_t or_dis:1; 2717 uint64_t offset_en:1; 2718 uint64_t offset:4; 2719 uint64_t byte:4; 2720 #else 2721 uint64_t byte:4; 2722 uint64_t offset:4; 2723 uint64_t offset_en:1; 2724 uint64_t or_dis:1; 2725 uint64_t bitmask:8; 2726 uint64_t delay_unload_0:1; 2727 uint64_t delay_unload_1:1; 2728 uint64_t delay_unload_2:1; 2729 uint64_t delay_unload_3:1; 2730 uint64_t reserved_22_63:42; 2731 #endif 2732 } s; 2733 struct cvmx_lmcx_rlevel_ctl_s cn61xx; 2734 struct cvmx_lmcx_rlevel_ctl_s cn63xx; 2735 struct cvmx_lmcx_rlevel_ctl_cn63xxp1 { 2736 #ifdef __BIG_ENDIAN_BITFIELD 2737 uint64_t reserved_9_63:55; 2738 uint64_t offset_en:1; 2739 uint64_t offset:4; 2740 uint64_t byte:4; 2741 #else 2742 uint64_t byte:4; 2743 uint64_t offset:4; 2744 uint64_t offset_en:1; 2745 uint64_t reserved_9_63:55; 2746 #endif 2747 } cn63xxp1; 2748 struct cvmx_lmcx_rlevel_ctl_s cn66xx; 2749 struct cvmx_lmcx_rlevel_ctl_s cn68xx; 2750 struct cvmx_lmcx_rlevel_ctl_s cn68xxp1; 2751 struct cvmx_lmcx_rlevel_ctl_s cnf71xx; 2752 }; 2753 2754 union cvmx_lmcx_rlevel_dbg { 2755 uint64_t u64; 2756 struct cvmx_lmcx_rlevel_dbg_s { 2757 #ifdef __BIG_ENDIAN_BITFIELD 2758 uint64_t bitmask:64; 2759 #else 2760 uint64_t bitmask:64; 2761 #endif 2762 } s; 2763 struct cvmx_lmcx_rlevel_dbg_s cn61xx; 2764 struct cvmx_lmcx_rlevel_dbg_s cn63xx; 2765 struct cvmx_lmcx_rlevel_dbg_s cn63xxp1; 2766 struct cvmx_lmcx_rlevel_dbg_s cn66xx; 2767 struct cvmx_lmcx_rlevel_dbg_s cn68xx; 2768 struct cvmx_lmcx_rlevel_dbg_s cn68xxp1; 2769 struct cvmx_lmcx_rlevel_dbg_s cnf71xx; 2770 }; 2771 2772 union cvmx_lmcx_rlevel_rankx { 2773 uint64_t u64; 2774 struct cvmx_lmcx_rlevel_rankx_s { 2775 #ifdef __BIG_ENDIAN_BITFIELD 2776 uint64_t reserved_56_63:8; 2777 uint64_t status:2; 2778 uint64_t byte8:6; 2779 uint64_t byte7:6; 2780 uint64_t byte6:6; 2781 uint64_t byte5:6; 2782 uint64_t byte4:6; 2783 uint64_t byte3:6; 2784 uint64_t byte2:6; 2785 uint64_t byte1:6; 2786 uint64_t byte0:6; 2787 #else 2788 uint64_t byte0:6; 2789 uint64_t byte1:6; 2790 uint64_t byte2:6; 2791 uint64_t byte3:6; 2792 uint64_t byte4:6; 2793 uint64_t byte5:6; 2794 uint64_t byte6:6; 2795 uint64_t byte7:6; 2796 uint64_t byte8:6; 2797 uint64_t status:2; 2798 uint64_t reserved_56_63:8; 2799 #endif 2800 } s; 2801 struct cvmx_lmcx_rlevel_rankx_s cn61xx; 2802 struct cvmx_lmcx_rlevel_rankx_s cn63xx; 2803 struct cvmx_lmcx_rlevel_rankx_s cn63xxp1; 2804 struct cvmx_lmcx_rlevel_rankx_s cn66xx; 2805 struct cvmx_lmcx_rlevel_rankx_s cn68xx; 2806 struct cvmx_lmcx_rlevel_rankx_s cn68xxp1; 2807 struct cvmx_lmcx_rlevel_rankx_s cnf71xx; 2808 }; 2809 2810 union cvmx_lmcx_rodt_comp_ctl { 2811 uint64_t u64; 2812 struct cvmx_lmcx_rodt_comp_ctl_s { 2813 #ifdef __BIG_ENDIAN_BITFIELD 2814 uint64_t reserved_17_63:47; 2815 uint64_t enable:1; 2816 uint64_t reserved_12_15:4; 2817 uint64_t nctl:4; 2818 uint64_t reserved_5_7:3; 2819 uint64_t pctl:5; 2820 #else 2821 uint64_t pctl:5; 2822 uint64_t reserved_5_7:3; 2823 uint64_t nctl:4; 2824 uint64_t reserved_12_15:4; 2825 uint64_t enable:1; 2826 uint64_t reserved_17_63:47; 2827 #endif 2828 } s; 2829 struct cvmx_lmcx_rodt_comp_ctl_s cn50xx; 2830 struct cvmx_lmcx_rodt_comp_ctl_s cn52xx; 2831 struct cvmx_lmcx_rodt_comp_ctl_s cn52xxp1; 2832 struct cvmx_lmcx_rodt_comp_ctl_s cn56xx; 2833 struct cvmx_lmcx_rodt_comp_ctl_s cn56xxp1; 2834 struct cvmx_lmcx_rodt_comp_ctl_s cn58xx; 2835 struct cvmx_lmcx_rodt_comp_ctl_s cn58xxp1; 2836 }; 2837 2838 union cvmx_lmcx_rodt_ctl { 2839 uint64_t u64; 2840 struct cvmx_lmcx_rodt_ctl_s { 2841 #ifdef __BIG_ENDIAN_BITFIELD 2842 uint64_t reserved_32_63:32; 2843 uint64_t rodt_hi3:4; 2844 uint64_t rodt_hi2:4; 2845 uint64_t rodt_hi1:4; 2846 uint64_t rodt_hi0:4; 2847 uint64_t rodt_lo3:4; 2848 uint64_t rodt_lo2:4; 2849 uint64_t rodt_lo1:4; 2850 uint64_t rodt_lo0:4; 2851 #else 2852 uint64_t rodt_lo0:4; 2853 uint64_t rodt_lo1:4; 2854 uint64_t rodt_lo2:4; 2855 uint64_t rodt_lo3:4; 2856 uint64_t rodt_hi0:4; 2857 uint64_t rodt_hi1:4; 2858 uint64_t rodt_hi2:4; 2859 uint64_t rodt_hi3:4; 2860 uint64_t reserved_32_63:32; 2861 #endif 2862 } s; 2863 struct cvmx_lmcx_rodt_ctl_s cn30xx; 2864 struct cvmx_lmcx_rodt_ctl_s cn31xx; 2865 struct cvmx_lmcx_rodt_ctl_s cn38xx; 2866 struct cvmx_lmcx_rodt_ctl_s cn38xxp2; 2867 struct cvmx_lmcx_rodt_ctl_s cn50xx; 2868 struct cvmx_lmcx_rodt_ctl_s cn52xx; 2869 struct cvmx_lmcx_rodt_ctl_s cn52xxp1; 2870 struct cvmx_lmcx_rodt_ctl_s cn56xx; 2871 struct cvmx_lmcx_rodt_ctl_s cn56xxp1; 2872 struct cvmx_lmcx_rodt_ctl_s cn58xx; 2873 struct cvmx_lmcx_rodt_ctl_s cn58xxp1; 2874 }; 2875 2876 union cvmx_lmcx_rodt_mask { 2877 uint64_t u64; 2878 struct cvmx_lmcx_rodt_mask_s { 2879 #ifdef __BIG_ENDIAN_BITFIELD 2880 uint64_t rodt_d3_r1:8; 2881 uint64_t rodt_d3_r0:8; 2882 uint64_t rodt_d2_r1:8; 2883 uint64_t rodt_d2_r0:8; 2884 uint64_t rodt_d1_r1:8; 2885 uint64_t rodt_d1_r0:8; 2886 uint64_t rodt_d0_r1:8; 2887 uint64_t rodt_d0_r0:8; 2888 #else 2889 uint64_t rodt_d0_r0:8; 2890 uint64_t rodt_d0_r1:8; 2891 uint64_t rodt_d1_r0:8; 2892 uint64_t rodt_d1_r1:8; 2893 uint64_t rodt_d2_r0:8; 2894 uint64_t rodt_d2_r1:8; 2895 uint64_t rodt_d3_r0:8; 2896 uint64_t rodt_d3_r1:8; 2897 #endif 2898 } s; 2899 struct cvmx_lmcx_rodt_mask_s cn61xx; 2900 struct cvmx_lmcx_rodt_mask_s cn63xx; 2901 struct cvmx_lmcx_rodt_mask_s cn63xxp1; 2902 struct cvmx_lmcx_rodt_mask_s cn66xx; 2903 struct cvmx_lmcx_rodt_mask_s cn68xx; 2904 struct cvmx_lmcx_rodt_mask_s cn68xxp1; 2905 struct cvmx_lmcx_rodt_mask_s cnf71xx; 2906 }; 2907 2908 union cvmx_lmcx_scramble_cfg0 { 2909 uint64_t u64; 2910 struct cvmx_lmcx_scramble_cfg0_s { 2911 #ifdef __BIG_ENDIAN_BITFIELD 2912 uint64_t key:64; 2913 #else 2914 uint64_t key:64; 2915 #endif 2916 } s; 2917 struct cvmx_lmcx_scramble_cfg0_s cn61xx; 2918 struct cvmx_lmcx_scramble_cfg0_s cn66xx; 2919 struct cvmx_lmcx_scramble_cfg0_s cnf71xx; 2920 }; 2921 2922 union cvmx_lmcx_scramble_cfg1 { 2923 uint64_t u64; 2924 struct cvmx_lmcx_scramble_cfg1_s { 2925 #ifdef __BIG_ENDIAN_BITFIELD 2926 uint64_t key:64; 2927 #else 2928 uint64_t key:64; 2929 #endif 2930 } s; 2931 struct cvmx_lmcx_scramble_cfg1_s cn61xx; 2932 struct cvmx_lmcx_scramble_cfg1_s cn66xx; 2933 struct cvmx_lmcx_scramble_cfg1_s cnf71xx; 2934 }; 2935 2936 union cvmx_lmcx_scrambled_fadr { 2937 uint64_t u64; 2938 struct cvmx_lmcx_scrambled_fadr_s { 2939 #ifdef __BIG_ENDIAN_BITFIELD 2940 uint64_t reserved_36_63:28; 2941 uint64_t fdimm:2; 2942 uint64_t fbunk:1; 2943 uint64_t fbank:3; 2944 uint64_t frow:16; 2945 uint64_t fcol:14; 2946 #else 2947 uint64_t fcol:14; 2948 uint64_t frow:16; 2949 uint64_t fbank:3; 2950 uint64_t fbunk:1; 2951 uint64_t fdimm:2; 2952 uint64_t reserved_36_63:28; 2953 #endif 2954 } s; 2955 struct cvmx_lmcx_scrambled_fadr_s cn61xx; 2956 struct cvmx_lmcx_scrambled_fadr_s cn66xx; 2957 struct cvmx_lmcx_scrambled_fadr_s cnf71xx; 2958 }; 2959 2960 union cvmx_lmcx_slot_ctl0 { 2961 uint64_t u64; 2962 struct cvmx_lmcx_slot_ctl0_s { 2963 #ifdef __BIG_ENDIAN_BITFIELD 2964 uint64_t reserved_24_63:40; 2965 uint64_t w2w_init:6; 2966 uint64_t w2r_init:6; 2967 uint64_t r2w_init:6; 2968 uint64_t r2r_init:6; 2969 #else 2970 uint64_t r2r_init:6; 2971 uint64_t r2w_init:6; 2972 uint64_t w2r_init:6; 2973 uint64_t w2w_init:6; 2974 uint64_t reserved_24_63:40; 2975 #endif 2976 } s; 2977 struct cvmx_lmcx_slot_ctl0_s cn61xx; 2978 struct cvmx_lmcx_slot_ctl0_s cn63xx; 2979 struct cvmx_lmcx_slot_ctl0_s cn63xxp1; 2980 struct cvmx_lmcx_slot_ctl0_s cn66xx; 2981 struct cvmx_lmcx_slot_ctl0_s cn68xx; 2982 struct cvmx_lmcx_slot_ctl0_s cn68xxp1; 2983 struct cvmx_lmcx_slot_ctl0_s cnf71xx; 2984 }; 2985 2986 union cvmx_lmcx_slot_ctl1 { 2987 uint64_t u64; 2988 struct cvmx_lmcx_slot_ctl1_s { 2989 #ifdef __BIG_ENDIAN_BITFIELD 2990 uint64_t reserved_24_63:40; 2991 uint64_t w2w_xrank_init:6; 2992 uint64_t w2r_xrank_init:6; 2993 uint64_t r2w_xrank_init:6; 2994 uint64_t r2r_xrank_init:6; 2995 #else 2996 uint64_t r2r_xrank_init:6; 2997 uint64_t r2w_xrank_init:6; 2998 uint64_t w2r_xrank_init:6; 2999 uint64_t w2w_xrank_init:6; 3000 uint64_t reserved_24_63:40; 3001 #endif 3002 } s; 3003 struct cvmx_lmcx_slot_ctl1_s cn61xx; 3004 struct cvmx_lmcx_slot_ctl1_s cn63xx; 3005 struct cvmx_lmcx_slot_ctl1_s cn63xxp1; 3006 struct cvmx_lmcx_slot_ctl1_s cn66xx; 3007 struct cvmx_lmcx_slot_ctl1_s cn68xx; 3008 struct cvmx_lmcx_slot_ctl1_s cn68xxp1; 3009 struct cvmx_lmcx_slot_ctl1_s cnf71xx; 3010 }; 3011 3012 union cvmx_lmcx_slot_ctl2 { 3013 uint64_t u64; 3014 struct cvmx_lmcx_slot_ctl2_s { 3015 #ifdef __BIG_ENDIAN_BITFIELD 3016 uint64_t reserved_24_63:40; 3017 uint64_t w2w_xdimm_init:6; 3018 uint64_t w2r_xdimm_init:6; 3019 uint64_t r2w_xdimm_init:6; 3020 uint64_t r2r_xdimm_init:6; 3021 #else 3022 uint64_t r2r_xdimm_init:6; 3023 uint64_t r2w_xdimm_init:6; 3024 uint64_t w2r_xdimm_init:6; 3025 uint64_t w2w_xdimm_init:6; 3026 uint64_t reserved_24_63:40; 3027 #endif 3028 } s; 3029 struct cvmx_lmcx_slot_ctl2_s cn61xx; 3030 struct cvmx_lmcx_slot_ctl2_s cn63xx; 3031 struct cvmx_lmcx_slot_ctl2_s cn63xxp1; 3032 struct cvmx_lmcx_slot_ctl2_s cn66xx; 3033 struct cvmx_lmcx_slot_ctl2_s cn68xx; 3034 struct cvmx_lmcx_slot_ctl2_s cn68xxp1; 3035 struct cvmx_lmcx_slot_ctl2_s cnf71xx; 3036 }; 3037 3038 union cvmx_lmcx_timing_params0 { 3039 uint64_t u64; 3040 struct cvmx_lmcx_timing_params0_s { 3041 #ifdef __BIG_ENDIAN_BITFIELD 3042 uint64_t reserved_47_63:17; 3043 uint64_t trp_ext:1; 3044 uint64_t tcksre:4; 3045 uint64_t trp:4; 3046 uint64_t tzqinit:4; 3047 uint64_t tdllk:4; 3048 uint64_t tmod:4; 3049 uint64_t tmrd:4; 3050 uint64_t txpr:4; 3051 uint64_t tcke:4; 3052 uint64_t tzqcs:4; 3053 uint64_t tckeon:10; 3054 #else 3055 uint64_t tckeon:10; 3056 uint64_t tzqcs:4; 3057 uint64_t tcke:4; 3058 uint64_t txpr:4; 3059 uint64_t tmrd:4; 3060 uint64_t tmod:4; 3061 uint64_t tdllk:4; 3062 uint64_t tzqinit:4; 3063 uint64_t trp:4; 3064 uint64_t tcksre:4; 3065 uint64_t trp_ext:1; 3066 uint64_t reserved_47_63:17; 3067 #endif 3068 } s; 3069 struct cvmx_lmcx_timing_params0_cn61xx { 3070 #ifdef __BIG_ENDIAN_BITFIELD 3071 uint64_t reserved_47_63:17; 3072 uint64_t trp_ext:1; 3073 uint64_t tcksre:4; 3074 uint64_t trp:4; 3075 uint64_t tzqinit:4; 3076 uint64_t tdllk:4; 3077 uint64_t tmod:4; 3078 uint64_t tmrd:4; 3079 uint64_t txpr:4; 3080 uint64_t tcke:4; 3081 uint64_t tzqcs:4; 3082 uint64_t reserved_0_9:10; 3083 #else 3084 uint64_t reserved_0_9:10; 3085 uint64_t tzqcs:4; 3086 uint64_t tcke:4; 3087 uint64_t txpr:4; 3088 uint64_t tmrd:4; 3089 uint64_t tmod:4; 3090 uint64_t tdllk:4; 3091 uint64_t tzqinit:4; 3092 uint64_t trp:4; 3093 uint64_t tcksre:4; 3094 uint64_t trp_ext:1; 3095 uint64_t reserved_47_63:17; 3096 #endif 3097 } cn61xx; 3098 struct cvmx_lmcx_timing_params0_cn61xx cn63xx; 3099 struct cvmx_lmcx_timing_params0_cn63xxp1 { 3100 #ifdef __BIG_ENDIAN_BITFIELD 3101 uint64_t reserved_46_63:18; 3102 uint64_t tcksre:4; 3103 uint64_t trp:4; 3104 uint64_t tzqinit:4; 3105 uint64_t tdllk:4; 3106 uint64_t tmod:4; 3107 uint64_t tmrd:4; 3108 uint64_t txpr:4; 3109 uint64_t tcke:4; 3110 uint64_t tzqcs:4; 3111 uint64_t tckeon:10; 3112 #else 3113 uint64_t tckeon:10; 3114 uint64_t tzqcs:4; 3115 uint64_t tcke:4; 3116 uint64_t txpr:4; 3117 uint64_t tmrd:4; 3118 uint64_t tmod:4; 3119 uint64_t tdllk:4; 3120 uint64_t tzqinit:4; 3121 uint64_t trp:4; 3122 uint64_t tcksre:4; 3123 uint64_t reserved_46_63:18; 3124 #endif 3125 } cn63xxp1; 3126 struct cvmx_lmcx_timing_params0_cn61xx cn66xx; 3127 struct cvmx_lmcx_timing_params0_cn61xx cn68xx; 3128 struct cvmx_lmcx_timing_params0_cn61xx cn68xxp1; 3129 struct cvmx_lmcx_timing_params0_cn61xx cnf71xx; 3130 }; 3131 3132 union cvmx_lmcx_timing_params1 { 3133 uint64_t u64; 3134 struct cvmx_lmcx_timing_params1_s { 3135 #ifdef __BIG_ENDIAN_BITFIELD 3136 uint64_t reserved_47_63:17; 3137 uint64_t tras_ext:1; 3138 uint64_t txpdll:5; 3139 uint64_t tfaw:5; 3140 uint64_t twldqsen:4; 3141 uint64_t twlmrd:4; 3142 uint64_t txp:3; 3143 uint64_t trrd:3; 3144 uint64_t trfc:5; 3145 uint64_t twtr:4; 3146 uint64_t trcd:4; 3147 uint64_t tras:5; 3148 uint64_t tmprr:4; 3149 #else 3150 uint64_t tmprr:4; 3151 uint64_t tras:5; 3152 uint64_t trcd:4; 3153 uint64_t twtr:4; 3154 uint64_t trfc:5; 3155 uint64_t trrd:3; 3156 uint64_t txp:3; 3157 uint64_t twlmrd:4; 3158 uint64_t twldqsen:4; 3159 uint64_t tfaw:5; 3160 uint64_t txpdll:5; 3161 uint64_t tras_ext:1; 3162 uint64_t reserved_47_63:17; 3163 #endif 3164 } s; 3165 struct cvmx_lmcx_timing_params1_s cn61xx; 3166 struct cvmx_lmcx_timing_params1_s cn63xx; 3167 struct cvmx_lmcx_timing_params1_cn63xxp1 { 3168 #ifdef __BIG_ENDIAN_BITFIELD 3169 uint64_t reserved_46_63:18; 3170 uint64_t txpdll:5; 3171 uint64_t tfaw:5; 3172 uint64_t twldqsen:4; 3173 uint64_t twlmrd:4; 3174 uint64_t txp:3; 3175 uint64_t trrd:3; 3176 uint64_t trfc:5; 3177 uint64_t twtr:4; 3178 uint64_t trcd:4; 3179 uint64_t tras:5; 3180 uint64_t tmprr:4; 3181 #else 3182 uint64_t tmprr:4; 3183 uint64_t tras:5; 3184 uint64_t trcd:4; 3185 uint64_t twtr:4; 3186 uint64_t trfc:5; 3187 uint64_t trrd:3; 3188 uint64_t txp:3; 3189 uint64_t twlmrd:4; 3190 uint64_t twldqsen:4; 3191 uint64_t tfaw:5; 3192 uint64_t txpdll:5; 3193 uint64_t reserved_46_63:18; 3194 #endif 3195 } cn63xxp1; 3196 struct cvmx_lmcx_timing_params1_s cn66xx; 3197 struct cvmx_lmcx_timing_params1_s cn68xx; 3198 struct cvmx_lmcx_timing_params1_s cn68xxp1; 3199 struct cvmx_lmcx_timing_params1_s cnf71xx; 3200 }; 3201 3202 union cvmx_lmcx_tro_ctl { 3203 uint64_t u64; 3204 struct cvmx_lmcx_tro_ctl_s { 3205 #ifdef __BIG_ENDIAN_BITFIELD 3206 uint64_t reserved_33_63:31; 3207 uint64_t rclk_cnt:32; 3208 uint64_t treset:1; 3209 #else 3210 uint64_t treset:1; 3211 uint64_t rclk_cnt:32; 3212 uint64_t reserved_33_63:31; 3213 #endif 3214 } s; 3215 struct cvmx_lmcx_tro_ctl_s cn61xx; 3216 struct cvmx_lmcx_tro_ctl_s cn63xx; 3217 struct cvmx_lmcx_tro_ctl_s cn63xxp1; 3218 struct cvmx_lmcx_tro_ctl_s cn66xx; 3219 struct cvmx_lmcx_tro_ctl_s cn68xx; 3220 struct cvmx_lmcx_tro_ctl_s cn68xxp1; 3221 struct cvmx_lmcx_tro_ctl_s cnf71xx; 3222 }; 3223 3224 union cvmx_lmcx_tro_stat { 3225 uint64_t u64; 3226 struct cvmx_lmcx_tro_stat_s { 3227 #ifdef __BIG_ENDIAN_BITFIELD 3228 uint64_t reserved_32_63:32; 3229 uint64_t ring_cnt:32; 3230 #else 3231 uint64_t ring_cnt:32; 3232 uint64_t reserved_32_63:32; 3233 #endif 3234 } s; 3235 struct cvmx_lmcx_tro_stat_s cn61xx; 3236 struct cvmx_lmcx_tro_stat_s cn63xx; 3237 struct cvmx_lmcx_tro_stat_s cn63xxp1; 3238 struct cvmx_lmcx_tro_stat_s cn66xx; 3239 struct cvmx_lmcx_tro_stat_s cn68xx; 3240 struct cvmx_lmcx_tro_stat_s cn68xxp1; 3241 struct cvmx_lmcx_tro_stat_s cnf71xx; 3242 }; 3243 3244 union cvmx_lmcx_wlevel_ctl { 3245 uint64_t u64; 3246 struct cvmx_lmcx_wlevel_ctl_s { 3247 #ifdef __BIG_ENDIAN_BITFIELD 3248 uint64_t reserved_22_63:42; 3249 uint64_t rtt_nom:3; 3250 uint64_t bitmask:8; 3251 uint64_t or_dis:1; 3252 uint64_t sset:1; 3253 uint64_t lanemask:9; 3254 #else 3255 uint64_t lanemask:9; 3256 uint64_t sset:1; 3257 uint64_t or_dis:1; 3258 uint64_t bitmask:8; 3259 uint64_t rtt_nom:3; 3260 uint64_t reserved_22_63:42; 3261 #endif 3262 } s; 3263 struct cvmx_lmcx_wlevel_ctl_s cn61xx; 3264 struct cvmx_lmcx_wlevel_ctl_s cn63xx; 3265 struct cvmx_lmcx_wlevel_ctl_cn63xxp1 { 3266 #ifdef __BIG_ENDIAN_BITFIELD 3267 uint64_t reserved_10_63:54; 3268 uint64_t sset:1; 3269 uint64_t lanemask:9; 3270 #else 3271 uint64_t lanemask:9; 3272 uint64_t sset:1; 3273 uint64_t reserved_10_63:54; 3274 #endif 3275 } cn63xxp1; 3276 struct cvmx_lmcx_wlevel_ctl_s cn66xx; 3277 struct cvmx_lmcx_wlevel_ctl_s cn68xx; 3278 struct cvmx_lmcx_wlevel_ctl_s cn68xxp1; 3279 struct cvmx_lmcx_wlevel_ctl_s cnf71xx; 3280 }; 3281 3282 union cvmx_lmcx_wlevel_dbg { 3283 uint64_t u64; 3284 struct cvmx_lmcx_wlevel_dbg_s { 3285 #ifdef __BIG_ENDIAN_BITFIELD 3286 uint64_t reserved_12_63:52; 3287 uint64_t bitmask:8; 3288 uint64_t byte:4; 3289 #else 3290 uint64_t byte:4; 3291 uint64_t bitmask:8; 3292 uint64_t reserved_12_63:52; 3293 #endif 3294 } s; 3295 struct cvmx_lmcx_wlevel_dbg_s cn61xx; 3296 struct cvmx_lmcx_wlevel_dbg_s cn63xx; 3297 struct cvmx_lmcx_wlevel_dbg_s cn63xxp1; 3298 struct cvmx_lmcx_wlevel_dbg_s cn66xx; 3299 struct cvmx_lmcx_wlevel_dbg_s cn68xx; 3300 struct cvmx_lmcx_wlevel_dbg_s cn68xxp1; 3301 struct cvmx_lmcx_wlevel_dbg_s cnf71xx; 3302 }; 3303 3304 union cvmx_lmcx_wlevel_rankx { 3305 uint64_t u64; 3306 struct cvmx_lmcx_wlevel_rankx_s { 3307 #ifdef __BIG_ENDIAN_BITFIELD 3308 uint64_t reserved_47_63:17; 3309 uint64_t status:2; 3310 uint64_t byte8:5; 3311 uint64_t byte7:5; 3312 uint64_t byte6:5; 3313 uint64_t byte5:5; 3314 uint64_t byte4:5; 3315 uint64_t byte3:5; 3316 uint64_t byte2:5; 3317 uint64_t byte1:5; 3318 uint64_t byte0:5; 3319 #else 3320 uint64_t byte0:5; 3321 uint64_t byte1:5; 3322 uint64_t byte2:5; 3323 uint64_t byte3:5; 3324 uint64_t byte4:5; 3325 uint64_t byte5:5; 3326 uint64_t byte6:5; 3327 uint64_t byte7:5; 3328 uint64_t byte8:5; 3329 uint64_t status:2; 3330 uint64_t reserved_47_63:17; 3331 #endif 3332 } s; 3333 struct cvmx_lmcx_wlevel_rankx_s cn61xx; 3334 struct cvmx_lmcx_wlevel_rankx_s cn63xx; 3335 struct cvmx_lmcx_wlevel_rankx_s cn63xxp1; 3336 struct cvmx_lmcx_wlevel_rankx_s cn66xx; 3337 struct cvmx_lmcx_wlevel_rankx_s cn68xx; 3338 struct cvmx_lmcx_wlevel_rankx_s cn68xxp1; 3339 struct cvmx_lmcx_wlevel_rankx_s cnf71xx; 3340 }; 3341 3342 union cvmx_lmcx_wodt_ctl0 { 3343 uint64_t u64; 3344 struct cvmx_lmcx_wodt_ctl0_s { 3345 #ifdef __BIG_ENDIAN_BITFIELD 3346 uint64_t reserved_0_63:64; 3347 #else 3348 uint64_t reserved_0_63:64; 3349 #endif 3350 } s; 3351 struct cvmx_lmcx_wodt_ctl0_cn30xx { 3352 #ifdef __BIG_ENDIAN_BITFIELD 3353 uint64_t reserved_32_63:32; 3354 uint64_t wodt_d1_r1:8; 3355 uint64_t wodt_d1_r0:8; 3356 uint64_t wodt_d0_r1:8; 3357 uint64_t wodt_d0_r0:8; 3358 #else 3359 uint64_t wodt_d0_r0:8; 3360 uint64_t wodt_d0_r1:8; 3361 uint64_t wodt_d1_r0:8; 3362 uint64_t wodt_d1_r1:8; 3363 uint64_t reserved_32_63:32; 3364 #endif 3365 } cn30xx; 3366 struct cvmx_lmcx_wodt_ctl0_cn30xx cn31xx; 3367 struct cvmx_lmcx_wodt_ctl0_cn38xx { 3368 #ifdef __BIG_ENDIAN_BITFIELD 3369 uint64_t reserved_32_63:32; 3370 uint64_t wodt_hi3:4; 3371 uint64_t wodt_hi2:4; 3372 uint64_t wodt_hi1:4; 3373 uint64_t wodt_hi0:4; 3374 uint64_t wodt_lo3:4; 3375 uint64_t wodt_lo2:4; 3376 uint64_t wodt_lo1:4; 3377 uint64_t wodt_lo0:4; 3378 #else 3379 uint64_t wodt_lo0:4; 3380 uint64_t wodt_lo1:4; 3381 uint64_t wodt_lo2:4; 3382 uint64_t wodt_lo3:4; 3383 uint64_t wodt_hi0:4; 3384 uint64_t wodt_hi1:4; 3385 uint64_t wodt_hi2:4; 3386 uint64_t wodt_hi3:4; 3387 uint64_t reserved_32_63:32; 3388 #endif 3389 } cn38xx; 3390 struct cvmx_lmcx_wodt_ctl0_cn38xx cn38xxp2; 3391 struct cvmx_lmcx_wodt_ctl0_cn38xx cn50xx; 3392 struct cvmx_lmcx_wodt_ctl0_cn30xx cn52xx; 3393 struct cvmx_lmcx_wodt_ctl0_cn30xx cn52xxp1; 3394 struct cvmx_lmcx_wodt_ctl0_cn30xx cn56xx; 3395 struct cvmx_lmcx_wodt_ctl0_cn30xx cn56xxp1; 3396 struct cvmx_lmcx_wodt_ctl0_cn38xx cn58xx; 3397 struct cvmx_lmcx_wodt_ctl0_cn38xx cn58xxp1; 3398 }; 3399 3400 union cvmx_lmcx_wodt_ctl1 { 3401 uint64_t u64; 3402 struct cvmx_lmcx_wodt_ctl1_s { 3403 #ifdef __BIG_ENDIAN_BITFIELD 3404 uint64_t reserved_32_63:32; 3405 uint64_t wodt_d3_r1:8; 3406 uint64_t wodt_d3_r0:8; 3407 uint64_t wodt_d2_r1:8; 3408 uint64_t wodt_d2_r0:8; 3409 #else 3410 uint64_t wodt_d2_r0:8; 3411 uint64_t wodt_d2_r1:8; 3412 uint64_t wodt_d3_r0:8; 3413 uint64_t wodt_d3_r1:8; 3414 uint64_t reserved_32_63:32; 3415 #endif 3416 } s; 3417 struct cvmx_lmcx_wodt_ctl1_s cn30xx; 3418 struct cvmx_lmcx_wodt_ctl1_s cn31xx; 3419 struct cvmx_lmcx_wodt_ctl1_s cn52xx; 3420 struct cvmx_lmcx_wodt_ctl1_s cn52xxp1; 3421 struct cvmx_lmcx_wodt_ctl1_s cn56xx; 3422 struct cvmx_lmcx_wodt_ctl1_s cn56xxp1; 3423 }; 3424 3425 union cvmx_lmcx_wodt_mask { 3426 uint64_t u64; 3427 struct cvmx_lmcx_wodt_mask_s { 3428 #ifdef __BIG_ENDIAN_BITFIELD 3429 uint64_t wodt_d3_r1:8; 3430 uint64_t wodt_d3_r0:8; 3431 uint64_t wodt_d2_r1:8; 3432 uint64_t wodt_d2_r0:8; 3433 uint64_t wodt_d1_r1:8; 3434 uint64_t wodt_d1_r0:8; 3435 uint64_t wodt_d0_r1:8; 3436 uint64_t wodt_d0_r0:8; 3437 #else 3438 uint64_t wodt_d0_r0:8; 3439 uint64_t wodt_d0_r1:8; 3440 uint64_t wodt_d1_r0:8; 3441 uint64_t wodt_d1_r1:8; 3442 uint64_t wodt_d2_r0:8; 3443 uint64_t wodt_d2_r1:8; 3444 uint64_t wodt_d3_r0:8; 3445 uint64_t wodt_d3_r1:8; 3446 #endif 3447 } s; 3448 struct cvmx_lmcx_wodt_mask_s cn61xx; 3449 struct cvmx_lmcx_wodt_mask_s cn63xx; 3450 struct cvmx_lmcx_wodt_mask_s cn63xxp1; 3451 struct cvmx_lmcx_wodt_mask_s cn66xx; 3452 struct cvmx_lmcx_wodt_mask_s cn68xx; 3453 struct cvmx_lmcx_wodt_mask_s cn68xxp1; 3454 struct cvmx_lmcx_wodt_mask_s cnf71xx; 3455 }; 3456 3457 #endif 3458