1 /* 2 * Switch a MMU context. 3 * 4 * This file is subject to the terms and conditions of the GNU General Public 5 * License. See the file "COPYING" in the main directory of this archive 6 * for more details. 7 * 8 * Copyright (C) 1996, 1997, 1998, 1999 by Ralf Baechle 9 * Copyright (C) 1999 Silicon Graphics, Inc. 10 */ 11 #ifndef _ASM_MMU_CONTEXT_H 12 #define _ASM_MMU_CONTEXT_H 13 14 #include <linux/errno.h> 15 #include <linux/sched.h> 16 #include <linux/smp.h> 17 #include <linux/slab.h> 18 #include <asm/cacheflush.h> 19 #include <asm/hazards.h> 20 #include <asm/tlbflush.h> 21 #ifdef CONFIG_MIPS_MT_SMTC 22 #include <asm/mipsmtregs.h> 23 #include <asm/smtc.h> 24 #endif /* SMTC */ 25 #include <asm-generic/mm_hooks.h> 26 27 #define TLBMISS_HANDLER_SETUP_PGD(pgd) \ 28 do { \ 29 extern void tlbmiss_handler_setup_pgd(unsigned long); \ 30 tlbmiss_handler_setup_pgd((unsigned long)(pgd)); \ 31 } while (0) 32 33 #ifdef CONFIG_MIPS_PGD_C0_CONTEXT 34 #define TLBMISS_HANDLER_SETUP() \ 35 do { \ 36 TLBMISS_HANDLER_SETUP_PGD(swapper_pg_dir); \ 37 write_c0_xcontext((unsigned long) smp_processor_id() << \ 38 SMP_CPUID_REGSHIFT); \ 39 } while (0) 40 41 #else /* !CONFIG_MIPS_PGD_C0_CONTEXT: using pgd_current*/ 42 43 /* 44 * For the fast tlb miss handlers, we keep a per cpu array of pointers 45 * to the current pgd for each processor. Also, the proc. id is stuffed 46 * into the context register. 47 */ 48 extern unsigned long pgd_current[]; 49 50 #define TLBMISS_HANDLER_SETUP() \ 51 write_c0_context((unsigned long) smp_processor_id() << \ 52 SMP_CPUID_REGSHIFT); \ 53 back_to_back_c0_hazard(); \ 54 TLBMISS_HANDLER_SETUP_PGD(swapper_pg_dir) 55 #endif /* CONFIG_MIPS_PGD_C0_CONTEXT*/ 56 #if defined(CONFIG_CPU_R3000) || defined(CONFIG_CPU_TX39XX) 57 58 #define ASID_INC 0x40 59 #define ASID_MASK 0xfc0 60 61 #elif defined(CONFIG_CPU_R8000) 62 63 #define ASID_INC 0x10 64 #define ASID_MASK 0xff0 65 66 #elif defined(CONFIG_MIPS_MT_SMTC) 67 68 #define ASID_INC 0x1 69 extern unsigned long smtc_asid_mask; 70 #define ASID_MASK (smtc_asid_mask) 71 #define HW_ASID_MASK 0xff 72 /* End SMTC/34K debug hack */ 73 #else /* FIXME: not correct for R6000 */ 74 75 #define ASID_INC 0x1 76 #define ASID_MASK 0xff 77 78 #endif 79 80 #define cpu_context(cpu, mm) ((mm)->context.asid[cpu]) 81 #define cpu_asid(cpu, mm) (cpu_context((cpu), (mm)) & ASID_MASK) 82 #define asid_cache(cpu) (cpu_data[cpu].asid_cache) 83 84 static inline void enter_lazy_tlb(struct mm_struct *mm, struct task_struct *tsk) 85 { 86 } 87 88 /* 89 * All unused by hardware upper bits will be considered 90 * as a software asid extension. 91 */ 92 #define ASID_VERSION_MASK ((unsigned long)~(ASID_MASK|(ASID_MASK-1))) 93 #define ASID_FIRST_VERSION ((unsigned long)(~ASID_VERSION_MASK) + 1) 94 95 #ifndef CONFIG_MIPS_MT_SMTC 96 /* Normal, classic MIPS get_new_mmu_context */ 97 static inline void 98 get_new_mmu_context(struct mm_struct *mm, unsigned long cpu) 99 { 100 extern void kvm_local_flush_tlb_all(void); 101 unsigned long asid = asid_cache(cpu); 102 103 if (! ((asid += ASID_INC) & ASID_MASK) ) { 104 if (cpu_has_vtag_icache) 105 flush_icache_all(); 106 #ifdef CONFIG_KVM 107 kvm_local_flush_tlb_all(); /* start new asid cycle */ 108 #else 109 local_flush_tlb_all(); /* start new asid cycle */ 110 #endif 111 if (!asid) /* fix version if needed */ 112 asid = ASID_FIRST_VERSION; 113 } 114 115 cpu_context(cpu, mm) = asid_cache(cpu) = asid; 116 } 117 118 #else /* CONFIG_MIPS_MT_SMTC */ 119 120 #define get_new_mmu_context(mm, cpu) smtc_get_new_mmu_context((mm), (cpu)) 121 122 #endif /* CONFIG_MIPS_MT_SMTC */ 123 124 /* 125 * Initialize the context related info for a new mm_struct 126 * instance. 127 */ 128 static inline int 129 init_new_context(struct task_struct *tsk, struct mm_struct *mm) 130 { 131 int i; 132 133 for_each_possible_cpu(i) 134 cpu_context(i, mm) = 0; 135 136 return 0; 137 } 138 139 static inline void switch_mm(struct mm_struct *prev, struct mm_struct *next, 140 struct task_struct *tsk) 141 { 142 unsigned int cpu = smp_processor_id(); 143 unsigned long flags; 144 #ifdef CONFIG_MIPS_MT_SMTC 145 unsigned long oldasid; 146 unsigned long mtflags; 147 int mytlb = (smtc_status & SMTC_TLB_SHARED) ? 0 : cpu_data[cpu].vpe_id; 148 local_irq_save(flags); 149 mtflags = dvpe(); 150 #else /* Not SMTC */ 151 local_irq_save(flags); 152 #endif /* CONFIG_MIPS_MT_SMTC */ 153 154 /* Check if our ASID is of an older version and thus invalid */ 155 if ((cpu_context(cpu, next) ^ asid_cache(cpu)) & ASID_VERSION_MASK) 156 get_new_mmu_context(next, cpu); 157 #ifdef CONFIG_MIPS_MT_SMTC 158 /* 159 * If the EntryHi ASID being replaced happens to be 160 * the value flagged at ASID recycling time as having 161 * an extended life, clear the bit showing it being 162 * in use by this "CPU", and if that's the last bit, 163 * free up the ASID value for use and flush any old 164 * instances of it from the TLB. 165 */ 166 oldasid = (read_c0_entryhi() & ASID_MASK); 167 if(smtc_live_asid[mytlb][oldasid]) { 168 smtc_live_asid[mytlb][oldasid] &= ~(0x1 << cpu); 169 if(smtc_live_asid[mytlb][oldasid] == 0) 170 smtc_flush_tlb_asid(oldasid); 171 } 172 /* 173 * Tread softly on EntryHi, and so long as we support 174 * having ASID_MASK smaller than the hardware maximum, 175 * make sure no "soft" bits become "hard"... 176 */ 177 write_c0_entryhi((read_c0_entryhi() & ~HW_ASID_MASK) | 178 cpu_asid(cpu, next)); 179 ehb(); /* Make sure it propagates to TCStatus */ 180 evpe(mtflags); 181 #else 182 write_c0_entryhi(cpu_asid(cpu, next)); 183 #endif /* CONFIG_MIPS_MT_SMTC */ 184 TLBMISS_HANDLER_SETUP_PGD(next->pgd); 185 186 /* 187 * Mark current->active_mm as not "active" anymore. 188 * We don't want to mislead possible IPI tlb flush routines. 189 */ 190 cpumask_clear_cpu(cpu, mm_cpumask(prev)); 191 cpumask_set_cpu(cpu, mm_cpumask(next)); 192 193 local_irq_restore(flags); 194 } 195 196 /* 197 * Destroy context related info for an mm_struct that is about 198 * to be put to rest. 199 */ 200 static inline void destroy_context(struct mm_struct *mm) 201 { 202 } 203 204 #define deactivate_mm(tsk, mm) do { } while (0) 205 206 /* 207 * After we have set current->mm to a new value, this activates 208 * the context for the new mm so we see the new mappings. 209 */ 210 static inline void 211 activate_mm(struct mm_struct *prev, struct mm_struct *next) 212 { 213 unsigned long flags; 214 unsigned int cpu = smp_processor_id(); 215 216 #ifdef CONFIG_MIPS_MT_SMTC 217 unsigned long oldasid; 218 unsigned long mtflags; 219 int mytlb = (smtc_status & SMTC_TLB_SHARED) ? 0 : cpu_data[cpu].vpe_id; 220 #endif /* CONFIG_MIPS_MT_SMTC */ 221 222 local_irq_save(flags); 223 224 /* Unconditionally get a new ASID. */ 225 get_new_mmu_context(next, cpu); 226 227 #ifdef CONFIG_MIPS_MT_SMTC 228 /* See comments for similar code above */ 229 mtflags = dvpe(); 230 oldasid = read_c0_entryhi() & ASID_MASK; 231 if(smtc_live_asid[mytlb][oldasid]) { 232 smtc_live_asid[mytlb][oldasid] &= ~(0x1 << cpu); 233 if(smtc_live_asid[mytlb][oldasid] == 0) 234 smtc_flush_tlb_asid(oldasid); 235 } 236 /* See comments for similar code above */ 237 write_c0_entryhi((read_c0_entryhi() & ~HW_ASID_MASK) | 238 cpu_asid(cpu, next)); 239 ehb(); /* Make sure it propagates to TCStatus */ 240 evpe(mtflags); 241 #else 242 write_c0_entryhi(cpu_asid(cpu, next)); 243 #endif /* CONFIG_MIPS_MT_SMTC */ 244 TLBMISS_HANDLER_SETUP_PGD(next->pgd); 245 246 /* mark mmu ownership change */ 247 cpumask_clear_cpu(cpu, mm_cpumask(prev)); 248 cpumask_set_cpu(cpu, mm_cpumask(next)); 249 250 local_irq_restore(flags); 251 } 252 253 /* 254 * If mm is currently active_mm, we can't really drop it. Instead, 255 * we will get a new one for it. 256 */ 257 static inline void 258 drop_mmu_context(struct mm_struct *mm, unsigned cpu) 259 { 260 unsigned long flags; 261 #ifdef CONFIG_MIPS_MT_SMTC 262 unsigned long oldasid; 263 /* Can't use spinlock because called from TLB flush within DVPE */ 264 unsigned int prevvpe; 265 int mytlb = (smtc_status & SMTC_TLB_SHARED) ? 0 : cpu_data[cpu].vpe_id; 266 #endif /* CONFIG_MIPS_MT_SMTC */ 267 268 local_irq_save(flags); 269 270 if (cpumask_test_cpu(cpu, mm_cpumask(mm))) { 271 get_new_mmu_context(mm, cpu); 272 #ifdef CONFIG_MIPS_MT_SMTC 273 /* See comments for similar code above */ 274 prevvpe = dvpe(); 275 oldasid = (read_c0_entryhi() & ASID_MASK); 276 if (smtc_live_asid[mytlb][oldasid]) { 277 smtc_live_asid[mytlb][oldasid] &= ~(0x1 << cpu); 278 if(smtc_live_asid[mytlb][oldasid] == 0) 279 smtc_flush_tlb_asid(oldasid); 280 } 281 /* See comments for similar code above */ 282 write_c0_entryhi((read_c0_entryhi() & ~HW_ASID_MASK) 283 | cpu_asid(cpu, mm)); 284 ehb(); /* Make sure it propagates to TCStatus */ 285 evpe(prevvpe); 286 #else /* not CONFIG_MIPS_MT_SMTC */ 287 write_c0_entryhi(cpu_asid(cpu, mm)); 288 #endif /* CONFIG_MIPS_MT_SMTC */ 289 } else { 290 /* will get a new context next time */ 291 #ifndef CONFIG_MIPS_MT_SMTC 292 cpu_context(cpu, mm) = 0; 293 #else /* SMTC */ 294 int i; 295 296 /* SMTC shares the TLB (and ASIDs) across VPEs */ 297 for_each_online_cpu(i) { 298 if((smtc_status & SMTC_TLB_SHARED) 299 || (cpu_data[i].vpe_id == cpu_data[cpu].vpe_id)) 300 cpu_context(i, mm) = 0; 301 } 302 #endif /* CONFIG_MIPS_MT_SMTC */ 303 } 304 local_irq_restore(flags); 305 } 306 307 #endif /* _ASM_MMU_CONTEXT_H */ 308