1 /* 2 * Switch a MMU context. 3 * 4 * This file is subject to the terms and conditions of the GNU General Public 5 * License. See the file "COPYING" in the main directory of this archive 6 * for more details. 7 * 8 * Copyright (C) 1996, 1997, 1998, 1999 by Ralf Baechle 9 * Copyright (C) 1999 Silicon Graphics, Inc. 10 */ 11 #ifndef _ASM_MMU_CONTEXT_H 12 #define _ASM_MMU_CONTEXT_H 13 14 #include <linux/errno.h> 15 #include <linux/sched.h> 16 #include <linux/mm_types.h> 17 #include <linux/smp.h> 18 #include <linux/slab.h> 19 20 #include <asm/barrier.h> 21 #include <asm/cacheflush.h> 22 #include <asm/dsemul.h> 23 #include <asm/ginvt.h> 24 #include <asm/hazards.h> 25 #include <asm/tlbflush.h> 26 #include <asm-generic/mm_hooks.h> 27 28 #define htw_set_pwbase(pgd) \ 29 do { \ 30 if (cpu_has_htw) { \ 31 write_c0_pwbase(pgd); \ 32 back_to_back_c0_hazard(); \ 33 } \ 34 } while (0) 35 36 extern void tlbmiss_handler_setup_pgd(unsigned long); 37 extern char tlbmiss_handler_setup_pgd_end[]; 38 39 /* Note: This is also implemented with uasm in arch/mips/kvm/entry.c */ 40 #define TLBMISS_HANDLER_SETUP_PGD(pgd) \ 41 do { \ 42 tlbmiss_handler_setup_pgd((unsigned long)(pgd)); \ 43 htw_set_pwbase((unsigned long)pgd); \ 44 } while (0) 45 46 #ifdef CONFIG_MIPS_PGD_C0_CONTEXT 47 48 #define TLBMISS_HANDLER_RESTORE() \ 49 write_c0_xcontext((unsigned long) smp_processor_id() << \ 50 SMP_CPUID_REGSHIFT) 51 52 #define TLBMISS_HANDLER_SETUP() \ 53 do { \ 54 TLBMISS_HANDLER_SETUP_PGD(swapper_pg_dir); \ 55 TLBMISS_HANDLER_RESTORE(); \ 56 } while (0) 57 58 #else /* !CONFIG_MIPS_PGD_C0_CONTEXT: using pgd_current*/ 59 60 /* 61 * For the fast tlb miss handlers, we keep a per cpu array of pointers 62 * to the current pgd for each processor. Also, the proc. id is stuffed 63 * into the context register. 64 */ 65 extern unsigned long pgd_current[]; 66 67 #define TLBMISS_HANDLER_RESTORE() \ 68 write_c0_context((unsigned long) smp_processor_id() << \ 69 SMP_CPUID_REGSHIFT) 70 71 #define TLBMISS_HANDLER_SETUP() \ 72 TLBMISS_HANDLER_RESTORE(); \ 73 back_to_back_c0_hazard(); \ 74 TLBMISS_HANDLER_SETUP_PGD(swapper_pg_dir) 75 #endif /* CONFIG_MIPS_PGD_C0_CONTEXT*/ 76 77 /* 78 * The ginvt instruction will invalidate wired entries when its type field 79 * targets anything other than the entire TLB. That means that if we were to 80 * allow the kernel to create wired entries with the MMID of current->active_mm 81 * then those wired entries could be invalidated when we later use ginvt to 82 * invalidate TLB entries with that MMID. 83 * 84 * In order to prevent ginvt from trashing wired entries, we reserve one MMID 85 * for use by the kernel when creating wired entries. This MMID will never be 86 * assigned to a struct mm, and we'll never target it with a ginvt instruction. 87 */ 88 #define MMID_KERNEL_WIRED 0 89 90 /* 91 * All unused by hardware upper bits will be considered 92 * as a software asid extension. 93 */ 94 static inline u64 asid_version_mask(unsigned int cpu) 95 { 96 unsigned long asid_mask = cpu_asid_mask(&cpu_data[cpu]); 97 98 return ~(u64)(asid_mask | (asid_mask - 1)); 99 } 100 101 static inline u64 asid_first_version(unsigned int cpu) 102 { 103 return ~asid_version_mask(cpu) + 1; 104 } 105 106 static inline u64 cpu_context(unsigned int cpu, const struct mm_struct *mm) 107 { 108 if (cpu_has_mmid) 109 return atomic64_read(&mm->context.mmid); 110 111 return mm->context.asid[cpu]; 112 } 113 114 static inline void set_cpu_context(unsigned int cpu, 115 struct mm_struct *mm, u64 ctx) 116 { 117 if (cpu_has_mmid) 118 atomic64_set(&mm->context.mmid, ctx); 119 else 120 mm->context.asid[cpu] = ctx; 121 } 122 123 #define asid_cache(cpu) (cpu_data[cpu].asid_cache) 124 #define cpu_asid(cpu, mm) \ 125 (cpu_context((cpu), (mm)) & cpu_asid_mask(&cpu_data[cpu])) 126 127 static inline void enter_lazy_tlb(struct mm_struct *mm, struct task_struct *tsk) 128 { 129 } 130 131 extern void get_new_mmu_context(struct mm_struct *mm); 132 extern void check_mmu_context(struct mm_struct *mm); 133 extern void check_switch_mmu_context(struct mm_struct *mm); 134 135 /* 136 * Initialize the context related info for a new mm_struct 137 * instance. 138 */ 139 static inline int 140 init_new_context(struct task_struct *tsk, struct mm_struct *mm) 141 { 142 int i; 143 144 if (cpu_has_mmid) { 145 set_cpu_context(0, mm, 0); 146 } else { 147 for_each_possible_cpu(i) 148 set_cpu_context(i, mm, 0); 149 } 150 151 mm->context.bd_emupage_allocmap = NULL; 152 spin_lock_init(&mm->context.bd_emupage_lock); 153 init_waitqueue_head(&mm->context.bd_emupage_queue); 154 155 return 0; 156 } 157 158 static inline void switch_mm(struct mm_struct *prev, struct mm_struct *next, 159 struct task_struct *tsk) 160 { 161 unsigned int cpu = smp_processor_id(); 162 unsigned long flags; 163 local_irq_save(flags); 164 165 htw_stop(); 166 check_switch_mmu_context(next); 167 168 /* 169 * Mark current->active_mm as not "active" anymore. 170 * We don't want to mislead possible IPI tlb flush routines. 171 */ 172 cpumask_clear_cpu(cpu, mm_cpumask(prev)); 173 cpumask_set_cpu(cpu, mm_cpumask(next)); 174 htw_start(); 175 176 local_irq_restore(flags); 177 } 178 179 /* 180 * Destroy context related info for an mm_struct that is about 181 * to be put to rest. 182 */ 183 static inline void destroy_context(struct mm_struct *mm) 184 { 185 dsemul_mm_cleanup(mm); 186 } 187 188 #define activate_mm(prev, next) switch_mm(prev, next, current) 189 #define deactivate_mm(tsk, mm) do { } while (0) 190 191 static inline void 192 drop_mmu_context(struct mm_struct *mm) 193 { 194 unsigned long flags; 195 unsigned int cpu; 196 u32 old_mmid; 197 u64 ctx; 198 199 local_irq_save(flags); 200 201 cpu = smp_processor_id(); 202 ctx = cpu_context(cpu, mm); 203 204 if (!ctx) { 205 /* no-op */ 206 } else if (cpu_has_mmid) { 207 /* 208 * Globally invalidating TLB entries associated with the MMID 209 * is pretty cheap using the GINVT instruction, so we'll do 210 * that rather than incur the overhead of allocating a new 211 * MMID. The latter would be especially difficult since MMIDs 212 * are global & other CPUs may be actively using ctx. 213 */ 214 htw_stop(); 215 old_mmid = read_c0_memorymapid(); 216 write_c0_memorymapid(ctx & cpu_asid_mask(&cpu_data[cpu])); 217 mtc0_tlbw_hazard(); 218 ginvt_mmid(); 219 sync_ginv(); 220 write_c0_memorymapid(old_mmid); 221 instruction_hazard(); 222 htw_start(); 223 } else if (cpumask_test_cpu(cpu, mm_cpumask(mm))) { 224 /* 225 * mm is currently active, so we can't really drop it. 226 * Instead we bump the ASID. 227 */ 228 htw_stop(); 229 get_new_mmu_context(mm); 230 write_c0_entryhi(cpu_asid(cpu, mm)); 231 htw_start(); 232 } else { 233 /* will get a new context next time */ 234 set_cpu_context(cpu, mm, 0); 235 } 236 237 local_irq_restore(flags); 238 } 239 240 #endif /* _ASM_MMU_CONTEXT_H */ 241