1 /* 2 * Switch a MMU context. 3 * 4 * This file is subject to the terms and conditions of the GNU General Public 5 * License. See the file "COPYING" in the main directory of this archive 6 * for more details. 7 * 8 * Copyright (C) 1996, 1997, 1998, 1999 by Ralf Baechle 9 * Copyright (C) 1999 Silicon Graphics, Inc. 10 */ 11 #ifndef _ASM_MMU_CONTEXT_H 12 #define _ASM_MMU_CONTEXT_H 13 14 #include <linux/errno.h> 15 #include <linux/sched.h> 16 #include <linux/smp.h> 17 #include <linux/slab.h> 18 #include <asm/cacheflush.h> 19 #include <asm/hazards.h> 20 #include <asm/tlbflush.h> 21 #ifdef CONFIG_MIPS_MT_SMTC 22 #include <asm/mipsmtregs.h> 23 #include <asm/smtc.h> 24 #endif /* SMTC */ 25 #include <asm-generic/mm_hooks.h> 26 27 /* 28 * For the fast tlb miss handlers, we keep a per cpu array of pointers 29 * to the current pgd for each processor. Also, the proc. id is stuffed 30 * into the context register. 31 */ 32 extern unsigned long pgd_current[]; 33 34 #define TLBMISS_HANDLER_SETUP_PGD(pgd) \ 35 pgd_current[smp_processor_id()] = (unsigned long)(pgd) 36 37 #ifdef CONFIG_32BIT 38 #define TLBMISS_HANDLER_SETUP() \ 39 write_c0_context((unsigned long) smp_processor_id() << 25); \ 40 back_to_back_c0_hazard(); \ 41 TLBMISS_HANDLER_SETUP_PGD(swapper_pg_dir) 42 #endif 43 #ifdef CONFIG_64BIT 44 #define TLBMISS_HANDLER_SETUP() \ 45 write_c0_context((unsigned long) smp_processor_id() << 26); \ 46 back_to_back_c0_hazard(); \ 47 TLBMISS_HANDLER_SETUP_PGD(swapper_pg_dir) 48 #endif 49 50 #if defined(CONFIG_CPU_R3000) || defined(CONFIG_CPU_TX39XX) 51 52 #define ASID_INC 0x40 53 #define ASID_MASK 0xfc0 54 55 #elif defined(CONFIG_CPU_R8000) 56 57 #define ASID_INC 0x10 58 #define ASID_MASK 0xff0 59 60 #elif defined(CONFIG_CPU_RM9000) 61 62 #define ASID_INC 0x1 63 #define ASID_MASK 0xfff 64 65 /* SMTC/34K debug hack - but maybe we'll keep it */ 66 #elif defined(CONFIG_MIPS_MT_SMTC) 67 68 #define ASID_INC 0x1 69 extern unsigned long smtc_asid_mask; 70 #define ASID_MASK (smtc_asid_mask) 71 #define HW_ASID_MASK 0xff 72 /* End SMTC/34K debug hack */ 73 #else /* FIXME: not correct for R6000 */ 74 75 #define ASID_INC 0x1 76 #define ASID_MASK 0xff 77 78 #endif 79 80 #define cpu_context(cpu, mm) ((mm)->context[cpu]) 81 #define cpu_asid(cpu, mm) (cpu_context((cpu), (mm)) & ASID_MASK) 82 #define asid_cache(cpu) (cpu_data[cpu].asid_cache) 83 84 static inline void enter_lazy_tlb(struct mm_struct *mm, struct task_struct *tsk) 85 { 86 } 87 88 /* 89 * All unused by hardware upper bits will be considered 90 * as a software asid extension. 91 */ 92 #define ASID_VERSION_MASK ((unsigned long)~(ASID_MASK|(ASID_MASK-1))) 93 #define ASID_FIRST_VERSION ((unsigned long)(~ASID_VERSION_MASK) + 1) 94 95 #ifndef CONFIG_MIPS_MT_SMTC 96 /* Normal, classic MIPS get_new_mmu_context */ 97 static inline void 98 get_new_mmu_context(struct mm_struct *mm, unsigned long cpu) 99 { 100 unsigned long asid = asid_cache(cpu); 101 102 if (! ((asid += ASID_INC) & ASID_MASK) ) { 103 if (cpu_has_vtag_icache) 104 flush_icache_all(); 105 local_flush_tlb_all(); /* start new asid cycle */ 106 if (!asid) /* fix version if needed */ 107 asid = ASID_FIRST_VERSION; 108 } 109 cpu_context(cpu, mm) = asid_cache(cpu) = asid; 110 } 111 112 #else /* CONFIG_MIPS_MT_SMTC */ 113 114 #define get_new_mmu_context(mm, cpu) smtc_get_new_mmu_context((mm), (cpu)) 115 116 #endif /* CONFIG_MIPS_MT_SMTC */ 117 118 /* 119 * Initialize the context related info for a new mm_struct 120 * instance. 121 */ 122 static inline int 123 init_new_context(struct task_struct *tsk, struct mm_struct *mm) 124 { 125 int i; 126 127 for_each_online_cpu(i) 128 cpu_context(i, mm) = 0; 129 130 return 0; 131 } 132 133 static inline void switch_mm(struct mm_struct *prev, struct mm_struct *next, 134 struct task_struct *tsk) 135 { 136 unsigned int cpu = smp_processor_id(); 137 unsigned long flags; 138 #ifdef CONFIG_MIPS_MT_SMTC 139 unsigned long oldasid; 140 unsigned long mtflags; 141 int mytlb = (smtc_status & SMTC_TLB_SHARED) ? 0 : cpu_data[cpu].vpe_id; 142 local_irq_save(flags); 143 mtflags = dvpe(); 144 #else /* Not SMTC */ 145 local_irq_save(flags); 146 #endif /* CONFIG_MIPS_MT_SMTC */ 147 148 /* Check if our ASID is of an older version and thus invalid */ 149 if ((cpu_context(cpu, next) ^ asid_cache(cpu)) & ASID_VERSION_MASK) 150 get_new_mmu_context(next, cpu); 151 #ifdef CONFIG_MIPS_MT_SMTC 152 /* 153 * If the EntryHi ASID being replaced happens to be 154 * the value flagged at ASID recycling time as having 155 * an extended life, clear the bit showing it being 156 * in use by this "CPU", and if that's the last bit, 157 * free up the ASID value for use and flush any old 158 * instances of it from the TLB. 159 */ 160 oldasid = (read_c0_entryhi() & ASID_MASK); 161 if(smtc_live_asid[mytlb][oldasid]) { 162 smtc_live_asid[mytlb][oldasid] &= ~(0x1 << cpu); 163 if(smtc_live_asid[mytlb][oldasid] == 0) 164 smtc_flush_tlb_asid(oldasid); 165 } 166 /* 167 * Tread softly on EntryHi, and so long as we support 168 * having ASID_MASK smaller than the hardware maximum, 169 * make sure no "soft" bits become "hard"... 170 */ 171 write_c0_entryhi((read_c0_entryhi() & ~HW_ASID_MASK) | 172 cpu_asid(cpu, next)); 173 ehb(); /* Make sure it propagates to TCStatus */ 174 evpe(mtflags); 175 #else 176 write_c0_entryhi(cpu_asid(cpu, next)); 177 #endif /* CONFIG_MIPS_MT_SMTC */ 178 TLBMISS_HANDLER_SETUP_PGD(next->pgd); 179 180 /* 181 * Mark current->active_mm as not "active" anymore. 182 * We don't want to mislead possible IPI tlb flush routines. 183 */ 184 cpumask_clear_cpu(cpu, mm_cpumask(prev)); 185 cpumask_set_cpu(cpu, mm_cpumask(next)); 186 187 local_irq_restore(flags); 188 } 189 190 /* 191 * Destroy context related info for an mm_struct that is about 192 * to be put to rest. 193 */ 194 static inline void destroy_context(struct mm_struct *mm) 195 { 196 } 197 198 #define deactivate_mm(tsk, mm) do { } while (0) 199 200 /* 201 * After we have set current->mm to a new value, this activates 202 * the context for the new mm so we see the new mappings. 203 */ 204 static inline void 205 activate_mm(struct mm_struct *prev, struct mm_struct *next) 206 { 207 unsigned long flags; 208 unsigned int cpu = smp_processor_id(); 209 210 #ifdef CONFIG_MIPS_MT_SMTC 211 unsigned long oldasid; 212 unsigned long mtflags; 213 int mytlb = (smtc_status & SMTC_TLB_SHARED) ? 0 : cpu_data[cpu].vpe_id; 214 #endif /* CONFIG_MIPS_MT_SMTC */ 215 216 local_irq_save(flags); 217 218 /* Unconditionally get a new ASID. */ 219 get_new_mmu_context(next, cpu); 220 221 #ifdef CONFIG_MIPS_MT_SMTC 222 /* See comments for similar code above */ 223 mtflags = dvpe(); 224 oldasid = read_c0_entryhi() & ASID_MASK; 225 if(smtc_live_asid[mytlb][oldasid]) { 226 smtc_live_asid[mytlb][oldasid] &= ~(0x1 << cpu); 227 if(smtc_live_asid[mytlb][oldasid] == 0) 228 smtc_flush_tlb_asid(oldasid); 229 } 230 /* See comments for similar code above */ 231 write_c0_entryhi((read_c0_entryhi() & ~HW_ASID_MASK) | 232 cpu_asid(cpu, next)); 233 ehb(); /* Make sure it propagates to TCStatus */ 234 evpe(mtflags); 235 #else 236 write_c0_entryhi(cpu_asid(cpu, next)); 237 #endif /* CONFIG_MIPS_MT_SMTC */ 238 TLBMISS_HANDLER_SETUP_PGD(next->pgd); 239 240 /* mark mmu ownership change */ 241 cpumask_clear_cpu(cpu, mm_cpumask(prev)); 242 cpumask_set_cpu(cpu, mm_cpumask(next)); 243 244 local_irq_restore(flags); 245 } 246 247 /* 248 * If mm is currently active_mm, we can't really drop it. Instead, 249 * we will get a new one for it. 250 */ 251 static inline void 252 drop_mmu_context(struct mm_struct *mm, unsigned cpu) 253 { 254 unsigned long flags; 255 #ifdef CONFIG_MIPS_MT_SMTC 256 unsigned long oldasid; 257 /* Can't use spinlock because called from TLB flush within DVPE */ 258 unsigned int prevvpe; 259 int mytlb = (smtc_status & SMTC_TLB_SHARED) ? 0 : cpu_data[cpu].vpe_id; 260 #endif /* CONFIG_MIPS_MT_SMTC */ 261 262 local_irq_save(flags); 263 264 if (cpumask_test_cpu(cpu, mm_cpumask(mm))) { 265 get_new_mmu_context(mm, cpu); 266 #ifdef CONFIG_MIPS_MT_SMTC 267 /* See comments for similar code above */ 268 prevvpe = dvpe(); 269 oldasid = (read_c0_entryhi() & ASID_MASK); 270 if (smtc_live_asid[mytlb][oldasid]) { 271 smtc_live_asid[mytlb][oldasid] &= ~(0x1 << cpu); 272 if(smtc_live_asid[mytlb][oldasid] == 0) 273 smtc_flush_tlb_asid(oldasid); 274 } 275 /* See comments for similar code above */ 276 write_c0_entryhi((read_c0_entryhi() & ~HW_ASID_MASK) 277 | cpu_asid(cpu, mm)); 278 ehb(); /* Make sure it propagates to TCStatus */ 279 evpe(prevvpe); 280 #else /* not CONFIG_MIPS_MT_SMTC */ 281 write_c0_entryhi(cpu_asid(cpu, mm)); 282 #endif /* CONFIG_MIPS_MT_SMTC */ 283 } else { 284 /* will get a new context next time */ 285 #ifndef CONFIG_MIPS_MT_SMTC 286 cpu_context(cpu, mm) = 0; 287 #else /* SMTC */ 288 int i; 289 290 /* SMTC shares the TLB (and ASIDs) across VPEs */ 291 for_each_online_cpu(i) { 292 if((smtc_status & SMTC_TLB_SHARED) 293 || (cpu_data[i].vpe_id == cpu_data[cpu].vpe_id)) 294 cpu_context(i, mm) = 0; 295 } 296 #endif /* CONFIG_MIPS_MT_SMTC */ 297 } 298 local_irq_restore(flags); 299 } 300 301 #endif /* _ASM_MMU_CONTEXT_H */ 302