1 /* 2 * Switch a MMU context. 3 * 4 * This file is subject to the terms and conditions of the GNU General Public 5 * License. See the file "COPYING" in the main directory of this archive 6 * for more details. 7 * 8 * Copyright (C) 1996, 1997, 1998, 1999 by Ralf Baechle 9 * Copyright (C) 1999 Silicon Graphics, Inc. 10 */ 11 #ifndef _ASM_MMU_CONTEXT_H 12 #define _ASM_MMU_CONTEXT_H 13 14 #include <linux/errno.h> 15 #include <linux/sched.h> 16 #include <linux/smp.h> 17 #include <linux/slab.h> 18 #include <asm/cacheflush.h> 19 #include <asm/hazards.h> 20 #include <asm/tlbflush.h> 21 #ifdef CONFIG_MIPS_MT_SMTC 22 #include <asm/mipsmtregs.h> 23 #include <asm/smtc.h> 24 #endif /* SMTC */ 25 #include <asm-generic/mm_hooks.h> 26 27 #ifdef CONFIG_MIPS_PGD_C0_CONTEXT 28 29 #define TLBMISS_HANDLER_SETUP_PGD(pgd) \ 30 tlbmiss_handler_setup_pgd((unsigned long)(pgd)) 31 32 extern void tlbmiss_handler_setup_pgd(unsigned long pgd); 33 34 #define TLBMISS_HANDLER_SETUP() \ 35 do { \ 36 TLBMISS_HANDLER_SETUP_PGD(swapper_pg_dir); \ 37 write_c0_xcontext((unsigned long) smp_processor_id() << 51); \ 38 } while (0) 39 40 #else /* CONFIG_MIPS_PGD_C0_CONTEXT: using pgd_current*/ 41 42 /* 43 * For the fast tlb miss handlers, we keep a per cpu array of pointers 44 * to the current pgd for each processor. Also, the proc. id is stuffed 45 * into the context register. 46 */ 47 extern unsigned long pgd_current[]; 48 49 #define TLBMISS_HANDLER_SETUP_PGD(pgd) \ 50 pgd_current[smp_processor_id()] = (unsigned long)(pgd) 51 52 #ifdef CONFIG_32BIT 53 #define TLBMISS_HANDLER_SETUP() \ 54 write_c0_context((unsigned long) smp_processor_id() << 25); \ 55 back_to_back_c0_hazard(); \ 56 TLBMISS_HANDLER_SETUP_PGD(swapper_pg_dir) 57 #endif 58 #ifdef CONFIG_64BIT 59 #define TLBMISS_HANDLER_SETUP() \ 60 write_c0_context((unsigned long) smp_processor_id() << 26); \ 61 back_to_back_c0_hazard(); \ 62 TLBMISS_HANDLER_SETUP_PGD(swapper_pg_dir) 63 #endif 64 #endif /* CONFIG_MIPS_PGD_C0_CONTEXT*/ 65 #if defined(CONFIG_CPU_R3000) || defined(CONFIG_CPU_TX39XX) 66 67 #define ASID_INC 0x40 68 #define ASID_MASK 0xfc0 69 70 #elif defined(CONFIG_CPU_R8000) 71 72 #define ASID_INC 0x10 73 #define ASID_MASK 0xff0 74 75 #elif defined(CONFIG_CPU_RM9000) 76 77 #define ASID_INC 0x1 78 #define ASID_MASK 0xfff 79 80 /* SMTC/34K debug hack - but maybe we'll keep it */ 81 #elif defined(CONFIG_MIPS_MT_SMTC) 82 83 #define ASID_INC 0x1 84 extern unsigned long smtc_asid_mask; 85 #define ASID_MASK (smtc_asid_mask) 86 #define HW_ASID_MASK 0xff 87 /* End SMTC/34K debug hack */ 88 #else /* FIXME: not correct for R6000 */ 89 90 #define ASID_INC 0x1 91 #define ASID_MASK 0xff 92 93 #endif 94 95 #define cpu_context(cpu, mm) ((mm)->context.asid[cpu]) 96 #define cpu_asid(cpu, mm) (cpu_context((cpu), (mm)) & ASID_MASK) 97 #define asid_cache(cpu) (cpu_data[cpu].asid_cache) 98 99 static inline void enter_lazy_tlb(struct mm_struct *mm, struct task_struct *tsk) 100 { 101 } 102 103 /* 104 * All unused by hardware upper bits will be considered 105 * as a software asid extension. 106 */ 107 #define ASID_VERSION_MASK ((unsigned long)~(ASID_MASK|(ASID_MASK-1))) 108 #define ASID_FIRST_VERSION ((unsigned long)(~ASID_VERSION_MASK) + 1) 109 110 #ifndef CONFIG_MIPS_MT_SMTC 111 /* Normal, classic MIPS get_new_mmu_context */ 112 static inline void 113 get_new_mmu_context(struct mm_struct *mm, unsigned long cpu) 114 { 115 unsigned long asid = asid_cache(cpu); 116 117 if (! ((asid += ASID_INC) & ASID_MASK) ) { 118 if (cpu_has_vtag_icache) 119 flush_icache_all(); 120 local_flush_tlb_all(); /* start new asid cycle */ 121 if (!asid) /* fix version if needed */ 122 asid = ASID_FIRST_VERSION; 123 } 124 cpu_context(cpu, mm) = asid_cache(cpu) = asid; 125 } 126 127 #else /* CONFIG_MIPS_MT_SMTC */ 128 129 #define get_new_mmu_context(mm, cpu) smtc_get_new_mmu_context((mm), (cpu)) 130 131 #endif /* CONFIG_MIPS_MT_SMTC */ 132 133 /* 134 * Initialize the context related info for a new mm_struct 135 * instance. 136 */ 137 static inline int 138 init_new_context(struct task_struct *tsk, struct mm_struct *mm) 139 { 140 int i; 141 142 for_each_online_cpu(i) 143 cpu_context(i, mm) = 0; 144 145 return 0; 146 } 147 148 static inline void switch_mm(struct mm_struct *prev, struct mm_struct *next, 149 struct task_struct *tsk) 150 { 151 unsigned int cpu = smp_processor_id(); 152 unsigned long flags; 153 #ifdef CONFIG_MIPS_MT_SMTC 154 unsigned long oldasid; 155 unsigned long mtflags; 156 int mytlb = (smtc_status & SMTC_TLB_SHARED) ? 0 : cpu_data[cpu].vpe_id; 157 local_irq_save(flags); 158 mtflags = dvpe(); 159 #else /* Not SMTC */ 160 local_irq_save(flags); 161 #endif /* CONFIG_MIPS_MT_SMTC */ 162 163 /* Check if our ASID is of an older version and thus invalid */ 164 if ((cpu_context(cpu, next) ^ asid_cache(cpu)) & ASID_VERSION_MASK) 165 get_new_mmu_context(next, cpu); 166 #ifdef CONFIG_MIPS_MT_SMTC 167 /* 168 * If the EntryHi ASID being replaced happens to be 169 * the value flagged at ASID recycling time as having 170 * an extended life, clear the bit showing it being 171 * in use by this "CPU", and if that's the last bit, 172 * free up the ASID value for use and flush any old 173 * instances of it from the TLB. 174 */ 175 oldasid = (read_c0_entryhi() & ASID_MASK); 176 if(smtc_live_asid[mytlb][oldasid]) { 177 smtc_live_asid[mytlb][oldasid] &= ~(0x1 << cpu); 178 if(smtc_live_asid[mytlb][oldasid] == 0) 179 smtc_flush_tlb_asid(oldasid); 180 } 181 /* 182 * Tread softly on EntryHi, and so long as we support 183 * having ASID_MASK smaller than the hardware maximum, 184 * make sure no "soft" bits become "hard"... 185 */ 186 write_c0_entryhi((read_c0_entryhi() & ~HW_ASID_MASK) | 187 cpu_asid(cpu, next)); 188 ehb(); /* Make sure it propagates to TCStatus */ 189 evpe(mtflags); 190 #else 191 write_c0_entryhi(cpu_asid(cpu, next)); 192 #endif /* CONFIG_MIPS_MT_SMTC */ 193 TLBMISS_HANDLER_SETUP_PGD(next->pgd); 194 195 /* 196 * Mark current->active_mm as not "active" anymore. 197 * We don't want to mislead possible IPI tlb flush routines. 198 */ 199 cpumask_clear_cpu(cpu, mm_cpumask(prev)); 200 cpumask_set_cpu(cpu, mm_cpumask(next)); 201 202 local_irq_restore(flags); 203 } 204 205 /* 206 * Destroy context related info for an mm_struct that is about 207 * to be put to rest. 208 */ 209 static inline void destroy_context(struct mm_struct *mm) 210 { 211 } 212 213 #define deactivate_mm(tsk, mm) do { } while (0) 214 215 /* 216 * After we have set current->mm to a new value, this activates 217 * the context for the new mm so we see the new mappings. 218 */ 219 static inline void 220 activate_mm(struct mm_struct *prev, struct mm_struct *next) 221 { 222 unsigned long flags; 223 unsigned int cpu = smp_processor_id(); 224 225 #ifdef CONFIG_MIPS_MT_SMTC 226 unsigned long oldasid; 227 unsigned long mtflags; 228 int mytlb = (smtc_status & SMTC_TLB_SHARED) ? 0 : cpu_data[cpu].vpe_id; 229 #endif /* CONFIG_MIPS_MT_SMTC */ 230 231 local_irq_save(flags); 232 233 /* Unconditionally get a new ASID. */ 234 get_new_mmu_context(next, cpu); 235 236 #ifdef CONFIG_MIPS_MT_SMTC 237 /* See comments for similar code above */ 238 mtflags = dvpe(); 239 oldasid = read_c0_entryhi() & ASID_MASK; 240 if(smtc_live_asid[mytlb][oldasid]) { 241 smtc_live_asid[mytlb][oldasid] &= ~(0x1 << cpu); 242 if(smtc_live_asid[mytlb][oldasid] == 0) 243 smtc_flush_tlb_asid(oldasid); 244 } 245 /* See comments for similar code above */ 246 write_c0_entryhi((read_c0_entryhi() & ~HW_ASID_MASK) | 247 cpu_asid(cpu, next)); 248 ehb(); /* Make sure it propagates to TCStatus */ 249 evpe(mtflags); 250 #else 251 write_c0_entryhi(cpu_asid(cpu, next)); 252 #endif /* CONFIG_MIPS_MT_SMTC */ 253 TLBMISS_HANDLER_SETUP_PGD(next->pgd); 254 255 /* mark mmu ownership change */ 256 cpumask_clear_cpu(cpu, mm_cpumask(prev)); 257 cpumask_set_cpu(cpu, mm_cpumask(next)); 258 259 local_irq_restore(flags); 260 } 261 262 /* 263 * If mm is currently active_mm, we can't really drop it. Instead, 264 * we will get a new one for it. 265 */ 266 static inline void 267 drop_mmu_context(struct mm_struct *mm, unsigned cpu) 268 { 269 unsigned long flags; 270 #ifdef CONFIG_MIPS_MT_SMTC 271 unsigned long oldasid; 272 /* Can't use spinlock because called from TLB flush within DVPE */ 273 unsigned int prevvpe; 274 int mytlb = (smtc_status & SMTC_TLB_SHARED) ? 0 : cpu_data[cpu].vpe_id; 275 #endif /* CONFIG_MIPS_MT_SMTC */ 276 277 local_irq_save(flags); 278 279 if (cpumask_test_cpu(cpu, mm_cpumask(mm))) { 280 get_new_mmu_context(mm, cpu); 281 #ifdef CONFIG_MIPS_MT_SMTC 282 /* See comments for similar code above */ 283 prevvpe = dvpe(); 284 oldasid = (read_c0_entryhi() & ASID_MASK); 285 if (smtc_live_asid[mytlb][oldasid]) { 286 smtc_live_asid[mytlb][oldasid] &= ~(0x1 << cpu); 287 if(smtc_live_asid[mytlb][oldasid] == 0) 288 smtc_flush_tlb_asid(oldasid); 289 } 290 /* See comments for similar code above */ 291 write_c0_entryhi((read_c0_entryhi() & ~HW_ASID_MASK) 292 | cpu_asid(cpu, mm)); 293 ehb(); /* Make sure it propagates to TCStatus */ 294 evpe(prevvpe); 295 #else /* not CONFIG_MIPS_MT_SMTC */ 296 write_c0_entryhi(cpu_asid(cpu, mm)); 297 #endif /* CONFIG_MIPS_MT_SMTC */ 298 } else { 299 /* will get a new context next time */ 300 #ifndef CONFIG_MIPS_MT_SMTC 301 cpu_context(cpu, mm) = 0; 302 #else /* SMTC */ 303 int i; 304 305 /* SMTC shares the TLB (and ASIDs) across VPEs */ 306 for_each_online_cpu(i) { 307 if((smtc_status & SMTC_TLB_SHARED) 308 || (cpu_data[i].vpe_id == cpu_data[cpu].vpe_id)) 309 cpu_context(i, mm) = 0; 310 } 311 #endif /* CONFIG_MIPS_MT_SMTC */ 312 } 313 local_irq_restore(flags); 314 } 315 316 #endif /* _ASM_MMU_CONTEXT_H */ 317