1 /* 2 * Switch a MMU context. 3 * 4 * This file is subject to the terms and conditions of the GNU General Public 5 * License. See the file "COPYING" in the main directory of this archive 6 * for more details. 7 * 8 * Copyright (C) 1996, 1997, 1998, 1999 by Ralf Baechle 9 * Copyright (C) 1999 Silicon Graphics, Inc. 10 */ 11 #ifndef _ASM_MMU_CONTEXT_H 12 #define _ASM_MMU_CONTEXT_H 13 14 #include <linux/errno.h> 15 #include <linux/sched.h> 16 #include <linux/smp.h> 17 #include <linux/slab.h> 18 #include <asm/cacheflush.h> 19 #include <asm/dsemul.h> 20 #include <asm/hazards.h> 21 #include <asm/tlbflush.h> 22 #include <asm-generic/mm_hooks.h> 23 24 #define htw_set_pwbase(pgd) \ 25 do { \ 26 if (cpu_has_htw) { \ 27 write_c0_pwbase(pgd); \ 28 back_to_back_c0_hazard(); \ 29 } \ 30 } while (0) 31 32 #define TLBMISS_HANDLER_SETUP_PGD(pgd) \ 33 do { \ 34 extern void tlbmiss_handler_setup_pgd(unsigned long); \ 35 tlbmiss_handler_setup_pgd((unsigned long)(pgd)); \ 36 htw_set_pwbase((unsigned long)pgd); \ 37 } while (0) 38 39 #ifdef CONFIG_MIPS_PGD_C0_CONTEXT 40 41 #define TLBMISS_HANDLER_RESTORE() \ 42 write_c0_xcontext((unsigned long) smp_processor_id() << \ 43 SMP_CPUID_REGSHIFT) 44 45 #define TLBMISS_HANDLER_SETUP() \ 46 do { \ 47 TLBMISS_HANDLER_SETUP_PGD(swapper_pg_dir); \ 48 TLBMISS_HANDLER_RESTORE(); \ 49 } while (0) 50 51 #else /* !CONFIG_MIPS_PGD_C0_CONTEXT: using pgd_current*/ 52 53 /* 54 * For the fast tlb miss handlers, we keep a per cpu array of pointers 55 * to the current pgd for each processor. Also, the proc. id is stuffed 56 * into the context register. 57 */ 58 extern unsigned long pgd_current[]; 59 60 #define TLBMISS_HANDLER_RESTORE() \ 61 write_c0_context((unsigned long) smp_processor_id() << \ 62 SMP_CPUID_REGSHIFT) 63 64 #define TLBMISS_HANDLER_SETUP() \ 65 TLBMISS_HANDLER_RESTORE(); \ 66 back_to_back_c0_hazard(); \ 67 TLBMISS_HANDLER_SETUP_PGD(swapper_pg_dir) 68 #endif /* CONFIG_MIPS_PGD_C0_CONTEXT*/ 69 70 /* 71 * All unused by hardware upper bits will be considered 72 * as a software asid extension. 73 */ 74 static unsigned long asid_version_mask(unsigned int cpu) 75 { 76 unsigned long asid_mask = cpu_asid_mask(&cpu_data[cpu]); 77 78 return ~(asid_mask | (asid_mask - 1)); 79 } 80 81 static unsigned long asid_first_version(unsigned int cpu) 82 { 83 return ~asid_version_mask(cpu) + 1; 84 } 85 86 #define cpu_context(cpu, mm) ((mm)->context.asid[cpu]) 87 #define asid_cache(cpu) (cpu_data[cpu].asid_cache) 88 #define cpu_asid(cpu, mm) \ 89 (cpu_context((cpu), (mm)) & cpu_asid_mask(&cpu_data[cpu])) 90 91 static inline void enter_lazy_tlb(struct mm_struct *mm, struct task_struct *tsk) 92 { 93 } 94 95 96 /* Normal, classic MIPS get_new_mmu_context */ 97 static inline void 98 get_new_mmu_context(struct mm_struct *mm, unsigned long cpu) 99 { 100 extern void kvm_local_flush_tlb_all(void); 101 unsigned long asid = asid_cache(cpu); 102 103 if (!((asid += cpu_asid_inc()) & cpu_asid_mask(&cpu_data[cpu]))) { 104 if (cpu_has_vtag_icache) 105 flush_icache_all(); 106 #ifdef CONFIG_KVM 107 kvm_local_flush_tlb_all(); /* start new asid cycle */ 108 #else 109 local_flush_tlb_all(); /* start new asid cycle */ 110 #endif 111 if (!asid) /* fix version if needed */ 112 asid = asid_first_version(cpu); 113 } 114 115 cpu_context(cpu, mm) = asid_cache(cpu) = asid; 116 } 117 118 /* 119 * Initialize the context related info for a new mm_struct 120 * instance. 121 */ 122 static inline int 123 init_new_context(struct task_struct *tsk, struct mm_struct *mm) 124 { 125 int i; 126 127 for_each_possible_cpu(i) 128 cpu_context(i, mm) = 0; 129 130 atomic_set(&mm->context.fp_mode_switching, 0); 131 132 mm->context.bd_emupage_allocmap = NULL; 133 spin_lock_init(&mm->context.bd_emupage_lock); 134 init_waitqueue_head(&mm->context.bd_emupage_queue); 135 136 return 0; 137 } 138 139 static inline void switch_mm(struct mm_struct *prev, struct mm_struct *next, 140 struct task_struct *tsk) 141 { 142 unsigned int cpu = smp_processor_id(); 143 unsigned long flags; 144 local_irq_save(flags); 145 146 htw_stop(); 147 /* Check if our ASID is of an older version and thus invalid */ 148 if ((cpu_context(cpu, next) ^ asid_cache(cpu)) & asid_version_mask(cpu)) 149 get_new_mmu_context(next, cpu); 150 write_c0_entryhi(cpu_asid(cpu, next)); 151 TLBMISS_HANDLER_SETUP_PGD(next->pgd); 152 153 /* 154 * Mark current->active_mm as not "active" anymore. 155 * We don't want to mislead possible IPI tlb flush routines. 156 */ 157 cpumask_clear_cpu(cpu, mm_cpumask(prev)); 158 cpumask_set_cpu(cpu, mm_cpumask(next)); 159 htw_start(); 160 161 local_irq_restore(flags); 162 } 163 164 /* 165 * Destroy context related info for an mm_struct that is about 166 * to be put to rest. 167 */ 168 static inline void destroy_context(struct mm_struct *mm) 169 { 170 dsemul_mm_cleanup(mm); 171 } 172 173 #define deactivate_mm(tsk, mm) do { } while (0) 174 175 /* 176 * After we have set current->mm to a new value, this activates 177 * the context for the new mm so we see the new mappings. 178 */ 179 static inline void 180 activate_mm(struct mm_struct *prev, struct mm_struct *next) 181 { 182 unsigned long flags; 183 unsigned int cpu = smp_processor_id(); 184 185 local_irq_save(flags); 186 187 htw_stop(); 188 /* Unconditionally get a new ASID. */ 189 get_new_mmu_context(next, cpu); 190 191 write_c0_entryhi(cpu_asid(cpu, next)); 192 TLBMISS_HANDLER_SETUP_PGD(next->pgd); 193 194 /* mark mmu ownership change */ 195 cpumask_clear_cpu(cpu, mm_cpumask(prev)); 196 cpumask_set_cpu(cpu, mm_cpumask(next)); 197 htw_start(); 198 199 local_irq_restore(flags); 200 } 201 202 /* 203 * If mm is currently active_mm, we can't really drop it. Instead, 204 * we will get a new one for it. 205 */ 206 static inline void 207 drop_mmu_context(struct mm_struct *mm, unsigned cpu) 208 { 209 unsigned long flags; 210 211 local_irq_save(flags); 212 htw_stop(); 213 214 if (cpumask_test_cpu(cpu, mm_cpumask(mm))) { 215 get_new_mmu_context(mm, cpu); 216 write_c0_entryhi(cpu_asid(cpu, mm)); 217 } else { 218 /* will get a new context next time */ 219 cpu_context(cpu, mm) = 0; 220 } 221 htw_start(); 222 local_irq_restore(flags); 223 } 224 225 #endif /* _ASM_MMU_CONTEXT_H */ 226